DETAILED ACTION
This action is in response to the amendment 12/03/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 8 and 15 – 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2004/0008016; (hereinafter Sutardja).
Regarding claim 1, Sutardja [e.g. Figs. 1 – 7] discloses an apparatus comprising: switch control circuitry [e.g. Fig. 2; 112a-112b]; and mode control circuitry [e.g. Fig. 2; 102] configured to, in response to a determination that the switch control circuitry is to be operated in a fixed frequency mode [e.g. Figs. 5 - 6; PWM control 306 (S3)]: signal the switch control circuitry to transition to an on-time control mode [e.g. Figs. 5 – 6; 304 (S2)] to transmit an on-time control pulse [e.g. output of 112a / 112b; paragraphs 079 recites “The adaptive multi-mode control system 300 may switch to voltage-mode adaptive hysteretic control, S2, 304 when the regulated output voltage 320 is within a range of values such as VH3 and VL3. In voltage-mode adaptive hysteretic control, S2, 304 the maximum on-time and the maximum off-time under hysteretic control are limited to reduce the rate at which energy is transferred to the regulated output, reducing the amplitude of ringing about the steady-state value”]; and in response to determining that the switch control circuitry has transitioned to the on-time control mode [e.g. Fig. 5-6; 306 (S2)], signal the switch control circuitry to transmit a fixed frequency mode clock signal [e.g. PWM signal (constant frequency)] in the fixed frequency mode [e.g. paragraph 080 recites “The adaptive multi-mode control system 300 may switch to voltage-mode or current-mode pulse-width-modulation (PWM) control, S3, 306 as the ringing of the regulated output voltage decreases. During voltage-mode PWM control, S3, 306 the output regulator operates at a constant frequency and regulates the output voltage by controlling the duty cycle at which energy is transferred to the output. Switching to voltage-mode PWM control, S3, 306 may be based on the output current of the output regulator, the output voltage, and the voltage range over which the output voltage varies”].
Regarding claim 2, Sutardja [e.g. Figs. 1 – 7] discloses further comprising switch circuitry [e.g. 114a-114b], wherein: the switch circuitry includes a low side switch [e.g. 114b]; and the low side switch is controlled by the on-time control pulse [e.g. output of 112b] in the on-time control mode and by the fixed frequency mode clock signal [e.g. output of 112b] in the fixed frequency mode.
Regarding claim 3, Sutardja [e.g. Figs. 1 – 7] discloses wherein the switch control circuitry drives the switch circuitry [e.g. 112a-112b drives 114a-114b”].
Regarding claim 4, Sutardja [e.g. Figs. 1 – 7] discloses wherein the on-time control pulse is generated based on a comparison of an output voltage of the apparatus and a reference voltage [e.g. paragraph 073 recites “FIG. 3 shows an aspect of an operating mode of the voltage converter 100. At block 150, the regulated output is sensed and compared to a reference”].
Regarding claim 5, Sutardja [e.g. Figs. 1 – 7] discloses wherein the mode control circuitry is configured to operate in a hysteretic mode [e.g. Fig. 5 - 6; 302 (S1)] prior to transition to the on-time control mode [e.g. 304 (S2)].
Regarding claim 6, Sutardja [e.g. Figs. 1 – 7 and 12A] discloses wherein the switch is a transistor [e.g. Fig. 12A; Q5].
Regarding claim 7, Sutardja [e.g. Figs. 1 – 7] discloses wherein the switch circuitry further includes a high side switch [e.g. 114a].
Regarding claim 8, Sutardja [e.g. Figs. 1 – 7] discloses an apparatus comprising: switching circuitry [e.g. Fig. 1; power stage 20; paragraph 060 recites “The power regulator 10 may employ any topology such as buck …”]; an inductor [e.g. inductor at filter 24 well known of buck converters] coupled to the switching circuitry and an output [e.g. Vout]; a capacitor [e.g. capacitor at filter 24 well known of buck converters] coupled to the output; buck controller circuitry [e.g. Fig. 2; 112a-112b, 114a]; and mode control circuitry [e.g. Fig. 2; 102] configured to: in response to a determination that the buck controller circuitry is to be operated in a fixed frequency mode [e.g. Figs. 5 - 6; PWM control 306 (S3)], cause the buck controller circuitry to operate in an on-time control mode [e.g. Figs. 5 – 6; 304 (S2); paragraphs 079 recites “The adaptive multi-mode control system 300 may switch to voltage-mode adaptive hysteretic control, S2, 304 when the regulated output voltage 320 is within a range of values such as VH3 and VL3. In voltage-mode adaptive hysteretic control, S2, 304 the maximum on-time and the maximum off-time under hysteretic control are limited to reduce the rate at which energy is transferred to the regulated output, reducing the amplitude of ringing about the steady-state value”]; and in response to the buck controller circuitry operating in the on-time control mode [e.g. Fig. 5; 304], cause the buck controller circuitry to operate in the fixed frequency mode [e.g. paragraph 080 recites “The adaptive multi-mode control system 300 may switch to voltage-mode or current-mode pulse-width-modulation (PWM) control, S3, 306 as the ringing of the regulated output voltage decreases. During voltage-mode PWM control, S3, 306 the output regulator operates at a constant frequency and regulates the output voltage by controlling the duty cycle at which energy is transferred to the output. Switching to voltage-mode PWM control, S3, 306 may be based on the output current of the output regulator, the output voltage, and the voltage range over which the output voltage varies”].
Regarding claim 15, Sutardja [e.g. Figs. 1 – 7] discloses a method comprising, in response to a determination to operate switch control circuitry of buck converter circuitry [e.g. Fig. 1; power stage 20; paragraph 060 recites “The power regulator 10 may employ any topology such as buck …”] in a fixed frequency mode [e.g. Figs. 5 - 6; PWM control 306 (S3)]: signaling switch control circuitry [e.g. Fig. 2; 112a-112b] to transition switch control circuitry to an on-time control mode [e.g. Figs. 5 – 6; 304 (S2)] to transmit an on-time control pulse signal [e.g. output of 112a / 112b] to a switch [e.g. 114a-114b; paragraphs 079 recites “The adaptive multi-mode control system 300 may switch to voltage-mode adaptive hysteretic control, S2, 304 when the regulated output voltage 320 is within a range of values such as VH3 and VL3. In voltage-mode adaptive hysteretic control, S2, 304 the maximum on-time and the maximum off-time under hysteretic control are limited to reduce the rate at which energy is transferred to the regulated output, reducing the amplitude of ringing about the steady-state value”]; determining that the switch control circuitry has transitioned to the on-time control mode [e.g. 304 (S3)]; and in response to determining that the switch control circuitry has transitioned to the on-time control mode [e.g. Fig. 5; 304 (S3)], signaling the switch control circuitry to transmit a fixed frequency mode clock signal [e.g. PWM signal (constant frequency)] to the switch in the fixed frequency mode [e.g. paragraph 080 recites “The adaptive multi-mode control system 300 may switch to voltage-mode or current-mode pulse-width-modulation (PWM) control, S3, 306 as the ringing of the regulated output voltage decreases. During voltage-mode PWM control, S3, 306 the output regulator operates at a constant frequency and regulates the output voltage by controlling the duty cycle at which energy is transferred to the output. Switching to voltage-mode PWM control, S3, 306 may be based on the output current of the output regulator, the output voltage, and the voltage range over which the output voltage varies”].
Regarding claim 16, Sutardja [e.g. Fig. 12a; paragraph 094 recites “The power array 500 may be included in a power regulator such as power regulator 10”] discloses wherein the switch is a low side switch [e.g. Q5] of the buck converter circuitry [e.g. paragraph 095 recites “The switch arrays 502a and 502b may be connected as any topology such as buck”].
Regarding claim 17, Sutardja [e.g. Figs. 1 – 7] discloses further comprising driving switch circuitry [e.g. 114a-114b] of the buck converter circuitry using the switch control circuitry drives buck converter circuitry.
Regarding claim 18, Sutardja [e.g. Figs. 1 – 7] discloses further comprising generating the on-time control pulse based on a comparison of an output voltage of the buck converter circuitry and a reference voltage [e.g. paragraph 073 recites “FIG. 3 shows an aspect of an operating mode of the voltage converter 100. At block 150, the regulated output is sensed and compared to a reference”].
Regarding claim 19, Sutardja [e.g. Figs. 1 – 7] discloses further comprising controlling the switch control circuitry to operate in a hysteretic mode [e.g. Fig. 5 - 6; 302 (S1)] prior to transitioning to the on-time control mode [e.g. 304 (S2)].
Regarding claim 20, Sutardja [e.g. Figs. 1 – 7] fails to disclose wherein signaling the switch control circuitry to transmit the fixed frequency mode clock signal includes signaling the switch control circuitry to transmit the fixed frequency mode clock signal after at least one of: a switching frequency of the switch control circuitry has been adapted to a target switching frequency; a ramp peak value of the switch control circuitry has settled; or the switch control circuitry is at a start of a switch period.
Higashi [e.g. Figs. 1 and 10] teaches wherein signaling the switch control circuitry to transmit the fixed frequency mode clock signal [e.g. PWM] includes signaling the switch control circuitry to transmit the fixed frequency mode clock signal after at least one of: a switching frequency of the switch control circuitry has been adapted to a target switching frequency [e.g. Fig. 10; 100Khz]; a ramp peak value of the switch control circuitry has settled [e.g. Fig. 10, inductor current peak]; or the switch control circuitry is at a start of a switch period [e.g. Fig. 10; at lower peak of inductor current].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Sutardja by wherein signaling the switch control circuitry to transmit the fixed frequency mode clock signal includes signaling the switch control circuitry to transmit the fixed frequency mode clock signal after at least one of: a switching frequency of the switch control circuitry has been adapted to a target switching frequency; a ramp peak value of the switch control circuitry has settled; or the switch control circuitry is at a start of a switch periodas taught by Higashi in order of being able to suppress fluctuation of the output voltage, and possible to output a constant voltage to the load in a stable manner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sutardja in view of US Pub. No. 2018/0019654; (hereinafter Higashi).
Regarding claim 9, Sutardja fails to disclose wherein the mode control circuitry is configured to cause the buck controller circuitry to operate in the fixed frequency mode after a determination that a switching frequency of the buck controller circuitry has been adapted to a target switching frequency.
Higashi [e.g. Figs. 1 and 4] teaches wherein the mode control circuitry [e.g. 25] is configured to cause the buck controller circuitry to operate in the fixed frequency mode [e.g. PWM signal at constant duty ratio] after a determination that a switching frequency of the buck controller circuitry has been adapted to a target switching frequency [e.g. 100Khz].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Sutardja by wherein the mode control circuitry is configured to cause the buck controller circuitry to operate in the fixed frequency mode after a determination that a switching frequency of the buck controller circuitry has been adapted to a target switching frequency as taught by Higashi in order of being able to quickly suppress fluctuation in the output voltage.
Regarding claim 10, Sutardja fails to disclose wherein the mode control circuitry is configured to cause the buck controller circuitry to operate in the fixed frequency mode after a determination that a ramp peak value of the buck controller circuitry has settled.
Higashi [e.g. Figs. 1 and 10] teaches wherein the mode control circuitry is configured to cause the buck controller circuitry to operate in the fixed frequency mode [e.g. Fig. 10; PWM] after a determination that a ramp peak value of the buck controller circuitry has settled [e.g. inductor current].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Sutardja by wherein the mode control circuitry is configured to cause the buck controller circuitry to operate in the fixed frequency mode after a determination that a ramp peak value of the buck controller circuitry has settled as taught by Higashi in order of being able to suppress fluctuation of the output voltage, and possible to output a constant voltage to the load in a stable manner.
Regarding claim 11, Sutardja fails to disclose wherein the mode control circuitry is configured to cause the buck controller circuitry to operate in the fixed frequency mode after a determination that the buck controller circuitry is at a start of a switch period.
Higashi [e.g. Figs. 1 and 10] teaches wherein the mode control circuitry is configured to cause the buck controller circuitry to operate in the fixed frequency mode [e.g. Fig. 10; PWM] after a determination that the buck controller circuitry is at a start of a switch period [e.g. Fig. 10; at lower peak of inductor current].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Sutardja by wherein the mode control circuitry is configured to cause the buck controller circuitry to operate in the fixed frequency mode after a determination that the buck controller circuitry is at a start of a switch period as taught by Higashi in order of being able to suppress fluctuation of the output voltage, and possible to output a constant voltage to the load in a stable manner.
Regarding claim 12, Sutardja fails to disclose wherein the mode control circuitry is to cause the buck controller circuitry to operate in the fixed frequency mode after: a switching frequency of the buck controller circuitry has been adapted to a target switching frequency; a ramp peak value of the buck controller circuitry has settled; and the buck controller circuitry is at a start of a switch period.
Higashi [e.g. Figs. 1 and 10] teaches wherein the mode control circuitry is to cause the buck controller circuitry to operate in the fixed frequency mode [e.g. PWM] after: a switching frequency of the buck controller circuitry has been adapted to a target switching frequency [e.g. Fig. 10; 100Khz]; a ramp peak value of the buck controller circuitry has settled [e.g. Fig. 10, inductor current peak]; and the buck controller circuitry is at a start of a switch period [e.g. Fig. 10; at lower peak of inductor current].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Sutardja by wherein the mode control circuitry is to cause the buck controller circuitry to operate in the fixed frequency mode after: a switching frequency of the buck controller circuitry has been adapted to a target switching frequency; a ramp peak value of the buck controller circuitry has settled; and the buck controller circuitry is at a start of a switch period as taught by Higashi in order of being able to suppress fluctuation of the output voltage, and possible to output a constant voltage to the load in a stable manner.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the arguments does not rely on the new ground of rejection.
Allowable Subject Matter
Claims 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 13 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the mode control circuitry is to cause the buck controller circuitry to operate in on-time control mode after a determination that an on-time generator has been adapted to a length of a high-side switch period”.
The primary reason for the indication of the allowability of claim 14 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further including a buck timer, wherein the mode control circuitry is to cause the buck controller circuitry to operate in on-time control mode after a determination that the buck timer has been adapted to generate a time period of a cycle of the fixed frequency mode.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838