DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
In light of applicant’s amendments, the previous claim objections are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 7 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 4 recites the limitation “the device.” This limitation lacks antecedent basis rendering it indefinite. For claim interpretation purposes this is considered as attempting to depend on the limitation “a processing device” found in claim 1 line 7 (where the recited “a processing device” limitation would need to precede the claimed “the device” limitation in the claim to be properly referred to).
Claims 7 and 8 depend on indefinite claim 1 and are therefore also indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
Determining the scope and contents of the prior art.
Ascertaining the differences between the prior art and the claims at issue.
Resolving the level of ordinary skill in the pertinent art.
Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 9 and 15 are rejected under 35 U.S.C. 103(a) as being unpatentable over Mittal et al. (hereinafter Mittal, US 20190243695) in view of Subbiah et al. (hereinafter Subbiah, US 2020/0394143).
Regarding claim 1, Mittal discloses:
an apparatus, comprising:
a first interface configured to communicate storage access messages in a computer network, wherein the first interface is a network interface ((see at least Fig. 2 and 3 and ph. [0037] – [0073] for the message passing interfaces that allow to connect to storage devices and, in particular see at least that ph. [0052] establishes the storage devices as external to the host devices/systems, where the data orchestrator communicates with the peripheral device(s) over the peripheral interconnect (acts as an interface between host system and Storage Device(s) and Peripheral Devices, providing communication using message passing interface) without assistance from the host system (i.e. it’s not part of the host system and therefore it/they are networked components relative to each other));
a second interface connectable to an external processor outside of the device (see at least Fig. 2 and 3 and ph. [0037] – [0073], with at least ph. [0052] in particular for the peripheral interconnect that can connected to the data orchestrators (processors) of the storage devices), wherein the second interface is adapted to operate on a peripheral bus (see at least ph. [0021] for peripheral interconnect (described as an input/output bus) used as part of the message passing interface used and implemented throughout and particularly referenced in at least ph. [0052]);
a random-access memory (see at least Fig. 1 and ph. [0026] – [0036] for the memory sub-system, where in particular at least ph. [0026] discloses the memory sub-system 110, that may be implemented utilizing various types of RAM, (e.g. DIMM, NVDIMM …));
a processing device (see at least Fig. 1 and ph. [0026] – [0036] (with particular attention to at least ph. [0027]) for processor(s) used to power the processing of the system); and
a storage system having a local memory (see at least Fig. 1 – 3 and ph. [0026] – [0075] where in particular ph. [0032] discloses the local memory 119 of the system disclosed) and having a storage capacity accessible via a network storage service over the first interface (see at least Fig. 1 – 3 and ph. [0026] – [0075] where in particular at least ph. [0073] discloses that over the message passing interface (including an example of said first interface) communicates data over networks / networked components and that this allows access to the storage devices with their external (i.e. networked) storage provided to the system and the memory systems in at least ph. [0026]); and
an interconnect configured to provide, responsive to the storage access messages, a plurality of connections among the storage system, the random-access memory, the processing device, and the external processor (see at least Fig. 2, 3 and 4 and ph. [0037] – [0073], [0075] and ph. [0090] and in particular ph. [0072] and [0073] that discloses the switch fabric(s) 215 as a type of communication messaging bus that can connect to the storage devices and the host devices/systems and as per at least Fig. 2 and ph. [0026] and [0027] connect these devices/systems with their memories, storage and processors/processing devices and as per at least Fig. 4 and ph. [0075] the features of Fig. 2 and 3 can be implemented in such a combination that a host system – storage device system of Fig. 2 may be implemented in combination with the system of Fig. 3 (“the system of FIG. 4 can be implemented using the computing systems of FIG. 1, 2 *and/or* 3, presented in ph. [0075]), where the inclusion of and/or indicated combinations of the disclosed systems of the other figures as viable embodiments so that the interconnects/fabrics of at least Fig. 3 and its respectively cited paragraphs above will provide the messaging to the disclosed and cited components of the memories, storage devices and processing devices/processors in Fig. 1 2 and their disclosed and cited paragraphs above), wherein the interconnect includes a bus switch and each of the plurality of connections is a functioning bus connection (see at least Fig. 2, 3 and 4 and ph. [0037] – [0073], [0075] wherein in particular Fig. 3 and ph. [0072] and [0073] that disclose the switch fabric as a type of communication messaging bus and disclose multiples of the switch fabric and therefore any one instance of these switch fabrics is also an effective messaging bus and that performs the connections to the components shown in Fig. 1, 2 and their respective components that at least ph. [0090] discloses as the and as at least ph. [0090] establishes these switch fabrics as a type of bus);
wherein the processing device is configured to convert incoming commands received at the network interface into first messages and second messages (see at least ph. [0066] for converting commands, requests or instructions into detailed instructions or appropriate commands for the memory sub-system).
Although Mittal suggests converting commands, it does not specifically teach converting incoming packets into first and second messages, however, Subbiah discloses:
incoming packets processed through an initiator / adaptor (see at least ph. [0033] for packets received from initiator / adapter devices).
It would have been obvious for a person of ordinary skill in the art before the effective filing date to modify the teachings of Mittal, by the teachings of Subbiah in order to implement the sending of data as a single united unit to avoid intermittent deliveries of related data.
Regarding claim 9, Mittal discloses:
a method, comprising:
communicating, via a first interface of an apparatus, storage access messages in a computer network, wherein the apparatus includes a storage system having a local memory and having a storage capacity accessible via a network storage service over the first interface, wherein the first interface is a network interface: ((see at least Fig. 2 and 3 and ph. [0037] – [0073] for the message passing interfaces that allow to connect to storage devices and, in particular see at least that ph. [0052] establishes the storage devices as external to the host devices/systems, where the data orchestrator communicates with the peripheral device(s) over the peripheral interconnect (acts as an interface between host system and Storage Device(s) and Peripheral Devices, providing communication using message passing interface) without assistance from the host system (i.e. it’s not part of the host system and therefore it/they are networked components relative to each other));
communicating via a second interface of an apparatus, with an external processor outside the device (see at least Fig. 2 and 3 and ph. [0037] – [0073], with at least ph. [0052] in particular for the peripheral interconnect that can connected to the data orchestrators (processors) of the storage devices), the device having a random-access memory (see at least ph. [0021] for peripheral interconnect (described as an input/output bus) used as part of the message passing interface used and implemented throughout and particularly referenced in at least ph. [0052]); and a processing device (see at least Fig. 1 and ph. [0026] – [0036] (with particular attention to at least ph. [0027]) for processor(s) used to power the processing of the system), wherein the second interface is adapted to operate on a peripheral bus (see at least ph. [0021] for peripheral interconnect (described as an input/output bus) used as part of the message passing interface used and implemented throughout and particularly referenced in at least ph. [0052]);
providing, by an interconnect of the apparatus and responsive to storage access messages, a plurality of separate connections among the storage system, the random-access memory, the processing device, and the external processor (see at least Fig. 2, 3 and 4 and ph. [0037] – [0073], [0075] and ph. [0090] and in particular ph. [0072] and [0073] that discloses the switch fabric(s) 215 as a type of communication messaging bus that can connect to the storage devices and the host devices/systems and as per at least Fig. 2 and ph. [0026] and [0027] connect these devices/systems with their memories, storage and processors/processing devices and as per at least Fig. 4 and ph. [0075] the features of Fig. 2 and 3 can be implemented in such a combination that a host system – storage device system of Fig. 2 may be implemented in combination with the system of Fig. 3 (“the system of FIG. 4 can be implemented using the computing systems of FIG. 1, 2 *and/or* 3, presented in ph. [0075]), where the inclusion of and/or indicated combinations of the disclosed systems of the other figures as viable embodiments so that the interconnects/fabrics of at least Fig. 3 and its respectively cited paragraphs above will provide the messaging to the disclosed and cited components of the memories, storage devices and processing devices/processors in Fig. 1 2 and their disclosed and cited paragraphs above); and
converting, by the processing device, is configured to incoming commands received at the network interface into first messages and second messages (see at least ph. [0066] for converting commands, requests or instructions into detailed instructions or appropriate commands for the memory sub-system).
Although Mittal suggests converting commands, it does not specifically teach converting incoming packets into first and second messages, however, Subbiah discloses:
incoming packets processed through an initiator / adaptor (see at least ph. [0033] for packets received from initiator / adapter devices).
It would have been obvious for a person of ordinary skill in the art before the effective filing date to modify the teachings of Mittal, by the teachings of Subbiah in order to implement the sending of data as a single united unit to avoid intermittent deliveries of related data.
Regarding claim 15, Mittal discloses:
a non-transitory computer storage medium storing instructions which, when executed in a computing apparatus, cause the computing apparatus to perform a method (see at least Fig. 1, 2, 3 and 5 and their descriptive paragraphs for such a medium with instructions executed on various computing apparatuses, including host devices, to perform the functions and features disclosed throughout the reference), comprising:
communicating, via a first interface of an apparatus, storage access messages in a computer network, wherein the apparatus includes a storage system having a local memory and having a storage capacity accessible via a network storage service over the first interface, wherein the first interface is a network interface: ((see at least Fig. 2 and 3 and ph. [0037] – [0073] for the message passing interfaces that allow to connect to storage devices and see at least that ph. [0052] establishes the storage devices as external to the host devices/systems (the data orchestrator communicates with the peripheral device over the peripheral interconnect without assistance from the host system (i.e. it’s not part of the host system and therefore it/they are networked components relative to each other));
communicating via a second interface of an apparatus, with an external processor outside the device (see at least Fig. 2 and 3 and ph. [0037] – [0073] for the peripheral interconnect that can connected to the data orchestrators (processors) of the storage devices), the device having a random-access memory (see at least Fig. 1 and ph. [0026] – [0036] for the memory sub-system that may be implemented utilizing various types of RAM) and a processing device (see at least Fig. 2 and 3 and ph. [0037] – [0073] for the peripheral interconnect that can connected to the data orchestrators (processors) of the storage devices), wherein the second interface is adapted to operate on a peripheral bus (see at least ph. [0021] for peripheral interconnect (described as an input/output bus) used as part of the message passing interface used and implemented throughout);
providing, by an interconnect of the apparatus and responsive to storage access messages, a plurality of separate connections among the storage system, the random-access memory, the processing device, and the external processor (see at least Fig. 2, 3 and 4 and ph. [0037] – [0073], [0075] and ph. [0090] that discloses the switch fabric as a type of communication messaging bus that can connect to the storage devices and its memory and processing devices and the host devices with their memories, storage and processors/processing devices and whereas per at least Fig. 4 and ph. [0075] the features of Fig. 2 and 3 can be implemented in such a combination that a host system – storage device system of Fig. 2 may be implemented in combination with the system of Fig. 3 (“the system of FIG. 4 can be implemented using the computing systems of FIG. 1, 2 *and/or* 3, where the inclusion of and/or indicates combinations of the disclosed systems of the other figures as viable embodiments), wherein the interconnect includes a bus switch and each of the plurality of connections is a functioning bus connection (see at least Fig. 2, 3 and 4 and ph. [0037] – [0073], [0075] wherein in particular Fig. 3 and ph. [0072] and [0073] that disclose the switch fabric as a type of communication messaging bus and disclose multiples of the switch fabric and therefore any one instance of these switch fabrics is also an effective messaging bus and that performs the connections to the components shown in Fig. 1, 2 and their respective components that at least ph. [0090] discloses as the and as at least ph. [0090] establishes these switch fabrics as a type of bus); and
converting, by the processing device, is configured to incoming commands received at the network interface into first messages and second messages (see at least ph. [0066] for converting commands, requests or instructions into detailed instructions or appropriate commands for the memory sub-system).
Although Mittal suggests converting commands, it does not specifically teach converting incoming packets into first and second messages, however, Subbiah discloses:
incoming packets processed through an initiator / adaptor (see at least ph. [0033] for packets received from initiator / adapter devices).
It would have been obvious for a person of ordinary skill in the art before the effective filing date to modify the teachings of Mittal, by the teachings of Subbiah in order to implement the sending of data as a single united unit to avoid intermittent deliveries of related data.
Claims 1, 9 and 15 are rejected under 35 U.S.C. 103(a) as being on Murali et al (US 2009/0100148 A1) and Govindaraju et al (US 2017/0295503 A1).
Murali discloses An apparatus, comprising:
a first interface configured to communicate storage access messages in a computer network, wherein the first interface is a network interface; [Fig 2., Para 0015, an electronic device which comprises a sender and a receiver being coupled by a network-based interconnect.]
a second interface connectable to an external processor outside of the device, wherein the second interface is adapted to operate on a peripheral bus; [Fig 2., Para 0017, a shared interconnect, e.g. a bus-based interconnect, is provided between the at least one sender and the at least one receiver.]
a random-access memory; a processing device; a storage system having a local memory and having a storage capacity accessible via a network storage service over the first interface; [Fig. 2, Senders S1-S2, Receiver R; scalable network-based interconnect (N) communicates with the entire system; Fig. 6, IP, R1-R2; Para 0045-0046, The scalable network-based interconnects for data transfer are combined with an efficient flow control with a bus-based interconnect.]
and an interconnect configured to provide, responsive to the storage access messages, a plurality of connections among the storage system, the random-access memory, the processing device, and the external processor, [Fig. 2, scalable network-based interconnect (N) communicates with the entire system; Para 0045-0046, The scalable network-based interconnects for data transfer are combined with an efficient flow control with a bus-based interconnect.]
wherein the interconnect includes a bus switch and each of the plurality of connections is a functioning bus connection; [Fig. 2, Fig. 6, Para 0045; The network N comprises a plurality of switches SW. The network interfaces NI may serve as senders and receivers of a data transfer.]
Murali does not specifically teach wherein the processing device is configured to convert incoming packets received at the network interface into first messages and second messages.
Govindaraju teaches wherein the processing device is configured to convert incoming packets received at the network interface into first messages and second messages. [Col.8, Para 0048, When abstraction layer 650 receives messages from LWM2M Protocol layer 640A, abstraction layer 650 serializes the messages and constructs packets for IEEE 802.15.4 MAC layer 415. When abstraction layer 650 receives packets from IEEE 802.15.4 MAC layer 415, abstraction layer 650 de-serializes the packets and constructs messages for LWM2M Protocol layer 640A.]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Murali with the teachings of Govindaraju to include converting packets into messages as packet switching is a fundamental technology in modern networking and the internet that would provide a flexible system that can handle variable bit rate data streams, allowing for dynamic bandwidth allocation techniques.
Allowable Subject Matter
Claims 7, 8, 13, 14, 19 and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Other References Cited Not Relied Upon
Dunning et al. (US 2021/0286740) discloses a shared address/control bus provided in a memory interconnect and routed to each memory chip.
Shah et al. (US 2023/0017643) discloses a cache buffer for persistent memory ports coupled a to switch fabric/bus and are therefore appliance memory.
Kragel et al. (US 2022/0121587) discloses a storage device/storage appliance over a network in communication with a host-computing device over and external bus (with an external hard drive provided as an example).
Response to Arguments
Applicant’s arguments have been fully considered but are moot in light of new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG C DORAIS whose telephone number is (571)270-3371. The examiner can normally be reached M-F 9:00 am - 6:00pm.
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/CRAIG C DORAIS/Primary Examiner, Art Unit 2198
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