Prosecution Insights
Last updated: April 19, 2026
Application No. 18/545,054

DISPLAY DEVICE AND DISPLAY PANEL

Non-Final OA §102§103§112
Filed
Dec 19, 2023
Examiner
CHOI, CALVIN Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
686 granted / 842 resolved
+13.5% vs TC avg
Strong +18% interview lift
Without
With
+17.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
30 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
65.1%
+25.1% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 842 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office Action is in response to the application filed on 19 December 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In regards to claim 10, claim 10 recites in pertinent part “the first metal patterning layer.” There does not appear to be any antecedent basis for this term and it is unclear to which element this term references. For the purposes of examination, the limitation in question will be read as “the non-metal material of each patterning layer overlap…” Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2019/0372057 A1; hereinafter Park). In regards to claim 1, Park teaches a display panel comprising: a substrate (100) [0068] comprising: a display area (figs. 1-2; [0068]) in which one or more images are displayed ([0006], [0044-0045]); an optical area (T/E) configured to allow light to be transmitted through the substrate along a light transmission path [0068]; and a normal area ([0068]: (E); interpreted as non-optical display area) located outside the optical area; a first driving transistor (TFT2) disposed on the substrate [0073]; a planarization layer (109) disposed on the first driving transistor [0113]; a first anode electrode (1200) disposed in the optical area (fig. 1: (1200) is in (T/E)) [0071], located on the planarization layer (fig. 3: (1200) is on (109)), and electrically connected to the first driving transistor through a contact hole (CT2) [0082] of the planarization layer (fig. 3); a bank (150) [0070] located on the first anode electrode (fig. 3) and including a light emitting opening (fig. 3: e.g. opening in the T/E region) which exposes a portion of the first anode electrode; a first emission layer (fig. 3: e.g. OLED2) disposed in the optical area and contacting a surface of the portion of the first anode electrode exposed through the light emitting opening (fig. 3; [0072]); a cathode electrode (140) [0076] commonly disposed in the optical area and the normal area (figs. 1-3: (140) is in (E) and (T/E)), located on the first emission layer and including a plurality of cathode holes in the optical area (e.g. implied (OLED2)); and a plurality of patterning layers respectively disposed in the plurality of cathode holes, and each patterning layer including a non-metal material (fig. 3: e.g. (130') is organic) [0077]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claim 1 above, in view of Park et al. (US 2022/0013598 A1; hereinafter Park’598). In regards to claim 2, Park teaches the limitations discussed above in addressing claim 1. Park appears to be silent as to, but does not preclude, the limitations wherein the bank comprises a plurality of bank transmission openings located in the light transmission path in the optical area, wherein each one of the plurality of cathode holes corresponds to a respective one of the plurality of bank transmission openings; and wherein all or a portion of each of the plurality of cathode holes overlaps with all or a portion of the respective bank transmission opening. Park’598 teaches, e.g. in fig. 40, the limitations wherein the bank (BNK) [0299] comprises a plurality of bank transmission openings (H1) [0304] located in the light transmission path (arrow depicting LIGHT) [0299] in the optical area (TA) [0302], wherein each one of the plurality of cathode holes (e.g. (RC1)) corresponds to a respective one of the plurality of bank transmission openings (fig. 40: (RC1) corresponds to (H1)) [0304]; and wherein all or a portion of each of the plurality of cathode holes overlaps with all or a portion of the respective bank transmission opening (fig. 40: elements (RC1) align with (H1)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 3, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 2. Park’598 further teaches, e.g. in fig. 40, the limitations wherein the cathode electrode (CAT) [0300] is disposed to extend along at least one side surface of the bank (fig. 40: (CAT) extends along at least one upper side surface of (BNK)) to an inside portion of at least one of the plurality of bank transmission openings ((CAT) extends to an edge of the inside portion of one of (H1)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 4, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 2. Park’598 further teaches, e.g. in fig. 40, the limitations wherein the cathode electrode (CAT) [0300] is disposed to extend along at least one side surface of the bank (fig. 40: (CAT) extends along at least one upper side surface of (BNK)) to a boundary of at least one of the plurality of bank transmission openings ((CAT) extends to an edge of the inside portion of one of (H1)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 5, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 2. Park further teaches, e.g. in figs. 1-3, the limitations wherein at least one of the plurality of patterning layers (130') [0077] is disposed to overlap with the bank (150) [0070] or to extend from at least one of the plurality of bank transmission openings along at least one side surface of the bank to an upper portion of the bank. In regards to claim 6, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 2. Park further teaches, e.g. in figs. 1-3, the limitations wherein one patterning layer (130/130') [0077] among the plurality of patterning layers overlap with two bank transmission openings among the plurality of bank transmission openings, and the two bank transmission openings are separated by a portion of the bank (e.g. (130/130') overlaps with the openings for (OLED1/OLED2) respectively). In regards to claim 7, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 6. Park further teaches, e.g. in figs. 1-3, the limitations wherein the one patterning layer (130/130') [0077] comprises: a first portion (a portion of (130/130') over a portion (109)) located over the planarization layer (109) [0113]; an intermediate portion (portion of (130/130') over (150)) located over the portion of the bank (150) [0070] separating two bank transmission openings (fig. 3: (OLED1/OLED2)); and a second portion (another portion of (130/130') over another portion of (109)) located over the planarization layer (109) (e.g. fig. 3), wherein the intermediate portion is located between the first portion and the second portion, and the intermediate portion is disposed further from the substrate than the first portion and the second portion (fig. 3: in the central portion of the device e.g. over TFT2). In regards to claim 8, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 2. Park further teaches, e.g. in figs. 1-3, the limitations wherein each of the plurality of patterning layers (130/130') overlap with one bank transmission opening (e.g. openings over (OLED1/OLED2)) among the plurality of bank transmission openings. In regards to claim 9, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 2. Park’598 further teaches, e.g. in fig. 40, the limitations wherein the planarization layer (PLN1) [0295] comprises a plurality of planarization layer transmission openings (e.g. upward detents into which (BNK) extends in the optical area (TA)), and wherein the plurality of planarization layer transmission openings are located in the light transmission path (fig. 40: arrow depicting LIGHT) [0299], and correspond to the plurality of bank transmission openings (H1) [0304]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 10, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 9. Park’598 further teaches, e.g. in fig. 40, the limitations wherein a first bank transmission opening (e.g. one instance of (H1)) [0304] among the plurality of bank transmission openings, a first planarization layer transmission opening (e.g. one instance of the areas of upward detents into (PLN1) into which (BNK) extends) among the plurality of planarization layer transmission openings, and a first patterning layer (e.g. (CPL)) among the plurality of patterning layers ((CPL/EL); (EL) is also used in shaping a pattern) are disposed to correspond to each other (e.g. all the layers are in (TA)), and wherein the first metal patterning layer overlap with at least one side surface of the planarization layer adjacent to the first planarization layer transmission opening (e.g. (CPL) covers a side surface of (PCL) in (H1)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 11, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 9. Park’598 further teaches, e.g. in fig. 40, the limitations wherein a first bank transmission opening (e.g. one instance of (H1)) [0304] among the plurality of bank transmission openings, a first planarization layer transmission opening (e.g. one instance of the areas of upward detents into (PLN1)) among the plurality of planarization layer transmission openings, and a first patterning layer (e.g. (CPL)) among the plurality of patterning layers ((CPL/EL); (EL) is also used in shaping a pattern) are disposed to correspond to each other, and wherein at least one side surface of the bank (side surface of (BNK)) overlap with at least one side surface of the planarization layer (side surface of (PLN1) adjacent to the first planarization layer transmission opening (fig. 40: the side surface of (BNK) overlaps the side surface of (PLN1) in a plan view in an instance of the areas of upward detents into (PLN1)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 12, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 9. Park’598 further teaches, e.g. in fig. 40, the limitations wherein a first bank transmission opening (e.g. one instance of (H1)) [0304] among the plurality of bank transmission openings, a first planarization layer transmission opening (e.g. one instance of the areas of upward detents into (PLN1)) among the plurality of planarization layer transmission openings, and a first patterning layer (e.g. (CPL)) among the plurality of patterning layers ((CPL/EL); (EL) is also used in shaping a pattern) are disposed to correspond to each other, and wherein the first patterning layer overlap with at least one side surface of the bank adjacent to the first bank transmission opening (fig. 40: (CPL) overlaps a side surface of (BNK) in (H1)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 13, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 9. Park’598 further teaches, e.g. in fig. 40, the limitations wherein a first bank transmission opening (e.g. one instance of (H1)) [0304] among the plurality of bank transmission openings, a first planarization layer transmission opening (e.g. one instance of the areas of upward detents into (PLN1)) among the plurality of planarization layer transmission openings, and a first patterning layer (e.g. (CPL)) among the plurality of patterning layers ((CPL/EL); (EL) is also used in shaping a pattern) are disposed to correspond to each other, and wherein at least one edge of the first patterning layer is located between at least one edge of the first bank transmission opening and at least one edge of the first planarization layer transmission opening (e.g. an edge of (CPL) is between an edge of (BNK) and an edge of (PLN1) in (H1) in the vertical direction). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 14, Park teaches the limitations discussed above in addressing claim 1. Park appears to be silent as to, but does not preclude, the limitations wherein the plurality of patterning layers comprises an organic material as a non-metal material, and each of the plurality of patterning layers is in contact with an adjacent portion of the cathode electrode. Park’598 teaches, e.g. in fig. 40, the limitations wherein the plurality of patterning layers ((CPL/EL); (EL) is also used in shaping a pattern) comprises an organic material as a non-metal material ([0299]: (EL) comprises an organic compound), and each of the plurality of patterning layers (CPL/EL) is in contact with an adjacent portion of the cathode electrode (CAT) (fig. 40: (CPL) and (EL) both contact (CAT)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 15, Park teaches the limitations discussed above in addressing claim 1. Park appears to be silent as to, but does not preclude, the limitations wherein the optical area comprises a plurality of transmission areas and a low-transmittable area different from the plurality of transmission areas, wherein the first anode electrode is disposed in the low-transmittable area, and wherein the low-transmittable area is an area not allowing light to be transmitted or an area allowing light to be transmitted at a lower transmittance than the plurality of transmission areas. Park’598 teaches, e.g. in fig. 40, the limitations wherein the optical area (TA) comprises a plurality of transmission areas (shown by (18d)) and a low-transmittable area (18B) different from the plurality of transmission areas [0303], wherein the first anode electrode (AND) is disposed in the low-transmittable area (fig. 40: (AND) is primarily disposed within a plan view footprint of (18b)), and wherein the low-transmittable area is an area not allowing light to be transmitted or an area allowing light to be transmitted at a lower transmittance than the plurality of transmission areas [0303]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 16, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 15. Park’598 further teaches, e.g. in fig. 40, the limitations wherein the optical area further comprises: an optical bezel area surrounding the optical area (fig. 1: e.g. (CA) area around (41/42)), a first light emitting element (fig. 40: implicit from the upward arrow depicting light emission) configured with the first anode electrode (AND), the first emission layer (EL), and the cathode electrode (CAT) (fig. 40), and wherein the first driving transistor (TFT) is configured to drive the first light emitting element, and the first driving transistor is disposed in the optical bezel area being an area outside of the optical area without being disposed in the low-transmittable area of the optical area (fig. 40: (TFT) is in the plan view footprint of (18b/CA)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 17, the combination of Park and Park’598 teaches the limitations discussed above in addressing claim 15. Park’598 further teaches, e.g. in fig. 40, the limitations further comprising a first light emitting element (fig. 40: implicit from the upward arrow depicting light emission) configured with the first anode electrode (AND), the first emission layer (EL), and the cathode electrode (CAT) (fig. 40), and wherein the first driving transistor (TFT) is configured to drive the first light emitting element, and the first driving transistor is disposed in the low-transmittable area of the optical area (fig. 40: (TFT) is in the plan view footprint of (18b)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 18, Park teaches the limitations discussed above in addressing claim 1. Park appears to be silent as to, but does not preclude, the limitations wherein the plurality of patterning layers have substantially a same thickness as the thickness of the cathode electrode. Park’598 teaches, e.g. in fig. 40, the limitations wherein the plurality of patterning layers have substantially a same thickness as the thickness of the cathode electrode (fig. 40: (CPL) is depicted as having a substantially thickness as (CAT)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). In regards to claim 19, Park teaches the limitations discussed above in addressing claim 1. Park appears to be silent as to, but does not preclude, the limitations wherein a side surface of the plurality of patterning layers and a side surface of the cathode electrode are disposed in contact with or adjacent to each other. Park’598 teaches, e.g. in fig. 40, the limitations wherein a side surface of the plurality of patterning layers (e.g. side surface of (CPL/EL)) and a side surface of the cathode electrode (e.g. side surface of (CAT)) are disposed in contact with or adjacent to each other (fig. 40: e.g. a side surface of (CPL) directly contacts a side surface of (CAT) in (H1)). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park’598. In regards to claim 20, Park teaches, e.g. in figs. 1-3, a display device comprising: a substrate (100) [0068] including a display area (figs. 1-2; [0068]) displaying one or more images ([0006], [0044-0045]), an optical area (T/E) allowing light to be transmitted [0068] and a normal area ([0068]: (E); interpreted as non-optical display area) located outside the optical area; a first driving transistor (TFT2) on the substrate [0073]; a planarization layer (109) disposed on the first driving transistor [0113]; a first anode electrode (1200) disposed in the optical area (fig. 1: (1200) is in (T/E)) [0071], located on the planarization layer (fig. 3: (1200) is on (109)), and electrically connected to the first driving transistor through a contact hole (CT2) [0082] of the planarization layer (fig. 3); a bank (150) [0070] located on the first anode electrode (fig. 3), and comprising a light emitting opening (fig. 3: e.g. opening in the T/E region) for exposing a portion of the first anode electrode; a first emission layer (fig. 3: e.g. OLED2) disposed in the optical area and contacting a surface of the portion of the first anode electrode exposed through the light emitting opening (fig. 3; [0072]); and a cathode electrode (140) [0076] commonly disposed in the optical area and the normal area (figs. 1-3: (140) is in (E) and (T/E)), located on the first emission layer and including a plurality of cathode holes in the optical area (e.g. implied (OLED2)). Park appears to be silent as to, but does not preclude, the limitations wherein at least one of the bank and the planarization layer comprises at least one transmission opening in a light transmission path in the optical area. Park’598 teaches, e.g. in fig. 40, the limitations wherein at least one of the bank (BNK) [0299] and the planarization layer comprises at least one transmission opening (e.g. upward detents into which (BNK) extends in the optical area (TA)) in a light transmission path (arrow depicting LIGHT) [0299] in the optical area (TA) [0302]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Park with the aforementioned limitations taught by Park’598 to allow for an under-display camera (Park [0006]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CALVIN CHOI Patent Examiner Art Unit 2812 /CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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Prosecution Timeline

Dec 19, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102, §103, §112 (current)

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2y 4m
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