Prosecution Insights
Last updated: April 19, 2026
Application No. 18/545,152

ELECTRICAL RECEPTACLE WITH GROUND FAULT CIRCUIT INTERRUPTER AND POWER CONVERSION DEVICE FOR LOW-VOLTAGE INTERFACE

Non-Final OA §102§103
Filed
Dec 19, 2023
Examiner
SREEVATSA, SREEYA
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hubbell Incorporated
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
88%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
219 granted / 255 resolved
+17.9% vs TC avg
Minimal +2% lift
Without
With
+2.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
294
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
47.6%
+7.6% vs TC avg
§102
35.3%
-4.7% vs TC avg
§112
14.5%
-25.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 255 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending in this application. Information Disclosure Statement The information disclosure statement (IDS) were submitted on 03/18/2024 and 04/19/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claims 10, 15 and 17 are objected to because of the following informalities: Claim 10 lines 2-3, “the pass-through openings” should be -- the plurality of pass-through openings--. Claim 15 line 1, “the pin ports” should be -- the plurality of pin ports--. Claim 17 line 4, “GFCI” should be –ground fault circuit interrupter (GFCI)--. Appropriate correction is required. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-6, 8-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Roberts (US 20210135452 A1). Regarding claim 1, Roberts teaches an electrical outlet (i.e. protective device 10, figs.1-9) comprising: a housing (i.e. front cover 12, back-body 14, separator 16, figs.1-9) having a faceplate (i.e. front cover 12, figs.1-9) with a first opening (e.g. opening of outlet receptacles 12-1, 12-2, figs.1-9) in communication with a high-voltage interface ([0042], accept the hot, neutral and ground blades of a corded plug) and a second opening (e.g. opening of USB ports 12-3, 12-4, figs.1-9) in communication with a low-voltage interface ([0042], accept a USB plug); a power supply circuit board (i.e. USB printed circuit board 302, figs.2-9) having a power conversion circuit positioned in the housing ([0046], USB power supply circuit 1100 described briefly below in connection with FIG. 11, is formed on USB PCB 302); a protection circuit board (i.e. electromechanical PCB 201, figs.2-9) having a circuit interrupting device positioned in the housing ([0045], Ground fault interrupt circuit 1000 is formed on electromechanical PCB 201, upon which trip mechanism 203 is also mounted); a low-voltage circuit board (i.e. USB receptacle PCB 303, figs.2-9) including the low-voltage interface ([0043], upon which are mounted a type-A USB receptacle 303-1, and a type B USB receptacle 303-2); and a compliant pin (i.e. leads 204-1, 204-2, figs.2-9) electrically connecting the power conversion circuit and the low-voltage interface ([0051], can be permitted to extend through the electromechanical PCB 201 to USB PCB 302), wherein the protection circuit board is positioned between the power supply circuit board and the low-voltage circuit board (e.g. 201 is between 302 and 303, fig.2). Regarding claim 2, Roberts teaches the electrical outlet of claim 1, wherein the low-voltage interface is a universal serial bus interface ([0043], upon which are mounted a type-A USB receptacle 303-1, and a type B USB receptacle 303-2). Regarding claim 3, Roberts teaches the electrical outlet of claim 1, wherein the compliant pin extends through the protection circuit board ([0051], can be permitted to extend through the electromechanical PCB 201 to USB PCB 302). Regarding claim 4, Roberts teaches the electrical outlet of claim 1, wherein the compliant pin mechanically and electrically connects the low-voltage circuit board and the power supply circuit board ([0051], spanning the distance D between the electromechanical PCB 201 and USB PCB 302, and allowing it to make electrical contact with both ground fault interrupt circuit 1000 and USB power supply circuit 1100). Regarding claim 5, Roberts teaches the electrical outlet of claim 1, wherein the protection circuit board includes a first pin port (e.g. one of holes 301-4, 301-5, figs.3-4) and a second pin port (e.g. one of holes 301-4, 301-5, figs.3-4), and wherein the compliant pin extends between from the power supply circuit board and engages the first pin port ([0051], can further act to guide leads 204-1, 204-2 to USB PCB 302, and to permit leads 204-1, 204-2 to pass through spacer 301 to USB PCB 302) and a second compliant pin extends from the low-voltage circuit board and engages the second pin port ([0051], spanning the distance D between the electromechanical PCB 201 and USB PCB 302, and allowing it to make electrical contact with both ground fault interrupt circuit 1000 and USB power supply circuit 1100). Regarding claim 6, Roberts teaches the electrical outlet of claim 5, wherein the first pin port is aligned with the second pin port (e.g. lead 204-1 is aligned above and below PCB 201, fig.3). Regarding claim 8, Roberts teaches the electrical outlet of claim 1, wherein the circuit interrupting device is a ground fault circuit interrupter ([0040], the ground fault interruption circuit). Regarding claim 9, it is rejected for the same reasons as stated above for claim 1. Regarding claim 10, it is rejected for the same reasons as stated above for claim 5. Regarding claim 11, Roberts substantially teaches the claim limitations as stated above for claim 8. Roberts further teaches wherein the plurality of compliant pins are electrically isolated from the ground fault circuit interrupter ([0040], these features can be implemented independent of one another) (e.g. 204-1 and 204-2 are isolated from 203, fig.3). Regarding claim 12, it is rejected for the same reasons as stated above for claim 5. Regarding claim 13, it is rejected for the same reasons as stated above for claim 4. Regarding claim 14, it is rejected for the same reasons as stated above for claim 5. Regarding claim 15, it is rejected for the same reasons as stated above for claim 6. Regarding claim 17, the method is rejected for the same reasons as stated above for claim 1. Regarding claim 18, the method is rejected for the same reasons as stated above for claim 2. Regarding claim 19, the method is rejected for the same reasons as stated above for claim 4. Regarding claim 20, the method is rejected for the same reasons as stated above for claim 5. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts (US 20210135452 A1). Regarding claim 7, Roberts teaches the electrical outlet of claim 5. Roberts does not teach, wherein the first pin port is offset from the second pin port. It would have been an obvious matter of design choice to have the first pin port is offset from the second pin port, since the applicant has not disclosed that the first pin port offset from the second pin port solves any problem or is for a particular reason. It appears that the claimed invention would perform equally well with the first pin port offset from the second pin port, as it provides the advantage of versatile design. Regarding claim 16, it is rejected for the same reasons as stated above for claim 7. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SREEYA SREEVATSA whose telephone number is (571)272-8304. The examiner can normally be reached M-F 8am-5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SREEYA SREEVATSA/Primary Examiner, Art Unit 2838 02/18/2026
Read full office action

Prosecution Timeline

Dec 19, 2023
Application Filed
Feb 18, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
88%
With Interview (+2.5%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 255 resolved cases by this examiner. Grant probability derived from career allow rate.

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