DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 1 is objected to because of the following informalities: the claim recites “a plurality of N light-emitting sources” in line 3 and “N transistors” in line 4; however, the claim does not explicitly define N and N must be an integer greater than or equal to two due to the preamble requiring an addressable laser array. Therefore, it’s unclear if N excludes zero or one. The Examiner suggests amending the claim with N being an integer greater than or equal to two in order to avoid a potential 112-indeifnteness rejection. Appropriate correction is required. For purposes of examination, claim 1 is examined according to the Examiner’s suggestion.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7 and 14 are rejected under 35 U.S.C. 102a2 as being anticipated by Joshi et al. (US PG Pub 2024/0088623 A1).
Regarding claim 1, Joshi discloses a monolithic integrated circuit device (FIG. 1) comprising an addressable laser array (an integrated emitter array device 20, FIG. 1, [0025]), said addressable laser array comprising:
a plurality of N light-emitting sources (VCSELs 24, FIG. 1, [0026]);
a multiplexer (timing control logic 32/control circuit 30/transistors 26, FIG. 1, [0025]-[0026]) comprising N transistors (the transistors 26, FIG. 1, [0026]), each of said N transistors associated with a different one of said plurality of N light-emitting sources (a one-to-one correspondence between the VCSELs 24 and the transistors 26, FIG. 1); and
wherein each of said N transistors is operable to address said associated one light-emitting source (“control circuit 30 applies a control signal to the terminal of transistor 26, which causes the corresponding VCSEL 24 to output a light pulse,” [0027]).
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Regarding claim 2, Joshi discloses each of said plurality of N light-emitting sources is an LED, an EEL, a VCSEL, or a PCSEL (24 is a VCSEL, [0026]).
Regarding claim 3, Joshi discloses said monolithic integrated circuit comprises a substrate/wafer made of GaN, GaAs, InP, SiC, or GaSb (48 is a GaAs substrate, FIG. 3A, [0032]).
Regarding claim 4, Joshi discloses each of said plurality of N transistors is a MESFET, pHEMT, HFET, or HBT that is operable for 3-terminal analog functionality (26 is an HBT, [0026]).
Regarding claim 5, Joshi discloses said monolithic integrated circuit comprises a plurality of epitaxial layers (50/56/52/54/58/62/60/64, FIG. 3A, [0032]-[0033]) operable to form said light-emitting sources and said transistors.
Regarding claim 7, Joshi discloses said epitaxial layers used to form said light-emitting sources are different from said epitaxial layers used to form said transistors ([0032]-[0033]).
Regarding claim 14, Joshi discloses said epitaxial layers associated with said transistors overlay said epitaxial layers associated with said light-emitting sources (the layers 58/62/60 of the transistor 26 overlay the layers 50/56/52/54 of the VCSEL 24, FIG. 3A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. in view of Olbright et al. (US Patent 5,283,447).
Regarding claim 6, Joshi has disclosed the monolithic integrated circuit device outlined in the rejection to claim 5 above except said epitaxial layers used to form said light-emitting sources are isolated form said epitaxial layers used to form said transistors by one or more epitaxial layers of highly resistive GaAs and/or InGaP. Olbright discloses said epitaxial layers used to form said light-emitting sources are isolated form said epitaxial layers used to form said transistors by one or more highly resistive epitaxial layers (“HBT 136 is electrically isolated from the region of the VCSEL over which it is formed by an insulating layer 196 and an ion-implanted guard ring 197 and is electrically connected by contact 193 to the region of the VCSEL in which lasing takes place,” FIG. 8, col. 6 lines 49-54). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the monolithic integrated circuit device of Joshi with the one or more highly resistive epitaxial layers isolating the transistor from the VCSEL as taught by Olbright in order to obtain a lateral current confinement between the transistor and the VCSEL. It also would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the one or more highly resistive epitaxial layers of the combination with a material of GaAs or InGaP in order to obtain desired current confinement effect, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 13, Joshi has disclosed the monolithic integrated circuit device outlined in the rejection to claim 6 above except said InGaP layer is operable to stop etching between one or more epitaxial layers associated with said plurality of light-emitting sources and one or more epitaxial layers associated with said plurality of transistors. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the InGaP layer of the combination with operable to stop etching between one or more epitaxial layers associated with said plurality of light-emitting sources and one or more epitaxial layers associated with said plurality of transistors in order to form corresponding mesa structures.
Regarding claim 15, Joshi has disclosed the monolithic integrated circuit device outlined in the rejection to claim 1 above except said transistors are isolated from said light-emitting sources by ion implementation and/or mesa etching. Olbright discloses said transistors are isolated from said light-emitting sources by ion implementation and/or mesa etching (“HBT 136 is electrically isolated from the region of the VCSEL over which it is formed by an insulating layer 196 and an ion-implanted guard ring 197 and is electrically connected by contact 193 to the region of the VCSEL in which lasing takes place,” FIG. 8, col. 6 lines 49-54). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the monolithic integrated circuit device of Joshi with the ion implementation isolating the transistor from the VCSEL as taught by Olbright in order to obtain a lateral current confinement between the transistor and the VCSEL.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. in view of Deppe (US PG Pub 2005/0063440 A1).
Regarding claim 8, Joshi has disclosed the monolithic integrated circuit device outlined in the rejection to claim 1 above and further discloses an epitaxial structure of said plurality of N light-emitting sources comprises an N-type DBR layer (54, FIG. 3A, [0032]), one or more active layers (52, FIG. 3A, [0032]), and a P-type DBR layer (50, FIG. 3A, [0032]) except a smoothing buffer layer. Deppe discloses a VCSEL further comprising a smoothing buffer layer (“In FIG. 7 the mesa forming layer 520 is epitaxially grown on the lower DBR layers 510, which is also grown on substrate 500 that may contain addition buffer and crystal smoothing layers,” [0065]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the VCSEL of Joshi with a smoothing buffer layer as taught by Deppe in order to minimize crystal defect between layers of the VCSEL.
Regarding claim 9, Joshi, as modified, discloses said smoothing buffer layer, said N-type DBR layer, said one or more active layers, and said P-type DBR layer each comprise a plurality of epitaxial layers (FIG. 3A of Joshi and [0065] of Deppe).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. in view of CHINI et al. (US PG Pub 2013/0062667 A1, 08/27/25 IDS).
Regarding claims 10, Joshi has disclosed the monolithic integrated circuit device outlined in the rejection to claim 1 above except an epitaxial structure of said plurality of N transistors comprises one or more single recess pHEMTs that comprise a lower barrier layer, a lower delta doped layer, a lower spacer layer, a channel layer, an upper spacer layer, an upper delta doped layer, an upper barrier layer, a Schottky layer, an etch stop layer and a cap layer. CHINI discloses an epitaxial structure of said plurality of N transistors comprises one or more double recess pHEMTs (1, FIG. 6, [0114]) that comprise a lower barrier layer (12, FIG. 6), a lower delta doped layer (13, FIG. 6), a lower spacer layer (14, FIG. 6), a channel layer (15, FIG. 6), an upper spacer layer (16, FIG. 6), an upper delta doped layer (17, FIG. 6), an upper barrier layer (18, FIG. 6), a Schottky layer (41 or 42, FIG. 6), an etch stop layer (19, FIG. 6) and a cap layer (23, FIG. 6). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the transistors of Joshi with the pHEMTs as taught by CHINI in order to obtain superior high-frequency and low noise operation. It also would have been an obvious matter of design choice before the effective filing date of the claimed invention to modify the pHEMTs of the combination with one or more single recess pHEMTs in order to obtain low-voltage linearity and lower access resistance.
Regarding claims 11, Joshi has disclosed the monolithic integrated circuit device outlined in the rejection to claim 1 above except an epitaxial structure of said plurality of N transistors comprises one or more double recess pHEMTs that comprise a lower barrier layer, a lower delta doped layer, a lower spacer layer, a channel layer, an upper spacer layer, an upper delta doped layer, an upper barrier layer, a Schottky layer, an etch stop layer and a cap layer. CHINI discloses an epitaxial structure of said plurality of N transistors comprises one or more double recess pHEMTs (1, FIG. 6, [0114]) that comprise a lower barrier layer (12, FIG. 6), a lower delta doped layer (13, FIG. 6), a lower spacer layer (14, FIG. 6), a channel layer (15, FIG. 6), an upper spacer layer (16, FIG. 6), an upper delta doped layer (17, FIG. 6), an upper barrier layer (18, FIG. 6), a Schottky layer (41 or 42, FIG. 6), an etch stop layer (19, FIG. 6) and a cap layer (23, FIG. 6). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the transistors of Joshi with the double recess pHEMTs as taught by CHINI in order to obtain superior high-frequency and low noise operation.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Joshi et al. in view of McHugo et al. (US PG Pub 2004/0224463 A1).
Regarding claim 12, Joshi has disclosed the monolithic integrated circuit device outlined in the rejection to claim 1 above and further discloses an epitaxial structure of said plurality of N transistors comprise HBTs that comprise a collector layer (60, FIG. 3A, [0033]), a base layer (62, FIG. 3A, [0033]), and an emitter layer (58, FIG. 3A, [0033]) except the HBT further comprises a sub collector layer and emitter cap layers. McHugo discloses an epitaxial structure of a HBT (FIG. 6A, [0019]-[0020]) that comprise a sub collector layer (94A, FIG. 6A), a collector layer (112A, FIG. 6A), a base layer (114A, FIG. 6A), an emitter layer (116A, FIG. 6A), and emitter cap layers (118A, FIG. 6A). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the HBTs of Joshi with the HBT having a sub-collector layer and emitter cap layers as taught by McHugo in order to reduce parasitic base-collector capacitance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP2019067831A (hereafter JP’831, 08/25/25 IDS) and Herschbach et al. (US PG Pub 2015/0092258 A1, 08/25/25 IDS) both disclose a monolithic integrated circuit device comprising an addressable laser array similar to the claimed invention (see FIGS. 1 of JP’831 and Herschbach).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUANDA ZHANG whose telephone number is (571)270-1439. The examiner can normally be reached M-F 10:30 AM - 6:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MINSUN HARVEY can be reached at (571)272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUANDA ZHANG/Primary Examiner, Art Unit 2828
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