DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 05/27/2026, for application number 18/545,375 has been received and entered into record. Claims 1, 7, 14, 15 and 20 are amended. Claims 10-13 have been cancelled. Thus, claims 1, 3-9, 14-15 and 17-20 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2016/0133304 A1) in view of Kuo et al. (US 2020/0110662 A1) and in further view of Lu et al. (US 2001/0049764 A1).
Regarding claim 1, Park teaches a microcontroller that performs a control function (ECU 470, Figure 4 and Figure 6), the microcontroller comprising:
a memory management unit (MMU) (calibration memory management module 312, Figure 3) configured to perform a soft reset process, in response to detection of a soft reset event occurring in the microcontroller (“When the ECU is initialized, a reference page may be divided into M sub reference pages each configured to have 1:1 correspondence to a virtual sub working page.” Par 0042 and “a calibration memory management module dynamically allocating memory to be used for calibration in response to the received CCP message.” Par 0052) [the CMMM executes its memory organization logic when the ECU is initialized/ in response to external messages (triggering event)], by initializing, based on a soft reset event occurring in the microcontroller, remaining areas of a memory managed by the memory management unit other than a working page area based on a random access memory (RAM) memory for performing a calibration function (“when the ECU 650 is initialized, a sub working page corresponding to each sub reference page is set as the sub reference page itself.” Par 0136 and “the calibration memory management module 400 configures the total working page 420 in such a manner that sub working pages not allocated to the RAM region 430 among the sub working pages included in the working page 420 refer to corresponding sub reference pages.” Par 0079 and “The calibration memory management module divides a reference page and a working page into M sub reference pages and M sub working pages, respectively, and divides a RAM region for calibration data into N subpages, in which N is less than M.” par 0052 and Figures 3-4) [upon initialization, the MMU sets remaining areas (unallocated sub working pages) to refer back to reference pages while reserving a specific RAM region for the calibration function];
wherein, when the consistency of the memory stored in the working page area is normal and the currently set page information is a reference page, the memory management unit is configured to perform the re-establishment of the memory based on a calibration variable value of a flash area (“When the ECU is initialized, a reference page may be divided into M sub reference pages each configured to have 1:1 correspondence to a virtual sub working page.” Par 0028 and “when the ECU 650 is initialized, a sub working page corresponding to each sub reference page is set as the sub reference page itself.” Par 0136 and “control program data of a vehicle should be retained even when power is not supplied to the ECU and thus is stored in non-volatile memory, e.g., flash memory.” Par 0012) [during reestablishment, the working page is referred to calibration variables stored in flash based reference],
wherein, when the consistency of the memory stored in the working page area is normal and the currently set page information is a working page, the memory management unit is configured to perform the re-establishment of the memory based on a variable value of a RAM area changed with calibration (“Upon determining that a sub working page corresponding to the checked sub reference page is already allocated in S909, the ECU 650 may execute the DNLOAD command in S919 by reading the buffered data block.” Par 0135 and “calibration memory management module 400 may translate a corresponding logical address into a physical address of a RAM region to change the value of calibration data corresponding to the logical address such that the changed value is reflected in the vehicle control program.” Par 0096) [when the working page is already allocated (normal consistency), the MMU uses RAM region to execute changed calibration values].
However, Park does not explicitly teach a communication module including a non-volatile memory, the communication module configured to: store, in the non-volatile memory, communication setting information that has existed prior to occurrence of the soft reset event, and after completion of the soft reset process, actively perform a recovery procedure to re-establish a logical communication connection using the stored communication setting information so that system-level communication continuity is maintained across the soft reset event, and a microprocessor initialized according to the soft reset process, wherein the memory management unit is further configured to generate, before a soft reset occurs, a control signal related to the storage of memory setting information in order to maintain calibration when the soft reset occurs, determine consistency of the memory stored in the working page area before reset, and perform re-establishment of the memory after reset based on currently set page information, wherein, when the consistency of the memory stored in the working page area is normal, the memory management unit is configured to load memory information of the working page area stored before soft reset and then reallocate a memory unit block of the working page area after the soft reset based on the memory information of the working page area.
In the analogous art, Kuo teaches a communication module including a non-volatile memory (“The memory controller 110 may comprise…a storage device such as a read only memory (ROM) 112M, … and a transmission interface circuit 118,” par 0019 and Figure 1) [controller 110 with transmission interface may correspond to a communication module], the communication module configured to:
store, in the non-volatile memory, communication setting information that has existed prior to occurrence of the soft reset event (“The ROM 112M of this embodiment is arranged to store a program code 112C … The transmission interface circuit 118 may conform to a specific communications specification … and may perform communications according to the specific communications specification,” par 0020 and “the soft reset may comprise … re-executing the system execution file (or in-system programming file), … in order to achieve the purpose of system reset,” par 0050) [the communication module stores program code and communication specifications (setting information) which are preserved and re-executed during soft reset], and
after completion of the soft reset process, actively perform a recovery procedure to re-establish a logical communication connection using the stored communication setting information so that system-level communication continuity is maintained across the soft reset event (“activating the transmission interface circuit and relinking with the host device, the controller completes soft reset to make the data storage device operate normally again.” Par 0009 and “Since the transmission interface circuit 118 has been re-activated, the micro-processor 112 may relink and interact with the host device 50 through the transmission interface circuit 118.” Par 0051 and “the soft reset may comprise … re-executing the system execution file (or in-system programming file), … execute soft reset to instantly restore the data storage device 100 back to the normal mode to make it continue working.” Par 0030), and
a microprocessor initialized according to the soft reset process (“the microprocessor 112 may activate the watchdog timer to perform soft reset; wherein the soft reset may comprise performing system reset in a software manner, for example, re-executing the system execution file” par 0050 and “the memory controller 110 (e.g. the microprocessor 112) may complete the soft reset to make the data storage device 100 operate normally again.” Par 0051) [the microprocessor undergoes system reset via soft reset process (re-execution of system files)],
wherein the memory management unit is further configured to generate, before a soft reset occurs, a control signal related to the storage of memory setting information in order to maintain calibration when the soft reset occurs (“interrupting execution of a current procedure and activating an interruption service; … performing cache rearrangement … and programming rearranged cache data into the at least one NV memory element, to perform data recovery; and through activating a watchdog module … completing soft reset” par 0007 and “storing the cache data into the NV memory 120 to prevent any loss of cache data… make the data storage device 100 operate normally again, for example, by way of soft reset,” Par 0052) [the controller generates an interruption service (control signal) to store cache data into NVM before activating watchdog timer, thereby maintaining data across the reset], determine consistency of the memory stored in the working page area before reset (“In Step S26, the memory controller 110 determines whether the data has been sent/buffered into the volatile memory element 130… the cache head H needs to be properly corrected, to make the cache head H point towards valid cache data.” par 0046 and “In Step S28, the memory controller 110 resynchronizes the cache space of the volatile memory element 130, for example, by pulling the cache head H back to point towards the aforementioned valid cache data,” par 0047) [this checks validity of data within volatile memory (working page) and resynchronizes memory before reset is finalized], and perform re-establishment of the memory after reset based on currently set page information (“The memory controller 110 records mapping relationships between logical addresses and physical addresses of data in a logical-to-physical address mapping table” par 0021 and “ the memory controller 110 may update the group mapping tables according to a latest mapping relationship of the user data. A size of any group mapping table within the group mapping tables is preferably equal to a size of one page” par 0022 and paragraph 50) [to reestablish normal operations, the method loads latest mapping relationships stored in page-sized mapping tables].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Park and Kuo before him before the effective filing date of the claimed invention, to have modified Park to incorporate the teachings of Kuo to include a communication module to reestablish a logical communication connection and initialize a microprocessor according to a soft reset process to ensure system-level continuity with calibration device across reset events, preventing system halts and reducing the risk of user data loss. (Kuo, paragraph 52)
However, Park and Kuo do not explicitly teach wherein, when the consistency of the memory stored in the working page area is normal, the memory management unit is configured to load memory information of the working page area stored before soft reset and then reallocate a memory unit block of the working page area after the soft reset based on the memory information of the working page area.
In the analogous art, Lu teaches wherein, when the consistency of the memory stored in the working page area is normal, the memory management unit is configured to load memory information of the working page area stored before soft reset and then reallocate a memory unit block of the working page area after the soft reset based on the memory information of the working page area (“Upon power up, the system would revert to using Memory Register A and resume the memory management routine. Since none of the original data has been erased at this point—but merely marked as invalid in Memory Register B—reverting to Memory Register A would not cause the system to lose valid data. Instead, the swap area containing data from pages 23, 22, and 20 would be erased a second time and refilled with the data from pages 23, 22, and 20.” Par 0030) [not causing the system to lose valid data corresponds to the working page being normal; this also describes accessing/loading the state information contained in memory register A which was stored before the power event (which may also be a soft reset); then the memory management routine works on the swap area (working page) by copy/refilling (reallocating) the pages in the swap area].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Park, Kuo, and Lu before him before the effective filing date of the claimed invention, to have modified Park and Kuo to incorporate the teachings of Lu to resist power interruptions by storing memory status information, including page validity, in nonvolatile registers before a reset. Applying this method for managing page states and reallocating memory blocks enhances the page-based calibration, making it more resistant to data loss and corruption caused by unexpected power interruptions.
Regarding claim 5, Park, Kuo, and Lu teach the microcontroller of claim 1. Park further teaches wherein the control signal related to the storage of the communication setting information is generated by waiting until all of the communication setting information before reset is acquired at the same time in order to maintain the communication state before reset even after reset (“The calibration memory management module 312 is maintained in a busy state while the above working page allocation process is being performed, and processes the CCP message received from the external calibration device 320 after the working page allocation process is completed.” Par 0074 and “data transmitted due to the DNLOAD command should be retained until data copy is completed and buffer memory is required therefor.” Par 0117 and “If a new DNLOAD command is received while the buffer memory and TLB resources are already being used according to a previous DNLOAD command, the command processor 651 of the ECU 650 may transmit a command processor busy message indicating a busy state in which resource allocation is not possible,” par 0118) [the controller uses a busy state and buffer memory to wait until data and allocation processes are completed; this ensures CCP master (external device) has stable communication].
Claim 18 corresponds to claim 5 and is rejected accordingly.
Regarding claim 15, Park teaches a method for a microcontroller (ECU 470, Figure 4 and Figure 6) including a memory management unit (calibration memory management module 312, Figure 3), the method comprising:
performing, based on a soft reset event occurring in the microcontroller, a soft reset process of initializing remaining areas of a memory managed by the memory management unit other than a working page area based on a random access memory (RAM) memory for performing a calibration function (“When the ECU is initialized, a reference page may be divided into M sub reference pages each configured to have 1:1 correspondence to a virtual sub working page.” Par 0042 and “a calibration memory management module dynamically allocating memory to be used for calibration in response to the received CCP message.” Par 0052) [the CMMM executes its memory organization logic when the ECU is initialized/ in response to external messages (triggering event)] (“when the ECU 650 is initialized, a sub working page corresponding to each sub reference page is set as the sub reference page itself.” Par 0136 and “the calibration memory management module 400 configures the total working page 420 in such a manner that sub working pages not allocated to the RAM region 430 among the sub working pages included in the working page 420 refer to corresponding sub reference pages.” Par 0079 and “The calibration memory management module divides a reference page and a working page into M sub reference pages and M sub working pages, respectively, and divides a RAM region for calibration data into N subpages, in which N is less than M.” par 0052 and Figures 3-4) [upon initialization, the MMU sets remaining areas (unallocated sub working pages) to refer back to reference pages while reserving a specific RAM region for the calibration function];
when the consistency of the memory stored in the working page area is normal and the currently set page information is for a reference page, performing, by the memory management unit, the re-establishment of the memory based on a calibration variable value of a flash area (“When the ECU is initialized, a reference page may be divided into M sub reference pages each configured to have 1:1 correspondence to a virtual sub working page.” Par 0028 and “when the ECU 650 is initialized, a sub working page corresponding to each sub reference page is set as the sub reference page itself.” Par 0136 and “control program data of a vehicle should be retained even when power is not supplied to the ECU and thus is stored in non-volatile memory, e.g., flash memory.” Par 0012) [during reestablishment, the working page is referred to calibration variables stored in flash based reference]; and
when the consistency of the memory stored in the working page area is normal and the currently set page information is for a working page, performing, by the memory management unit, the re-establishment of the memory based on a variable value of a RAM area changed by calibration (“Upon determining that a sub working page corresponding to the checked sub reference page is already allocated in S909, the ECU 650 may execute the DNLOAD command in S919 by reading the buffered data block.” Par 0135 and “calibration memory management module 400 may translate a corresponding logical address into a physical address of a RAM region to change the value of calibration data corresponding to the logical address such that the changed value is reflected in the vehicle control program.” Par 0096) [when the working page is already allocated (normal consistency), the MMU uses RAM region to execute changed calibration values].
However, Park does not explicitly teach a communication module including a non-volatile memory, and a microprocessor to perform a control, maintaining a communication connection prior to the soft reset process as it is even after the soft reset process; and performing initialization according to the soft reset process, wherein maintaining the communication connection includes: generating a control signal related to a storage of communication setting information before a soft reset occurs in order to maintain a communication connection state even when the soft reset occurs, storing the communication setting information in the non-volatile memory provided in the communication module so that the communication setting information existing prior to occurrence of the soft reset event is preserved; re-establishing, after completion of the soft reset process, a logical communication connection using the stored communication setting information; and maintaining system-level communication continuity across the soft reset event based on the re-established logical communication connection, wherein the method further comprises: generating, by the memory management unit, a control signal related to storage of memory setting information before the soft reset occurs in order to maintain calibration when the soft reset occurs, determining consistency of the memory stored in the working page area before reset, and performing re-establishment of the memory after reset based on currently set page information; when the consistency of the memory stored in the working page area is normal, loading, by the memory management unit, memory information of the working page area stored before soft reset and then reallocating a memory unit block of the working page area after the soft reset based on the memory information of the working page area.
In the analogous art, Kuo teaches a communication module including a non-volatile memory (“The memory controller 110 may comprise…a storage device such as a read only memory (ROM) 112M, … and a transmission interface circuit 118,” par 0019 and Figure 1) [controller 110 with transmission interface may correspond to a communication module], and a microprocessor to perform a control function (microcontroller 112, Figure 1),
maintaining a communication connection prior to the soft reset process as it is even after the soft reset process (“activating the transmission interface circuit and relinking with the host device, completing soft reset to make the data storage device operate normally again.” Par 0007); and
performing initialization according to the soft reset process (“the soft reset may comprise performing system reset in a software manner, for example, re-executing the system execution file (or in-system programming file), or clearing the value(s) of the system register(s), in order to achieve the purpose of system reset,” par 0050),
wherein maintaining the communication connection includes:
generating a control signal related to a storage of communication setting information before a soft reset occurs in order to maintain a communication connection state even when the soft reset occurs (“In Step S40, the memory controller 110 may store an error log, and more particularly, may record associated information of a series of events starting from the occurrence of the soft errors into the error log,” par 0049 and “In Step S42, the memory controller 110 activates a watchdog module … the microprocessor 112 may activate the watchdog timer to perform soft reset;” par 0050 and paragraph 7) [critical system events are recorded in NVM (storage) before watchdog signal (control signal) initiates soft reset, allowing device to relink with hose and maintain operational state],
storing the communication setting information in the non-volatile memory provided in the communication module so that the communication setting information existing prior to occurrence of the soft reset event is preserved (“The ROM 112M of this embodiment is arranged to store a program code 112C … The transmission interface circuit 118 may conform to a specific communications specification … and may perform communications according to the specific communications specification,” par 0020 and “the soft reset may comprise … re-executing the system execution file (or in-system programming file), … in order to achieve the purpose of system reset,” par 0050) [the communication module stores program code and communication specifications (setting information) which are preserved and re-executed during soft reset];
re-establishing, after completion of the soft reset process, a logical communication connection using the stored communication setting information (“activating the transmission interface circuit and relinking with the host device, the controller completes soft reset to make the data storage device operate normally again.” Par 0009 and “Since the transmission interface circuit 118 has been re-activated, the micro-processor 112 may relink and interact with the host device 50 through the transmission interface circuit 118.” Par 0051 and “the soft reset may comprise … re-executing the system execution file (or in-system programming file), … execute soft reset to instantly restore the data storage device 100 back to the normal mode to make it continue working.” Par 0030); and
maintaining system-level communication continuity across the soft reset event based on the re-established logical communication connection (“through activating a watchdog module in the memory controller, and activating the transmission interface circuit and relinking with the host device, completing soft reset to make the data storage device operate normally again.” Par 0007) [this reestablishes logical communication connection during soft reset process],
wherein the method further comprises:
generating, by the memory management unit, a control signal related to storage of memory setting information before the soft reset occurs in order to maintain calibration when the soft reset occurs (“interrupting execution of a current procedure and activating an interruption service; … performing cache rearrangement … and programming rearranged cache data into the at least one NV memory element, to perform data recovery; and through activating a watchdog module … completing soft reset” par 0007 and “storing the cache data into the NV memory 120 to prevent any loss of cache data… make the data storage device 100 operate normally again, for example, by way of soft reset,” Par 0052) [the controller generates an interruption service (control signal) to store cache data into NVM before activating watchdog timer, thereby maintaining data across the reset], determining consistency of the memory stored in the working page area before reset (“In Step S26, the memory controller 110 determines whether the data has been sent/buffered into the volatile memory element 130… the cache head H needs to be properly corrected, to make the cache head H point towards valid cache data.” par 0046 and “In Step S28, the memory controller 110 resynchronizes the cache space of the volatile memory element 130, for example, by pulling the cache head H back to point towards the aforementioned valid cache data,” par 0047) [this checks validity of data within volatile memory (working page) and resynchronizes memory before reset is finalized], and performing re-establishment of the memory after reset based on currently set page information (“The memory controller 110 records mapping relationships between logical addresses and physical addresses of data in a logical-to-physical address mapping table” par 0021 and “ the memory controller 110 may update the group mapping tables according to a latest mapping relationship of the user data. A size of any group mapping table within the group mapping tables is preferably equal to a size of one page” par 0022 and paragraph 50) [to reestablish normal operations, the method loads latest mapping relationships stored in page-sized mapping tables];
It would have been obvious to a person having ordinary skill in the art, having the teachings of Park and Kuo before him before the effective filing date of the claimed invention, to have modified Park to incorporate the teachings of Kuo to include a communication module to reestablish a logical communication connection and initialize a microprocessor according to a soft reset process to ensure system-level continuity with calibration device across reset events, preventing system halts and reducing the risk of user data loss. (Kuo, paragraph 52)
However, Park and Kuo do not explicitly teach when the consistency of the memory stored in the working page area is normal, loading, by the memory management unit, memory information of the working page area stored before soft reset and then reallocating a memory unit block of the working page area after the soft reset based on the memory information of the working page area.
In the analogous art, Lu teaches when the consistency of the memory stored in the working page area is normal, loading, by the memory management unit, memory information of the working page area stored before soft reset and then reallocating a memory unit block of the working page area after the soft reset based on the memory information of the working page area (“Upon power up, the system would revert to using Memory Register A and resume the memory management routine. Since none of the original data has been erased at this point—but merely marked as invalid in Memory Register B—reverting to Memory Register A would not cause the system to lose valid data. Instead, the swap area containing data from pages 23, 22, and 20 would be erased a second time and refilled with the data from pages 23, 22, and 20.” Par 0030) [not causing the system to lose valid data corresponds to the working page being normal; this also describes accessing/loading the state information contained in memory register A which was stored before the power event (which may also be a soft reset); then the memory management routine works on the swap area (working page) by copy/refilling (reallocating) the pages in the swap area].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Park, Kuo, and Lu before him before the effective filing date of the claimed invention, to have modified Park and Kuo to incorporate the teachings of Lu to resist power interruptions by storing memory status information, including page validity, in nonvolatile registers before a reset. Applying this method for managing page states and reallocating memory blocks enhances the page-based calibration, making it more resistant to data loss and corruption caused by unexpected power interruptions.
Claims 3, 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Park, Kuo and Lu in view of Garofalo et al. (US 2011/0125865 A1).
Regarding claim 3, Park, Kuo and Lu teach the microcontroller of claim 1. However, Park, Kuo and Lu do not explicitly teach wherein the communication setting information includes physical communication channel information of the communication module before reset, measurement variable table registered for data measurement, page information set for calibration, and unit block information of a working page allocated for calibration.
In the analogous art, Garofalo further teaches wherein the communication setting information includes physical communication channel information of the communication module before reset (“an external computer 8 is connected to the microprocessor 2 of the electronic control unit 1 by means of a communication line 9 which operates according to the “CAN—Car Area Network” standard.” Par 0019), measurement variable table registered for data measurement (“The SRAM working memory 3 is instead intended to store the instantaneous process variables used by the control software.” Par 0004), page information set for calibration (“area C is divided into two pages C1 and C2 between them identical and redundant, each of which is aimed at storing all the calibration parameters.” Par 0021), and unit block information of a working page allocated for calibration (“the change of page C1 or C2 used by the microprocessor 2 (i.e. the modification of the virtual addresses of the calibration parameters used by the control software carried out by the memory management unit 10) is extremely fast and does not affect the engine control carried out by the electronic control unit 1; thus page C1 or C2 used by the microprocessor 2 may be changed at any time during the calibration phase thus allowing to modify the value of one or more calibration parameters, while the electronic control unit 1 is controlling an engine.” Par 0024 and “copying the entire content of the first page on the second page changing during said copying the calibration parameters so that the calibration parameters written on the second page contain the modification;” claim 1) [the page serves as a unit block].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Park, Kuo, Lu and Garofalo before him before the effective filing date of the claimed invention, to have modified Park, Kuo and Lu to incorporate the teachings of Garofalo to include specific communication setting information to lighten the burden of the workload deriving from communication with the external computer by utilizing a smart communication bridge and thus reduce overall system overhead. (Garofalo paragraph 30)
Claim 17 corresponds to claim 3 and is rejected accordingly.
Regarding claim 4, Park, Kuo, Lu and Garofalo teach the microcontroller of claim 3. Garofalo further teaches wherein the physical communication channel information includes information on a plurality of communication channels before reset when the communication module supports the plurality of communication channels (“an external computer 8 is connected to the microprocessor 2 of the electronic control unit 1 by means of a communication line 9 which operates according to the “CAN—Car Area Network” standard.” Par 0019 and “According to the alternative embodiment shown in FIG. 4, instead of the “CAN” standard, the communication line 9 uses a synchronized serial communication standard of “SPI” type; e.g. either the “Nexus” standard or the “JTAG” standard, which are typical and generally present in this type of microprocessors, may be used.” Par 0025) [there are alternate physical comm channel standards than the communication line and microprocessor can use].
Claims 6-9, 14, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park, Kuo and Lu in view of Lai et al. (US 2019/0012180 A1).
Regarding claim 6, Park, Kuo and Lu teach the microcontroller of claim 1. However, Park, Kuo and Lu do not explicitly teach wherein the communication module is configured to perform re-establishment of a communications state in response to the microprocessor being initialized.
In the analogous art, Lai teaches wherein the communication module is configured to perform re-establishment of a communications state in response to the microprocessor being initialized (“after entering the boot code mode based on the first signal stream, the MMC 502 establishes a connection with the host system 11 in the boot code mode.” Par 0063 and “The memory storage device is equipped with the ability to identify a command from the host system and to communicate with the host system after the connection is established.” Par 0004 and claim 20) [the memory storage device acts as the communication module to the host (microprocessor)].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Park, Kuo, Lu and Lai before him before the effective filing date of the claimed invention, to have modified Park, Kuo and Lu to incorporate the teachings of Lai to re-establish a communication state in response to the microprocessor being initialized by utilizing Lai’s method of establishing a connection with the host post entering the boot code mode to ensure communication with the host system. This is critical for calibration and debugging of the electronic system, especially if an abnormal operation was present.
Claim 19 corresponds to claim 6 and is rejected accordingly.
Regarding claim 7, Park, Kuo and Lu teach the microcontroller of claim 1. However, Park, Kuo and Lu do not explicitly teach the memory management unit is configured to re-establish the memory based on the stored memory setting information and the re- established communication state.
In the analogous art, Lai teaches the memory management unit is configured to re-establish the memory based on the stored memory setting information and the re-established communication state (“after entering the boot code mode based on the first signal stream, the MMC 502 establishes a connection with the host system 11 in the boot code mode.” Par 0063 and “The memory storage device is equipped with the ability to identify a command from the host system and to communicate with the host system after the connection is established.” Par 0004 and claim 20).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Park, Kuo, Lu and Lai before him before the effective filing date of the claimed invention, to have modified Park, Kuo and Lu to incorporate the teachings of Lai to re-establish the communication state in response to the microprocessor being initialized by utilizing Lai’s method of establishing a connection with the host post entering the boot code mode to ensure communication with the host system. This is critical for calibration and debugging of the electronic system, especially if an abnormal operation was present.
Claim 20 corresponds to claim 7 and is rejected accordingly.
Regarding claim 8, Park, Kuo, Lu and Lai teach the microcontroller of claim 7. Park further teaches wherein the memory setting information includes information of a calibration memory block held by the memory management unit before reset and a changed calibration value (“the calibration memory management module 312 may include relationship information about which sub reference page of the reference page 313 corresponds to which sub working page of the working page 314 (i.e., address mapping information).” Par 0073 and “ translate a corresponding logical address into a physical address of a RAM region to change the value of calibration data corresponding to the logical address such that the changed value is reflected in the vehicle control program.” Par 0095) [the calibration subpages correspond to the blocks].
Regarding claim 9, Park, Kuo, Lu and Lai teach the microcontroller of claim 7. Lai further teaches wherein the memory management unit is configured to perform re-establishment of the memory in response to the microprocessor being initialized (“after entering the boot code mode based on the first signal stream, the MMC 502 establishes a connection with the host system 11 in the boot code mode.” Par 0063 and “The memory storage device is equipped with the ability to identify a command from the host system and to communicate with the host system after the connection is established.” Par 0004 and claim 20).
Regarding claim 14, Park, Kuo and Lu teach the microcontroller of claim 1. However, Park, Kuo and Lu do not explicitly teach wherein when the consistency of the memory stored in the working page area is abnormal, the memory management unit is configured to perform initialization of the memory in a working page, initialize a memory error correction code calculation value, and initialize unit block setting information of the working page to an initial value.
In the analogous art, Lai teaches wherein when the consistency of the memory stored in a working page area is abnormal, the memory management unit is configured to perform initialization of the memory in the working page (“a setting of a connection parameter of the host system or the memory storage device is incorrect or a firmware of the memory storage device is damaged; accordingly, the connection between the memory storage device and the host system may not be successfully established.” Par 0004 and “The memory management circuit is further configured to execute a boot code according to the first signal stream and to enter a boot code mode.” Par 0008), initialize a memory error correction code calculation value (“when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates a corresponding error correcting (ECC) code and/or an error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correcting code and/or the error detecting code to the rewritable non-volatile memory module 406.” Par 0054) [the ECC code may correspond to a error correction code calculation value], and initialize unit block setting information of the working page to an initial value (“if the firmware code is not stored in the RNVM module 406, the firmware code in the RNVM module 406 is damaged, or a parameter setting in the firmware code is incorrect, the boot code mode is being remained and the firmware code in the RNVM module 406 is not executed” par 0064) [when the setting is incorrect the MMC causes system to remain in boot code mode which may correspond to an initialization action].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Park, Kuo, Lu and Lai before him before the effective filing date of the claimed invention, to have modified Park, Kuo and Lu to incorporate the teachings of Lai to initialize a memory error correction code calculation value by utilizing Lai’s method of establishing a connection with the host post entering the boot code mode to ensure communication with the host system. This is critical for calibration and debugging of the electronic system, especially if an abnormal operation was present.
Response to Arguments
Applicant's arguments filed 05/27/2026 have been fully considered but they are not persuasive. Applicant argues that Park does not teach selectively performing the re-establishment of the memory (i) based on a calibration variable value of a flash area, when the currently set page information is for a reference page; or (ii) based on a variable value of a RAM area changed by calibration when the currently set page information is for a working page, and Lu does not teach wherein, when the consistency of the memory stored in the working page area is normal, the memory management unit is configured to load memory information of the working page area stored before soft reset and then reallocate a memory unit block of the working page area after the soft reset based on the memory information of the working page area. Examiner respectfully disagrees.
Park teaches that when a calibration change is requested for data currently mapped to a reference page in flash memory, the system reestablishing memory by dynamically allocating a RAM based sub working page and copying the calibration variables from the flash area to the new region. This provides real time updates. When the currently set page is a working page, the memory is reestablished by checking the sub working page is already allocated to RAM and then directly storing the new calibration data block into that RAM region to show the updated variable value. Also see paragraphs 29, 33, 95 and 135 and Figure 4.
Lu teaches that upon power restoration after a soft reset, the memory management system uses the non-volatile memory status registers and swap segments to restore the previously stored state of memory pages into RAM. This ensures that valid data is correctly reallocated and compressed without loss. Additionally, the memory management routine checks the registers, after power restoration, if data integrity was comprised. If the data is in a valid state, this indicates that the consistency of the working page is normal. The system allocates memory in whole page blocks. These blocks are reallocated by identifying valid pages, moving them to a swap segment and “squeezing” them back into adjacent pages into a memory segment. This shows loading pre-interruption page status from non-volatile registers upon power resumption and reallocating valid page blocks into adjacent memory slots. Also see paragraphs 17, 18, 21, 23 and 25 and Figures 1 and 2.
One of ordinary skill in the art would be motivated to combine Park, Kuo and Lu because they are all directed at preservation of data integrity through synchronization of RAM and flash memory to ensure a consistent state across soft resets. This is done by using calibration variables and system statuses.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Lu et al. (US 2017/0344390 A1) teaches a method for resetting a memory in a computer system by executing boot code, updating an initialization code according to the boot code to update the initialization code, executing the updated code to restore the memory and re-executing boot code to initialize the memory and return to normal operation.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176
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