DETAILED ACTION
The response filed on March 24, 2026, is being examined.
Information Disclosure Statement
Applicants must continue to submit prior art references throughout the patent application process. A supplemental IDS must be submitted if prior art is discovered through a foreign patent application or an International Patent Search, or a related application before a prosecution closes. It is noted that no IDS submitted.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Note: The rejection under USC 102 and USC 103 below is given with modified language are given to advance prosecution; however, proper amendment to claims in next reply is required based on the explanation given in Election/Restriction section above to consider the rejection under USC 102 and USC 103; otherwise, It is considered as no claims for prosecution.
Specification
The disclosure is objected to because of the following informalities:
Specification is incomprehensive to define a seam.
Specification mentions that a seam between each of the one or more vertical interconnect arrays connected to the first and second substrate but fails to disclose how a seam between each of the one or more vertical interconnect array. Also, no drawing is present which provides clear view.
Therefore, not enough details are given about the structure of a seam. Therefore, Specification is incomprehensive.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 57 and 59-60, 63-64 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Rejection of claims 57 and 59, the limitation “a seam adjacent to the vertical interconnect array, wherein the vertical interconnect array is connected” contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art. Specification do not have clear support. It is new matter.
Specification mentions that a seam between each of the one or more vertical interconnect arrays connected to the first and second substrate but fails to disclose how a seam between each of the one or more vertical interconnect array. Also, no drawing is present which provides clear view of seam. Statement is incomplete and lacking information to one of the ordinary skill in the art can understand. It does not clearly mention that a seam adjacent to one vertical interconnect array but forgetting to a seam with whom. Therefore, it has enablement issue.
Therefore, the claims contain new matter as well as enablement issue.
Rejection of claims 60, 63-64, these claims are rejected for the same reason applied to the rejection of claim 59 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 57 and 59-60, 63-64 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Rejection of claims 57 and 59, the limitation “a seam adjacent to the vertical interconnect array, wherein the vertical interconnect array is connected” is indefinite for failing to particularly point out and distinctly claim the subject matter.
See explanation about a seam.
Therefore, claims are indefinite or unclear.
Rejection of claims 60, 63-64, these claims are rejected for the same reason applied to the rejection of claim 59 above.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102 which forms the basis for all rejections set forth in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 50-52 and 58 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) (whichever apply) as being anticipated by Sado et al. (GB2058652, herein referred to as Sado), or Takashi et al. (US4449774, herein referred to as Takashi), or Chou (US20030199181,), or Nakamura (US5041183) or Sturm (US7326068).
Rejection of claim 50, Sado (figures 4a,4b,11 in view of Figure 11 in Sado) or Takaski (figures 4-5 and 9 of Takashi) or Chou or Nakamura or Sturm discloses an integrated device package comprising: a first substrate (one of substrate 7 ad 8 as first substrate, figure 10 of Sado; alternatively one of substrate 5a and 5b as first substrate, figure 9 of Takashi); and
a vertical interconnect array(see figures 4a, 4b of Sado; alternatively see figures 4-5 of Takashi),
wherein the molding compound at a first end and a second end of the vertical interconnect array comprise a planar surface, and wherein a first end of the plurality of vertical interconnects is substantially co-planar with the molding compound at the first end of the plurality of vertical interconnects and a second end of the plurality of vertical interconnects is substantially co-planar with the molding compound at the second end of the plurality of vertical interconnects (both ends of plurality of vertical interconnects planar surfaces is substantially co-planar with the respective ends of compound structure, see figures 4a-4b, and specification of Sado; both ends of plurality of vertical interconnects planar surfaces is substantially co-planar with the respective ends of the compound structure, see figures 4-5, and specification of Takashi) ;
wherein the first end of the vertical interconnect array(see figure 10 of Sato; alternatively see figure 9 of Takashi; or similarly see figures 2-3 of Chou wherein boards 6-7 are connected to a connector 10 having plurality of vertical interconnects is substantially co-planar with the molding compound at the second end of the plurality of vertical interconnects; or similarly see figures 1-2 of Nakamura wherein boards are connected to a connector having plurality of vertical interconnects is substantially co-planar with the molding compound at the second end of the plurality of vertical interconnects; or similarly see figure 1a-1b of Sturm having plurality of vertical interconnects is substantially co-planar with the molding compound at the second end of the plurality of vertical interconnects and specification mentions the connector assembly 10 may be utilized for board-to-board, flex circuit-to-board).
Rejection of claim 51, Sato, Takashi, Chou, Nakamura, or Sturm discloses the integrated device package of Claim 50, wherein the plurality of vertical interconnects are arranged in a horizontal orientation such that a length of the plurality of vertical interconnects is greater than a height (see figure 4a-4b of Sato; alternatively see figure 5 of Takashi; or See Nakaura in figure 2).
Rejection of claim 52, Sato, Takashi, Chou, Nakamura, or Sturm discloses the integrated device package of Claim 50, wherein the plurality of vertical interconnects are arranged in a vertical orientation such that a length of the plurality of vertical interconnects is greater than a height (see one of elastomer connector in figure 10 of Sato; alternatively see figure 4 of Takashi; or see figure 2 of Chou; or See Figure 1B of Sturm ).
Rejection of claim 58, Sato, Takashi, Chou, Nakamura, or Sturm discloses the integrated device package of Claim 50, wherein the one or more vertical interconnect arrays comprise a one-dimensional array or a two-dimensional array (see the figures of Sato; alternatively, see the figures of Takashi; or see other prior arts).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 55-56 are rejected under 35 U.S.C. 103 (whichever apply) as being unpatented over by Sado or Takashi.
Rejection of claim 55, Sato, Takashi, Chou, Nakamura, or Sturm discloses the integrated device package of Claim 50, the integrated device package of Claim 50, further comprising a second substrate, wherein the second end of the one or more vertical interconnect arrays is physically and electrically connected to a first side of the second substrate, wherein the one vertical interconnect arrays are surface mounted to the first substrate, wherein the one or more vertical interconnect arrays are connected to the first substrate and the second substrate. (see substrates 7 and 8 in figure 10 of Sato; alternatively, see substrates 5a and 5b in figure 9 of Takashi ).
Sato, Takashi, Chou, Nakamura, or Sturm fail to disclose vertical interconnect arrays are connected to the first substrate and the second substrate via respective first and second conductive adhesives.
It would have been obvious as well known and old that two adjacent electronic devices connected to each other via conductive adhesive such as solder to make reliable and/or permanent connection between two adjacent electronic components so that the connection between them last longer or prevent misconnection or damage due to stress or movement. And it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Rejection of claim 56, Sato, Takashi, Chou, Nakamura, or Sturm discloses the integrated device package of Claim 50, wherein the conductive adhesive comprises solder or conductive epoxy (see rejection of claim 55 above).
Rejection of claims 57 and 59, claims 57 and 59 are rejected by Sato, Takashi, Chou, Nakamura, or Sturm as explained in the rejection of claim 1 above, furthermore a seam exists in each prior as joint between one of vertical interconnects and insulating compound.
Rejection of claim 60, see rejection of claim 60 is rejected by as rejection of claim 51.
Rejection of claim 63, see rejection of claim 64 is rejected by as rejection of claim 55-56.
Rejection of claim 64, see rejection of claim 59 as well see figures as mentioned in the prior arts.
Pertinent Prior Arts
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. Please refer to the enclosed PTO-892 form for the citation of pertinent arts in the present case, all of which disclose various boards to board interconnects assemblies.
Response to Arguments
Applicants’ arguments with respect to claim(s) have been considered but are moot because the new ground of rejection (see new references in the rejections) does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Responding to applicant arguments, in terms of arguments about restriction, note that paragraph 0019 mentions a vertical interconnect array, while paragraph 0023 cites Vertical interconnect arrays. Clear distinction is provided in the specification. And submitted claims are amended and applicant has elected claims without traverse. Additionally see further explanation of species provided in issued restriction requirement. Therefore, arguments are not persuasive.
Also, Sato and Takashi clearly show in the figures wherein a first end of the plurality of vertical interconnects is substantially co-planar with the molding compound at the first end of the plurality of vertical interconnects and a second end of the plurality of vertical interconnects is substantially co-planar with the molding compound at the second end of the plurality of vertical interconnect (see rejection above); additionally Sato clearly states “the electroconductive paths 51 and the insulating rubber base 53 have coplanar surfaces”.
Therefore. applicant arguments are not persuasive.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PARESH PAGHADAL/Primary Examiner, Art Unit 2847
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