DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 2-21 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 04 March 2024, 23 July 2024 and 04 September 2024. The information therein was considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 13 and 19, recite “…the second electrode extends along a first perimeter, and the bit line extends along a second perimeter that is within the first perimeter.” It is unclear what feature the “first perimeter” and the “second perimeter” are referring to. What is meant by the bit line is within the perimeter of the second electrode? Where is the second electrode located relative to the bit line? The specification is silent regarding a first perimeter and a second perimeter. Clarification is required. Since the scope of the claim cannot be determined no prior art is being applied.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2, 5-7, 16 and 20-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fantini et al. (US 10,128,439) (hereinafter, “Fantini”).
Re: independent claim 2, Fantini discloses in fig. 1C an apparatus, comprising: a word line comprising a first conductive material (104, col 5 ll. 11-19); a first electrode comprising a second conductive material (106, col 5 ll. 20-28), the first electrode (106) being positioned by a first side of the word line (104); a storage element comprising a chalcogenide material (110, col 5 ll. 29-30), the storage element (110) being positioned by a first side of the first electrode (106) and a first material layer (116’); a second electrode comprising a third conductive material (114, col 5 ll. 20-28), the second electrode (114) being positioned by a first side of the storage element (110) and a second material layer (118’) that is positioned by the first material layer (116’); and a bit line comprising a fourth conductive material (120, col 5 ll. 8-10), the bit line (120) being positioned by a first side of the second electrode (114).
Re: claim 5, Fantini discloses in fig. 1C the apparatus of claim 2, wherein the storage element is formed by filling a cavity between the first electrode and the second electrode (This is a product-by-process limitation, see MPEP § 2113).
Re: claim 6, Fantini discloses in fig. 1C the apparatus of claim 2, wherein: the first material layer comprises silicon nitride (116’, col 7 ll. 62-63) and is positioned by the first electrode (106), and the second material layer comprises aluminum oxide (118’, col 8 ll. 19-20) and is positioned by the first material layer (116’).
Re: claim 7, Fantini discloses in fig. 1C the apparatus of claim 2, wherein a second side of the storage element (110) and a second side of the second electrode (114) is coated with an aluminum oxide layer (118’) separating the storage element (110) and the second electrode (114) from a dielectric material (122).
Re: independent claim 16, Fantini discloses in fig. 1A an apparatus, comprising: a word line (104); a first electrode (106) positioned by a first side of the word line (104); a storage element (110) positioned by a first side of the first electrode (106) and a first material layer (given the breadth of this limitation any of layers 108, 116, 118, 122 read on the claimed first material layer); a second electrode (114) positioned by a first side of the storage element (110) and a second material layer (given the breadth of this limitation any of layers 112, 116, 118, 122 read on the claimed second material layer) that is positioned by the first material layer; a bit line (120) positioned by a first side of the second electrode (114); and a protective liner (116, 118), wherein a first edge of the first side of the second electrode (114) and a first edge of a first side of the storage element (110) are aligned and positioned by the protective liner (116, 118).
Re: claim 20, Fantini discloses in fig. 1C the apparatus of claim 16, further comprising: a second storage element (110 in 2nd stack structure 105) positioned by a second side of the second electrode (114 in 1st stack structure 105), a third electrode (106 in 2nd stack structure 105) positioned by a first side of the second storage element (110 in 2nd stack structure 105); and a second word line (104 in 2nd stack structure) positioned by a first side of the third electrode (106 in 2nd stack structure 105).
Re: claim 21, Fantini discloses in fig. 1C the apparatus of claim 16, further comprising: a second storage (110 in 2nd stack structure 105) element by the first side of the first electrode (106 in 1st stack structure), the second storage element (110 in 2nd stack structure 105) being separated from the storage element (110 in 1st stack structure 105) by at least the protective liner (116, 118).
Claim(s) 8, 10-12 and 14-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ravasio et al. (US 2015/0243708) (hereinafter, “Ravasio”).
Re: independent claim 8, Ravasio discloses in fig. 5C an apparatus, comprising: a word line (20); a first electrode (32) positioned by a first side of the word line; a storage element (34) positioned by a first side of the first electrode (32) and a first material layer (46); a second electrode (36) positioned by a first side of the storage element (34) and a second material layer (48) that is positioned by the first material layer; and a bit line (22) positioned by a first side of the second electrode (36), wherein a first edge of a first side of the bit line (22) is offset in a first direction (y-direction) from a first edge of the first side of the storage element (34), and a second edge of the first side of the bit line (22) is offset in a second direction (-y-direction) from a second edge of the first side of the storage element (34), the second direction being different than the first direction.
Re: claim 10, Ravasio discloses in fig. 5C the apparatus of claim 8, further comprising: a protective liner (47) positioned by the first electrode (32), the storage element (34), the second electrode (40), and the bit line (22).
Re: claim 11, Ravasio discloses in figs. 5C and 2N the apparatus of claim 8, further comprising: a third electrode (40 in 2nd stack) positioned by a first side of the bit line (22 in 1st stack); a second storage element (34 in 2nd stack) positioned by a first side of the third electrode, a fourth electrode (32 in 2nd stack) positioned by a first side of the second storage element; and a second word line (20 in 2nd stack in fig. 2N) positioned by a first side of the fourth electrode.
Re: claim 12, Ravasio discloses in fig. 5C the apparatus of claim 11, further comprising: a protective liner (47) positioned by the first electrode (32 in 1st stack), the storage element (34 in 1st stack), the second electrode (40 in 1st stack), and the bit line (22 in 1st stack).
Re: claim 14, Ravasio discloses in fig. 5C the apparatus of claim 8, further comprising: a third electrode (32 in 2nd stack) positioned by the first side of the word line (20); a second storage element (34 in 2nd stack) positioned by a first side of the third electrode, a fourth electrode (40 in 2nd stack) positioned by a first side of the second storage element; and a second bit line (22 in 2nd stack) positioned by a first side of the fourth electrode.
Re: claim 15, Ravasio discloses in fig. 5C the apparatus of claim 8, wherein: the first edge of the first side of the storage element (34) is aligned with a first edge of the first side of the first electrode (32) and offset in the first direction from a first edge of the first side of the second electrode (40), and the second edge of the first side of the storage element (34) is aligned with a second edge of the first side of the first electrode (32) and offset in the second direction from a second edge of the first side of the second electrode (40).
Allowable Subject Matter
Claims 3-4, 9 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 2/4/2026