DETAILED ACTION
This office action is responsive to communication filed on January 27, 2026. Claims 1-12, 14 and 16-24 are pending in the application and have been examined by the Examiner.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 16, 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 18 have been considered but are moot in view of the new grounds of rejection.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
All previous rejections under 35 USC 112 are hereby removed in view of Applicant’s response.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 14, 18-20 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Panicacci et al. (US 2021/0051287) in view of Sakakibara et al. (US 2011/0242381) and Hanzawa et al. (US 2025/0113110).
Consider claim 1, Panicacci et al. teaches:
An integrated circuit (see figures 3 and 6A) comprising:
a sensor structure (image sensor array, 302, figure 3, paragraph 0025), comprising pixels (“pixels”, paragraph 0026, 400 of figure 6A, paragraph 0036);
sets of weighting elements (Variable weighting capacitors (600) of figure 6A each comprise a bank of weighting capacitors as shown in figure 6B, paragraph 0037.), each set of weighting elements configured to weigh an output of a pixel of the sensor structure (see paragraphs 0036 and 0037),
wherein the set of weighting elements (600) is configured to weigh at least a portion of the output of the pixel in a first direction during a first time frame (i.e. in a positive direction, see step 686 of figure 6C, paragraphs 0043 and 0044) and wherein the set of weighting elements (600) is configured to weight at least a portion of the output of the pixel in a second direction during a second time frame (i.e. in a negative direction, see step 690 of figure 6C, paragraph 0045);
an output element (integrator, 620, figure 6A), the output element (620) configured to collect weighted outputs of the set of weighting elements (see paragraphs 0044 and 0045); and
an analog to digital converter (ADC block, 314, paragraph 0025).
Panicacci et al. teaches that the charge from the negative weighted outputs is subtracted from the charge of the positive weighted outputs in paragraph 0045, stating, “During this time, the charge from the negative weighted columns will subtract out from the positive weighted column values (i.e., to compute a difference between the positively weighted and negatively weighted pixel values).”
However, Panicacci et al. does not explicitly teach that the ADC is configured to count in a third direction in response to the positively weighted output during the first time frame and to count in a fourth direction opposite to the third direction in response to the negatively weighted output during the second time frame.
Sakakibara et al. similarly teaches an integrated circuit (figure 1) comprising a sensor structure (pixel array section, 12, paragraph 0099) and an ADC (AD conversion circuits, 23, paragraph 0107). Like Panicacci et al., Sakakibara et al. teaches that the output circuitry performs a “subtraction process” (see paragraph 0183).
However, Sakakibara et al. additionally teaches that in order to perform the subtraction process, the ADC (23), which includes an up/down counter (32), is configured to count in a third direction in response to a first output during a first time frame and to count in a fourth direction opposite to the first direction in response to a second output during a second time frame (“In this manner, the counting operation of the up/down counter 32 is carried out such that, for example, an up counting operation is carried out for the first time and a counting operation in the reverse direction, that is, a down counting operation, is carried out for the second time. By this counting operation, the subtraction process of the (first time comparison period) - (second time comparison period) is carried out automatically in the up/down counter 32.” paragraph 0183).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to perform the subtraction of the negatively weighted outputs from the positively weighted outputs taught by Panicacci et al. by using an ADC with an up/down counter in the manner taught by Sakakibara et al. as this only involves a simple substitution of one known element for another to obtain predictable results such as enabling the subtraction process to be performed and the and the result of the subtraction process to be retained (Sakakibara et al., paragraph 0183).
The combination of Panicacci et al. and Sakakibara et al. does not explicitly teach that the weighting elements are transistors.
Hanzawa et al. similarly teaches an integrated circuit (figure 1) having a sensor structure (pixel array unit, 11) comprising pixels (“pixels”, paragraph 0089), and further teaches that the output of a pixel (figure 27) is weighted via weight coefficients (see paragraphs 0180-0182).
Like Panicacci et al., Hanzawa et al. teaches that the weighting is performed via weighting elements (Q11-Q13) connected to a node (n1) of the of the pixel (see figure 27, paragraphs 0180-0182). However, Hanzawa et al. additionally teaches that the weighting elements (Q11-Q13) are transistors (“In this way, the circuit of the pixel 10 illustrated in FIG. 27 can perform a process of multiplying a pixel signal corresponding to electric charge acquired through photoelectric conversion performed by the photoelectric conversion unit PD by filter coefficients (weight coefficients) using the transistors Q11 to Q13 and the capacitor C.” paragraph 0182, see figure 27.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the weighting elements taught by the combination of Panicacci et al. and Sakakibara et al. comprise transistors as taught by Hanzawa et al. as this only involves a simple substitution of one known element (i.e. the weighting transistor configuration of Hanzawa et al.) for another (i.e. the weighting capacitor configuration of Panicacci et al.) to obtain predictable results such as enabling a pixel output signal to be weighted.
Consider claim 2, and as applied to claim 1 above, Panicacci et al. further teaches that the sensor structure comprises a sensor (pixel, 400, figure 6A), the sensor (400) comprising the pixels (“pixels”, paragraph 0026, 400 of figure 6A, paragraph 0036) and the sensor (400, figure 6A) is at least one of a photosensor (pixel, 400) comprising a photodiode (PD, paragraph 0029).
Panicacci et al. does not explicitly teach that the ADC is a single-slope ADC.
Sakakibara et al. teaches that the ADC is a single-slope ADC (“single slope type”, paragraph 0280).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the ADC taught by Panicacci et al. be a single-slope ADC as taught by Sakakibara et al. as this only involves a simple substitution of one known element for another to obtain predictable results such as enabling the subtraction process to be performed and the and the result of the subtraction process to be retained (Sakakibara et al., paragraph 0183).
Consider claim 3, and as applied to claim 2 above, Panicacci et al. further teaches that the sensor structure further comprises at least one of a reset element (reset transistor, paragraph 0029, see figure 4A) and an amplifying transistor (source follower transistor, paragraph 0029, see figure 4A).
Consider claim 4, and as applied to claim 3 above, Panicacci et al. further teaches that the sensor structure (400) is electrically connected with a gate of the amplifying transistor (SF, see figure 4A).
Consider claim 14, and as applied to claim 1 above, Panicacci et al. further teaches heterogeneous integration (see figure 2, paragraph 0024).
Consider claim 24, and as applied to claim 1 above, Panicacci et al. further teaches that the second direction is opposite of the first direction (i.e. positive versus negative, see claim 1 rationale).
Consider claim 18, Panicacci et al. teaches:
An integrated circuit structure (see figures 3 and 6A) comprising:
an array of cells (e.g. rows of image sensor array, 302, figure 3, paragraph 0025), each cell (i.e. each row) comprising
a sensor structure (i.e. a row of pixels, figures 3 and 6A, paragraph 0025);
a set of weighting elements (variable weighting capacitors, 600, figure 6A), each set of weighting elements configured to weigh an output of the sensor structure (see paragraphs 0036 and 0037),
wherein the set of weighting elements (600) is configured to weigh at least a portion of the output of the sensor structure in a first direction during a first time frame (i.e. in a positive direction, see step 686 of figure 6C, paragraphs 0043 and 0044) and wherein the set of weighting elements (600) is configured to weight at least a portion of the output of the sensor structure in a second direction during a second time frame (i.e. in a negative direction, see step 690 of figure 6C, paragraph 0045);
an output element (integrator, 620, figure 6A), the output element (620) configured to collect weighted outputs of the set of weighting elements (see paragraphs 0044 and 0045); and
an analog to digital converter (ADC block, 314, paragraph 0025).
Panicacci et al. teaches that the charge from the negative weighted outputs is subtracted from the charge of the positive weighted outputs in paragraph 0045, stating, “During this time, the charge from the negative weighted columns will subtract out from the positive weighted column values (i.e., to compute a difference between the positively weighted and negatively weighted pixel values).”
However, Panicacci et al. does not explicitly teach that the ADC is configured to count in a third direction in response to the positively weighted output during the first time frame and to count in a fourth direction opposite to the first direction in response to the negatively weighted output during the second time frame.
Sakakibara et al. similarly teaches an integrated circuit (figure 1) comprising a sensor structure (pixel array section, 12, paragraph 0099) and an ADC (AD conversion circuits, 23, paragraph 0107). Like Panicacci et al., Sakakibara et al. teaches that the output circuitry performs a “subtraction process” (see paragraph 0183).
However, Sakakibara et al. additionally teaches that in order to perform the subtraction process, the ADC (23), which includes an up/down counter (32), is configured to count in a third direction in response to a first output during a first time frame and to count in a fourth direction opposite to the first direction in response to a second output during a second time frame (“In this manner, the counting operation of the up/down counter 32 is carried out such that, for example, an up counting operation is carried out for the first time and a counting operation in the reverse direction, that is, a down counting operation, is carried out for the second time. By this counting operation, the subtraction process of the (first time comparison period) - (second time comparison period) is carried out automatically in the up/down counter 32.” paragraph 0183).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to perform the subtraction of the negatively weighted outputs from the positively weighted outputs taught by Panicacci et al. by using an ADC with an up/down counter in the manner taught by Sakakibara et al. as this only involves a simple substitution of one known element for another to obtain predictable results such as enabling the subtraction process to be performed and the and the result of the subtraction process to be retained (Sakakibara et al., paragraph 0183).
The combination of Panicacci et al. and Sakakibara et al. does not explicitly teach that the weighting elements are transistors.
Hanzawa et al. similarly teaches an integrated circuit (figure 1) having a sensor structure (pixel array unit, 11) comprising pixels (“pixels”, paragraph 0089), and further teaches that the output of a pixel (figure 27) is weighted via weight coefficients (see paragraphs 0180-0182).
Like Panicacci et al., Hanzawa et al. teaches that the weighting is performed via weighting elements (Q11-Q13) connected to a node (n1) of the of the pixel (see figure 27, paragraphs 0180-0182). However, Hanzawa et al. additionally teaches that the weighting elements (Q11-Q13) are transistors (“In this way, the circuit of the pixel 10 illustrated in FIG. 27 can perform a process of multiplying a pixel signal corresponding to electric charge acquired through photoelectric conversion performed by the photoelectric conversion unit PD by filter coefficients (weight coefficients) using the transistors Q11 to Q13 and the capacitor C.” paragraph 0182, see figure 27.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the weighting elements taught by the combination of Panicacci et al. and Sakakibara et al. comprise transistors as taught by Hanzawa et al. as this only involves a simple substitution of one known element (i.e. the weighting transistor configuration of Hanzawa et al.) for another (i.e. the weighting capacitor configuration of Panicacci et al.) to obtain predictable results such as enabling a pixel output signal to be weighted.
Consider claim 19, and as applied to claim 18 above, Panicacci et al. further teaches that the sensor structure comprises a sensor (pixel, 400, figure 6A) and the sensor (400, figure 6A) is at least one of a photosensor (pixel, 400) comprising a photodiode (PD, paragraph 0029).
Panicacci et al. does not explicitly teach that the ADC is a single-slope ADC.
Sakakibara et al. teaches that the ADC is a single-slope ADC (“single slope type”, paragraph 0280).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the ADC taught by Panicacci et al. be a single-slope ADC as taught by Sakakibara et al. as this only involves a simple substitution of one known element for another to obtain predictable results such as enabling the subtraction process to be performed and the and the result of the subtraction process to be retained (Sakakibara et al., paragraph 0183).
Consider claim 20, and as applied to claim 18 above, Panicacci et al. further teaches an accumulation node (integrating amplifier, 622, figure 6A) configured to accumulate charge and/or voltage from multiple of the cells of the array (see paragraphs 0042, 0044 and 0045).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Panicacci et al. (US 2021/0051287) in view of Sakakibara et al. (US 2011/0242381) and Hanzawa et al. (US 2025/0113110), as applied to claim 1 above, and further in view of Jang (US 2020/0219925).
Consider claim 17, and as applied to claim 1 above, Panicacci et al. further teaches an ADC (ADC block, 314, figure 3, paragraph 0030).
However, the combination of Panicacci et al., Sakakibara et al. and Hanzawa et al. does not explicitly teach a latched output element configured to rectify one or more output.
Jang similarly teaches an imager (figure 1) with an ADC (60), paragraph 0028.
However, Jang additionally teaches a latched output element (latch unit, 70) at the output of an ADC (60, see figure 1) configured to rectify one or more output (“The latch unit 70 latches the digital signal and the latched signal is sequentially outputted to an image signal processing unit (not shown in FIG. 1) in accordance with the decoding result in the column decoder 80.” paragraphs 0034 and 0028).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the integrated circuit taught by the combination of Panicacci et al., Sakakibara et al. and Hanzawa et al. comprise a latched output element as taught by Jang as this only involves combining prior art elements according to known methods to yield predictable results such as enabling readout of image signals.
Allowable Subject Matter
Claim 23 is allowed.
Claims 5-12, 16, 21, 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 23, the closest prior art, Panicacci et al. (US 2021/0051287) teaches:
An integrated circuit (see figures 3 and 6A) comprising:
a sensor structure (image sensor array, 302, figure 3, paragraph 0025), comprising pixels (“pixels”, paragraph 0026, 400 of figure 6A, paragraph 0036);
sets of weighting elements (Variable weighting capacitors (600) of figure 6A each comprise a bank of weighting capacitors as shown in figure 6B, paragraph 0037.), each set of weighting elements configured to weigh an output of a pixel of the sensor structure (see paragraphs 0036 and 0037),
wherein the set of weighting elements (600) is configured to weigh at least a portion of the output of the pixel in a first direction during a first time frame (i.e. in a positive direction, see step 686 of figure 6C, paragraphs 0043 and 0044) and wherein the set of weighting elements (600) is configured to weight at least a portion of the output of the pixel in a second direction during a second time frame (i.e. in a negative direction, see step 690 of figure 6C, paragraph 0045);
an output element (integrator, 620, figure 6A), the output element (620) configured to collect weighted outputs of the set of weighting elements (see paragraphs 0044 and 0045); and
an analog to digital converter (ADC block, 314, paragraph 0025).
Panicacci et al. teaches that the charge from the negative weighted outputs is subtracted from the charge of the positive weighted outputs in paragraph 0045, stating, “During this time, the charge from the negative weighted columns will subtract out from the positive weighted column values (i.e., to compute a difference between the positively weighted and negatively weighted pixel values).”
However, Panicacci et al. does not explicitly teach that the ADC is configured to count in a third direction in response to the positively weighted output during the first time frame and to count in a fourth direction opposite to the third direction in response to the negatively weighted output during the second time frame.
Sakakibara et al. (US 2011/0242381) similarly teaches an integrated circuit (figure 1) comprising a sensor structure (pixel array section, 12, paragraph 0099) and an ADC (AD conversion circuits, 23, paragraph 0107). Like Panicacci et al., Sakakibara et al. teaches that the output circuitry performs a “subtraction process” (see paragraph 0183).
However, Sakakibara et al. additionally teaches that in order to perform the subtraction process, the ADC (23), which includes an up/down counter (32), is configured to count in a third direction in response to a first output during a first time frame and to count in a fourth direction opposite to the first direction in response to a second output during a second time frame (“In this manner, the counting operation of the up/down counter 32 is carried out such that, for example, an up counting operation is carried out for the first time and a counting operation in the reverse direction, that is, a down counting operation, is carried out for the second time. By this counting operation, the subtraction process of the (first time comparison period) - (second time comparison period) is carried out automatically in the up/down counter 32.” paragraph 0183).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to perform the subtraction of the negatively weighted outputs from the positively weighted outputs taught by Panicacci et al. by using an ADC with an up/down counter in the manner taught by Sakakibara et al. as this only involves a simple substitution of one known element for another to obtain predictable results such as enabling the subtraction process to be performed and the and the result of the subtraction process to be retained (Sakakibara et al., paragraph 0183).
The combination of Panicacci et al. and Sakakibara et al. does not explicitly teach that the weighting elements are transistors.
Hanzawa et al. (US 2025/0113110) similarly teaches an integrated circuit (figure 1) having a sensor structure (pixel array unit, 11) comprising pixels (“pixels”, paragraph 0089), and further teaches that the output of a pixel (figure 27) is weighted via weight coefficients (see paragraphs 0180-0182).
Like Panicacci et al., Hanzawa et al. teaches that the weighting is performed via weighting elements (Q11-Q13) connected to a node (n1) of the of the pixel (see figure 27, paragraphs 0180-0182). However, Hanzawa et al. additionally teaches that the weighting elements (Q11-Q13) are transistors (“In this way, the circuit of the pixel 10 illustrated in FIG. 27 can perform a process of multiplying a pixel signal corresponding to electric charge acquired through photoelectric conversion performed by the photoelectric conversion unit PD by filter coefficients (weight coefficients) using the transistors Q11 to Q13 and the capacitor C.” paragraph 0182, see figure 27.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the weighting elements taught by the combination of Panicacci et al. and Sakakibara et al. comprise transistors as taught by Hanzawa et al. as this only involves a simple substitution of one known element (i.e. the weighting transistor configuration of Hanzawa et al.) for another (i.e. the weighting capacitor configuration of Panicacci et al.) to obtain predictable results such as enabling a pixel output signal to be weighted.
However, the prior art of record does not teach nor reasonably suggest at least that the set of weighting transistors comprises transistors of varying widths and/or varying widths/lengths (W/Ls); wherein each of the set of weighting transistors is configured to be selected by one or more of a set of select lines, and wherein the set of select lines is configured to apply by the set of weighting transistors weights in the first direction during the first time frame and weights in the second direction during the second time frame; wherein each of the set of select lines corresponds to a kernel and each kernel corresponds to at least a weight in the first direction and at least a weight in the second direction; wherein each of the set of weighting transistors is configured to receive a supply voltage from a supply voltage line for weights in the first direction and/or a supply voltage line for weights in the second direction; and wherein the set of weighting transistors comprises a set of weighting transistors each configured to apply a weighting based on a stored weighting value; wherein the stored weighting value is fixed and/or configured to be changed; and wherein the stored weighting value corresponds to a weighting value for a layer of a machine learning model; wherein the machine learning model is a convolutional neural network; and an output element, the output element configured to collect outputs of the sets of weighting transistors; and an analog to digital converter (ADC), wherein the ADC is configured to count in a third direction in response to the output during the first time frame and to count in a fourth direction opposite to the third direction in response to the output during the second time frame and wherein the ADC is a single-slope ADC (SS-ADC), wherein a reset of the ADC is configured to be set to a trainable parameter, the trainable parameter corresponding to batch normalization (BN), and wherein a value of the reset of the ADC depends on values stored in the sensor structure, and the integrated circuit further comprising homogeneous integration and/or heterogeneous integration, in combination with the other elements recited in claim 23.
Consider claim 5, the prior art of record does not teach nor reasonably suggest that the set of weighting transistors comprises transistors of varying widths and/or varying widths/lengths (W/Ls), in combination with the other elements recited in parent claim 1.
Claims 6-12 and 21 contain allowable subject matter as depending from claim 5.
Consider claim 16, the prior art of record does not teach nor reasonably suggest that a reset of the ADC is configured to be set to a trainable parameter, the trainable parameter corresponding to batch normalization (BN), in combination with the other elements recited in parent claim 1.
Claim 22 contains allowable subject matter as depending from claim 16.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hu (CN 113596361) teaches a pixel circuit (figure 3) with a positive weighting transistor (7) and a negative weighting transistor (8).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637