DETAILED ACTION
Notice of Pre-AIA or AIA Status
`The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Invention I (claims 1-16) and Species 1 (Fig. 1, claims 1-3, and 6-16) in the reply filed on 07/17/26 is acknowledged.
Claim Objections
Claim 10 is objected to because of the following informalities:
Claim 10 is not clear because it recites, in lines 1-2, the limitation “wherein the interposer further includes an additional conductive pad overlying and pad electrically coupled to the conductive structure” (emphasis added). For the purpose of examination, the Examiner assumes the above limitation of “wherein the interposer further includes an additional conductive pad overlying and pad electrically coupled to the conductive structure” (as recited in lines 1-2) is:
“wherein the interposer further includes an additional conductive pad overlying and electrically coupled to the conductive structure” (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S 2015/0115466 A1).
As to claim 1, Kim discloses in Fig. 1A a microelectronic device package, comprising: a microelectronic device (“semiconductor chip” 20) coupled to a substrate (“first package substrate” 10) (Fig. 1A, para. [0033], [0035]-[0037]); a stack of semiconductor dies (“semiconductor chips” 72, 74) positioned over the microelectronic device (“semiconductor chip” 20) (Fig. 1A, para. [0046]); an interposer (comprising elements 30, 31, 32, 34 and 38) positioned between the microelectronic device (“semiconductor chip” 20) and the stack of semiconductor dies (“semiconductor chips” 72, 74) (Fig. 1A, para. [0039], [0040], [0044]), the interposer (comprising elements 30, 31, 32, 34 and 38) including: a conductive structure (comprising “connecting line” 31, “connecting pads” 34, and “ground layer” 38) electrically connecting the microelectronic device (“semiconductor chip” 20) and a ground circuit (“ground layer” 19) of the substrate (“first package substrate” 10) (Fig. 1A, para. [0040], [0044]); and an insulative structure (as indicated at 30, Fig. 1A) positioned between the conductive structure (comprising “connecting line” 31, “connecting pads” 34, and “ground layer” 38) and the stack of semiconductor dies (“semiconductor chips” 72, 74) (Fig. 1A, para. [0039]-[0041]).
As to claim 2, as applied to claim 1 above, Kim discloses in Fig. 1A all claimed limitations including the limitation: wherein the interposer (comprising elements 30, 31, 32, 34 and 38) further comprises a conductive pad (32) extending between an upper surface (top surface) of the interposer (comprising elements 30, 31, 32, 34 and 38) and the conductive structure (comprising “connecting line” 31, “connecting pads” 34, and “ground layer” 38) (Fig. 1A, para. [0040]).
As to claim 6, as applied to claim 1 above, Kim discloses in Fig. 1A all claimed limitations including the limitation: wherein the conductive structure (comprising “connecting line” 31, “connecting pads” 34, and “ground layer” 38) is electrically connected to the microelectronic device (“semiconductor chip” 20) through conductive adhesive (“first via-connecting terminals” 28) (Fig. 1A, para. [0032], [0034], [0044], [0047]).
As to claim 8, as applied to claim 1 above, Kim discloses in Fig. 1A all claimed limitations including the limitation: wherein the stack of semiconductor dies (“semiconductor chips” 72, 74) comprises a stack of memory dies (Fig. 1A, para. [0046]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S 2015/0115466 A1) in view of Karnezos (U.S 2004/0056277 A1).
As to claim 3, as applied to claims 1 and 2 above, Kim discloses in Fig. 1A all claimed limitations including the limitation: wherein the conductive pad (32) of the interposer (comprising elements 30, 31, 32, 34 and 38) is connected to a ground pad (19) of the substrate (10) through a via-connecting terminal (28) (Fig. 1A, para.[0044]).
Kim does not disclose the conductive pad of the interposer is connected to a ground pad of the substrate through a wire bond.
However, Karnezos discloses in Fig. 6B a device package comprising: a conductive pad (“trace” 1031) of the interposer (comprising “dielectric layer” 1012 and “traces” 1031) is connected to a ground pad (“metal layer” 353 including “ground lines”, para. [0084]) of the substrate (comprising 342, 356) through a wire bond (1018) (Fig. 6B, para. [0082], [0084], [0086]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify the device package of Kim by replacing the via-connecting terminal with a wire bond to connect the interposer pad to the substrate ground pad, as taught by Karnezos. One skilled in the art would have been motivated to implement this modification, alongside adjusting the substrate’s size to accommodate the wire layout, in order to streamline the package line by utilizing the wire bond, thereby shortening manufacturing turnaround time, providing flexible connection, reducing thermal and mechanical stress on the interposer and substrate interfaces, and reducing overall production costs.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S 2015/0115466 A1) in view of CHIU (U.S 2022/0123521 A1).
As to claim 7, as applied to claims 1 and 6 above, Kim discloses in Fig. 1A all claimed limitations except for the conductive adhesive that includes one or more of metal paste, conductive tape, and conductive epoxy.
However, CHIU discloses in Fig. 2A a package comprising: a conductive structure (231) of an interposer (230) is electrically connecting to a chip 205 via a conductive adhesive (“conductive epoxy”, para. [0070]), wherein the conductive adhesive (“conductive epoxy”, para. [0070]) that includes one or more of metal paste, conductive tape, and conductive epoxy (“conductive epoxy”, para. [0070) (see Fig. 2A, para. [0070]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Kim’s device package by using the conductive adhesive that includes one or more of metal paste, conductive tape, and conductive epoxy as taught by CHIU, in order to reduce the thermal and mechanical stress between the interfaces of the interposer and the chip.
Claim(s) 9 and 11-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karnezos (U.S. 2004/0056277 A1) in view of Shin (U.S 2022/0091776 A1).
As to claim 9, Karnezos discloses in Fig. 6B a memory device, comprising: a substrate (comprising “package substrate” 342 and “dielectric layer” 356) including conductive pads (“metal layers” 351) (Fig. 6B, para. [0082]), ground pads (“patterned metal layers” 353 include “ground lines”, para. [0084]), and dielectric material (at least “dielectric layer” 356 include dielectric material) separating the conductive pads (“metal layers” 351) and the ground pads (“patterned metal layers” 353) (see Fig. 6B, para. [0082]); a first semiconductor die (344) electrically coupled to one or more of the conductive pads (“metal layers” 351) of the substrate (comprising “package substrate” 342 and “dielectric layer” 356) (Fig. 6B, para. [0082]); an interposer (comprising “dielectric layer” 1012 and “traces” 1031) over the first semiconductor die (344) and including a conductive structure (“traces” 1031) electrically coupled to the first semiconductor die (344), the conductive structure (“traces” 1031) electrically coupled to at least one ground pad (“patterned metal layer” 353) of the ground pads (“patterned metal layers” 353) of the substrate (comprising “package substrate” 342 and “dielectric layer” 356) through a first wire bond (1018) (Fig. 6B, para. [0085]-[0086]); and a second semiconductor die (1034) positioned over the interposer (comprising “dielectric layer” 1012 and “traces” 1031) and electrically isolated from the first semiconductor die (344) by an insulative structure (“dielectric layer” 1012) of the interposer (comprising “dielectric layer” 1012 and “traces” 1031) (Fig. 6B, para. [0085], [0086]), the second semiconductor die (1034) electrically coupled to one of the conductive pads (“metal layers” 351) of the substrate (comprising “package substrate” 342 and “dielectric layer” 356) through a second wire bond (1036) (Fig. 6B, para. [0086]).
Karnezos does not disclose the substrate includes semiconductor material.
However, Shin discloses in Fig. 2 a device package comprising: a substrate (225) includes a ground plane (see Fig. 2, para. [0035]), wherein the substrate (225) includes semiconductor material (the substrate may be a semiconductor substrate that includes semiconductor material or silicon material, para. [0106]) (Fig. 2, para. [0035], [0106]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Karnezos’s device by utilizing a substrate that includes semiconductor material as taught by Shin, in order to provide controllable electrical conductivity and enhance signal switching efficiency between the conductive pads and the ground.
As to claim 11, as applied to claim 9 above, Karnezos and Shin disclose all claimed limitations including the limitation: wherein a lateral edge of the interposer (comprising “dielectric layer” 1012 and “traces” 1031) extends beyond a lateral end of the second semiconductor die (1034) positioned over the interposer (comprising “dielectric layer” 1012 and “traces” 1031) (see Fig. 6B in Karnezos).
As to claim 12, as applied to claims 9 and 11 above, Karnezos and Shin disclose all claimed limitations including the device further comprising: one or more additional semiconductor dies (1044) stacked over the second semiconductor die (1034), wherein the one or more additional semiconductor dies (1044) are partially laterally offset from the second semiconductor die (1034) and the lateral edge of the interposer (comprising “dielectric layer” 1012 and “traces” 1031) is positioned within a footprint defined by a laterally offset lateral end of the one or more additional semiconductor dies (1044) (see Fig. 6B, para. [0086] in Karnezos).
As to claim 13, as applied to claim 9 above, Karnezos and Shin disclose all claimed limitations including the limitation: wherein the one of the one or more conductive pads (“metal layers” 351) of the substrate (comprising “package substrate” 342 and “dielectric layer” 356) comprises an additional ground pad (“the sandwiched metal layer 355 serves as a ground plane”, para. [0084]) (see Fig. 6B, para. [0084] in Karnezos).
As to claim 14, as applied to claims 9 and 13 above, Karnezos and Shin disclose all claimed limitations including the limitation: wherein the additional ground pad (“the sandwiched metal layer 355 serves as a ground plane”, para. [0084]) is positioned on an opposite side of the first semiconductor die (344) from the at least one ground pad (“metal layer” 353) coupled to the conductive structure (“traces” 1031) of the interposer (comprising “dielectric layer” 1012 and “traces” 1031) (see Fig. 6B, para. [0084] in Karnezos).
As to claim 15, as applied to claim 9 above, Karnezos and Shin disclose all claimed limitations including the limitation:
wherein the one of the one or more conductive pads (“metal layers” 351) of the substrate (comprising “package substrate” 342 and “dielectric layer” 356) comprises an additional ground pad (an additional ground pad may be a second pad/pattern/layer 353, Fig. 6B, para. [0084]) (see Fig. 6B, para. [0084] in Karnezos); and
wherein the additional ground pad (a second pad/pattern/layer 353, Fig. 6B, para. [0084]) is positioned on a same side of the first semiconductor die (344) as the at least one ground pad (“metal layer” 353) coupled to the conductive structure (“traces” 1031) of the interposer (comprising “dielectric layer” 1012 and “traces” 1031) (see Fig. 6B, para. [0084] in Karnezos).
As to claim 16, as applied to claim 9 above, Karnezos and Shin disclose all claimed limitations including the limitation:
wherein the one of the one or more conductive pads (“metal layers” 351) of the substrate (comprising “package substrate” 342 and “dielectric layer” 356) comprises an additional ground pad (an additional ground pad may be a second pad/pattern/layer 353, Fig. 6B, para. [0084]) (see Fig. 6B, para. [0084] in Karnezos); and
wherein the additional ground pad (a second pad/pattern/layer 353, Fig. 6B, para. [0084]) includes the at least one ground pad (“patterned metal layer” 353) coupled to the conductive structure (“traces” 1031) of the interposer (comprising “dielectric layer” 1012 and “traces” 1031) (see Fig. 6B, para. [0084] in Karnezos).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karnezos (U.S. 2004/0056277 A1) in view of Shin (U.S 2022/0091776 A1) as applied to claim 9 above, and further in view of PARK et al. (U.S 2020/0343163 A1).
As to claim 10, as applied to claim 9 above, Karnezos and Shin disclose all claimed limitations except for the limitation: wherein the interposer further includes an additional conductive pad overlying and electrically coupled to the conductive structure, the additional conductive pad partially defining a top surface of the interposer and the first wire bond is coupled to the conductive structure through the additional conductive pad.
However, PARK et al. disclose in Fig. 4 a device comprising: an interposer (423) that includes an additional conductive pad (“conductive pattern” 423a/423c) overlying and electrically coupled to the conductive structure (“conductive pattern” 423b), the additional conductive pad (“conductive pattern” 423a/423c) partially defining a top surface of the interposer (423) and the first wire bond (432) is coupled to the conductive structure (423b) through the additional conductive pad (“conductive pattern” 423a/423c) (Fig. 4, para. [0047]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify Karnezos’s device in view of Shin by ultilizing an interposer that includes an additional conductive pad overlying and electrically coupled to the conductive structure, the additional conductive pad partially defining a top surface of the interposer and the first wire bond is coupled to the conductive structure through the additional conductive pad as taught by PARK et al., in order to enhance electrical conductivity and ensure a reliable electrical connection between the interposer and the chip/substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kikuma et al. (U.S 2002/0027295 A1), Kim et al. (U.S 2022/0165680 A1), and Cablao et al. (U.S. 2008/0185719 A1) disclose a device package comprising an interposer between the first and second chips.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817
September 29, 2026
