DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the Applicant’s amendments filed on 03/25/2026. Claims 1-15 remain pending in the application. Claims 1-15 have been amended. Any examiner’s note, objection, and rejection not repeated is withdrawn due to Applicant’s amendment.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
This application claims priority to JP-2021-024926, filed 02/19/2021. The claim for foreign priority is acknowledged by the Examiner.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/11/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Examiner’s Note
The Examiner cites particular columns, paragraphs, figures, and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may also apply. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in its entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The Examiner notes that [0006], line 4 of the instant specification recites “...rform a process of...”, containing the apparent typographical error “rform”, which appears intended to read “perform”. Correction is recommended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa et al. (US 20210240616 A1) hereafter Stabrawa in view of Roozbeh et al. (US 20220058123 A1) hereafter Roozbeh, further in view of Hackborn et al. (US 20090113444 A1) hereafter Hackborn.
Regarding claim 1, Stabrawa teaches:
a respective piece of implementation data of a plurality of pieces of implementation data (Paragraph 204; “memory-allocation data structure(s) may include one or more indicators which convey whether one or more portions of the region 214 and/or of the external memory allocation have been allocated”, “For example, the one or more data structures may include one or more collections of portions which may be allocated to a corresponding application logic and/or which may be unallocated. In some examples, the one or more data structures may convey whether portion(s) of the region 214 and/or of the external memory allocation have been allocated”, teaches implementation data associated with respective memory portions/allocation areas, corresponding to the claimed pieces of implementation data.);
the respective piece of implementation data of the plurality of pieces of implementation data (Paragraph 204; “memory-allocation data structure(s) may include one or more indicators which convey whether one or more portions of the region 214 and/or of the external memory allocation have been allocated”, “For example, the one or more data structures may include one or more collections of portions which may be allocated to a corresponding application logic and/or which may be unallocated. In some examples, the one or more data structures may convey whether portion(s) of the region 214 and/or of the external memory allocation have been allocated”, which teaches implementation data associated with particular memory portions.)
a central processing unit (CPU) (Paragraph 52; “The processor 240 may be a general processor, a central processing unit (CPU)”) configured to:
indicating that a first service of the plurality of services is in a blank personalized state (Paragraph 204; “one or more indicators which convey whether one or more portions of the region... have been allocated”, and “one or more collections of portions which may be allocated... and/or which may be unallocated” teaches determining whether a memory portion is allocated or unallocated. Consistent with the description in the instant specification of a blank personalized state being one that is unallocated to any service (see Paragraph 39), therefore the cited passage corresponds to indicating that the service is in a blank personalized state. Because a system cannot utilize indicators conveying allocation status without determining the status represented by those indicators, reading and evaluating the indicators constitutes detection of the allocation state.), wherein the first service is associated with a first piece of implementation data of the plurality of pieces of implementation data (Paragraph 204; “memory-allocation data structure(s) may include one or more indicators which convey whether one or more portions of the region 214 and/or of the external memory allocation have been allocated”, “For example, the one or more data structures may include one or more collections of portions which may be allocated to a corresponding application logic and/or which may be unallocated. In some examples, the one or more data structures may convey whether portion(s) of the region 214 and/or of the external memory allocation have been allocated”, which teaches implementation data associated with particular memory portions);
the first piece of implementation data is in a first allocation area of the plurality of allocation areas (Paragraph 204; “indicator(s) may be associated with and/or included in one or more data structures which identify one or more portions of the region 214 and/or of the external memory allocation” teaches implementation data stored in association with identified memory portions, corresponding to a first allocation area of a plurality of allocation areas.);
change a service-determined allocation area state of the first allocation area to a service-undetermined allocation area state of the first allocation area (Paragraph 204; “memory-allocation data structure(s) may include one or more indicators which convey whether one or more portions of the region 214 and/or of the external memory allocation have been allocated”, which teaches allocation indicators that represent whether memory portions are allocated or unallocated.).
wherein the first allocation area includes the first piece of implementation data in the service-determined allocation area state (Paragraph 204; “memory-allocation data structure(s) may include one or more indicators which convey whether one or more portions of the region 214 and/or of the external memory allocation have been allocated”, “the indicator(s) may be associated with and/or included in one or more data structures which identify one or more portions of the region 214 and/or of the external memory allocation”, which teaches that memory allocation areas, corresponding to allocation areas, include identified portions associated with stored data and allocation status indicators, corresponding to the first allocation area including the first piece of implementation data in an allocation area including implementation data in an allocated, corresponding to service-determined, area state.);
in the service-undetermined allocation area state (Paragraph 204; “memory-allocation data structure(s) may include one or more indicators which convey whether one or more portions of the region 214 and/or of the external memory allocation have been allocated”, “the one or more data structures may include one or more collections of portions which may be allocated to a corresponding application logic and/or which may be unallocated”, which teaches allocation areas which are an unallocated state as indicated by allocation indicators, corresponding to a service-undetermined allocation area state.);
perform, after the first allocation area is in the service-undetermined allocation area state, an operation to store, in the first allocation area, a second piece of implementation data of the plurality of pieces of implementation data (Paragraph 204; “one or more collections of portions which may be allocated... and/or which may be unallocated” and “data structures which identify one or more portions of the region 214 and/or of the external memory allocation” teaches memory allocation structures in which unallocated portions are available for subsequent allocation and storage of data, corresponding to performance of a process that stores new implementation data for an application/process, corresponding to a service, into a previously unallocated allocation area.);
Stabrawa does not teach a memory that includes a plurality of allocation areas; the blank personalized state is associated with a deletion of the first piece of implementation data from the first allocation area; based on the first service that is in the blank personalized state; the respective service of the plurality of services; based on the first service that is in the blank personalized state; the first service is absent from the first allocation area; wherein the second piece of implementation data corresponds to a second service of the plurality of services.
However, Roozbeh teaches:
a memory that includes a plurality of allocation areas (Paragraph 58; “allocated portions of physical memory” and “free portions of physical memory” teach a memory having multiple physical memory portions corresponding to a plurality of allocation areas.), wherein the memory is configured to store, in each allocation area of the plurality of allocation areas, a respective service of a plurality of services (Paragraph 58; “monitoring memory portions for a given application/process/CPU core” and “related to high priority application” teaches memory portions associated with respective applications/processes, which correspond to the plurality of services stored in the allocation areas.);
the respective service of the plurality of services (Paragraph 58; “monitoring memory portions for a given application/process/CPU core”, teaches applications/processes associated with particular memory portions, corresponding to respective services.);
based on the first service that is in the blank personalized state (Paragraph 58; “application/process/CPU core.... monitoring memory portions”, which teaches services associated with memory usage whose state is monitored, thereby providing the service context for triggering memory management actions.);
the first service is absent from the first allocation area (Paragraph 58; “monitoring memory portions for a given application/process/CPU core” and “keeping information regarding allocated portions of physical memory and their addressing as well as... free portions of physical memory” teaches services implemented as applications/processes whose memory usage is actively tracked, including distinguishing between memory that is allocated to a service and memory that is free or no longer associated with the service, corresponding to the first service being absent from the first allocation area when the service is not using or no longer associated with the memory.);
wherein the second piece of implementation data corresponds to a second service of the plurality of services (Paragraph 58; “monitoring memory portions for a given application/process/CPU core” teaches services implemented as applications/processes associated with memory portions whose data are managed in memory, corresponding to implementation data being associated with a respective service.);
perform the service issuance process (Paragraph 58; “Accelerator function may for example be responsible for monitoring memory portions for a given application/process/CPU core, keeping information regarding allocated portions of physical memory and their addressing, keeping information regarding free portions of physical memory and their addressing as well as performing the migration of data. It may also be responsible to pre-allocating a suitable memory portion for given data, i.e., by communicating with a Memory allocator and a Slice selection function. This function may further be responsible for updating the page table.”, which discloses a runtime memory management system where a memory allocator and slice selection function allocate and assign memory portions to applications/processes, corresponding to services, which functionally corresponds to a service issuance process that provisions an allocation area to a service.)
Stabrawa and Roozbeh are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the memory allocation data structures of Stabrawa, including a memory with a plurality of allocation areas, a service of a plurality of services that may be placed in an allocation area, performing actions based on a service in an unallocated state, performing actions based on a service being absent from the allocation area in memory, and having implementation data correspond to a service, into the memory management system of Roozbeh, thereby implementing the known method of maintaining allocation information for memory portions using metadata and associated data structures and performing actions based on the associated data structures, within which an association between a particular implementation and a service may be defined, yielding the predictable result of improved tracking, organization, and allocation, thereby issuing, of resources assigned to a particular service. Further, it would have been obvious to have implemented the known method of updating allocated/unallocated indicators in response to allocation/deallocation events, yielding the predictable result of maintaining accurate state information.
Stabrawa in view of Roozbeh does not teach the blank personalized state is associated with a deletion of the first piece of implementation data from the first allocation area.
However, Hackborn teaches:
the blank personalized state is associated with a deletion of the first piece of implementation data from the first allocation area (Paragraph 61; “When an application is killed, the application becomes a dropped application and any associated application memory 218 is erased and made available to other applications”, which teaches that upon termination of an application/service, associated memory is erased, corresponding to deletion of implementation data from the first allocation area resulting in a blank personalized state.).
Stabrawa, Roozbeh, and Hackborn are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh to incorporate the teachings of Hackborn and incorporate the application termination and memory erasure techniques into the system of Stabrawa in view of Roozbeh. A person of ordinary skill in the art would have recognized that incorporation of the application termination and memory erasure techniques of Hackborn with the allocation tracking and memory region indicator system of Stabrawa in view of Roozbeh would be an implementation of the known method of updating allocation status data structures in response to service termination and memory reclamation, yielding the predictable result of accurately reflecting that memory associated with a terminated service is freed for reuse.
Claim 13 recites similar limitations as those of claim 1, additionally reciting a CPU configured to control transmission of a command to a terminal device to perform a service issuance process; the terminal device includes a memory, and the service issuance process is based on the command. Stabrawa teaches:
a CPU (Paragraph 52; “The processor 240 may be a general processor, a central processing unit (CPU)”.) configured to control transmission of a command to a terminal device to perform a service issuance process (Paragraph 109; “allocation logic 412 may address region access logic requests to the region access logic 212 included in one or more memory appliances. The region access logic requests may be requests handled via an interface of the region access logic 212” and “the region access logic requests may be messages transmitted via the communication interface(s) 230, 330, 430”, such as “requests to create the region 214”, which teaches allocation logic on a management server which transmits requests, corresponding to commands, to region access logic on a memory appliance, corresponding to a terminal device. The transmitted requests include requests to create a region among other memory region-management operations. Under the previously established interpretation that a service issuance process comprises allocating an available allocation area and storing implementation data corresponding to a service therein (see claim 1), the create-region/allocation operations correspond to performing the service issuance process.);
the terminal device includes a memory (Paragraph 45; “client-side memory access may facilitate the client 130 accessing the memory 210 on the memory appliance 110” and “client 130 may read, write, and/or perform other operations on the memory 210, to the regions 214 within the memory 210”, which teaches a client device that performs r/w operations involving memory regions. Although memory 210 is located in a memory appliance, client device is configured with client-side memory access which enable direct memory operations. This configuration implies a terminal device structured to interface and operate on memory as part of its memory access architecture, thereby corresponding to the terminal device including a memory.), and the service issuance process is based on the request(Paragraph 109; “allocation logic 412 may address region access logic requests to the region access logic 212 included in one or more memory appliances”, and “For example, region access logic requests received by the region access logic 212 may include requests to create the region 214”. A management/processing entity transmits requests, corresponding to commands, to a memory appliance region access logic 212 which trigger operations such as creation, modification, restoration, and destruction of regions. Therefore, the service issuance process is controlled by such transmitted commands.).
Hackborn teaches:
the command (Paragraph 41; “The application terminator 214 may, in response to receiving an appropriate command from the kernel 212, erase one or more applications 216 from memory 260.”).
It would have been obvious to employ the command-driven control of Hackborn in the memory management framework of Stabrawa in view of Roozbeh because using control commands by system components is a known technique, yielding the predictable result of enabling controlled execution of functionality.
Claim 13 is rejected for similar reasons as those of claim 1.
Claim 15 recites similar limitations as those of claim 1, additionally reciting a non-transitory computer-readable medium having stored thereon, computer executable instructions. Stabrawa teaches:
a non-transitory computer-readable medium (Paragraph 428; “The computer-readable storage media may be non-transitory computer-readable media, which includes CD-ROMs, volatile or non-volatile memory such as ROM and RAM, or any other suitable storage device.”) having stored thereon, computer executable instructions (Paragraph 52; “processor 240 may include one or more devices operable to execute computer executable instructions or computer code embodied in the memory 210 or in other memory to perform features of the external memory system.”).
Claim 15 is rejected for similar reasons as those of claim 1.
Regarding claim 2, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Stabrawa teaches:
based on each of the plurality of allocation areas that is in the service determined allocation area state (Paragraph 204; “memory-allocation data structure(s) may include one or more indicators which convey whether one or more portions of the region 214 and/or of the external memory allocation have been allocated”, “The one or more data structures may be organized to facilitate efficient memory allocation and/or deallocation. For example, the one or more data structures may include one or more collections of portions which may be allocated to a corresponding application logic and/or which may be unallocated”, which teaches allocation areas in memory which distinguish between allocated and unallocated portions and enable operations to be performed on those portions based on allocation status, corresponding to performing an operation based on allocation areas in a service-determined state.).
Roozbeh teaches:
perform the service issuance process (Paragraph 58; “Accelerator function may for example be responsible for monitoring memory portions for a given application/process/CPU core, keeping information regarding allocated portions of physical memory and their addressing, keeping information regarding free portions of physical memory and their addressing as well as performing the migration of data. It may also be responsible to pre-allocating a suitable memory portion for given data, i.e., by communicating with a Memory allocator and a Slice selection function. This function may further be responsible for updating the page table.”, which discloses a runtime memory management system where a memory allocator and slice selection function allocate and assign memory portions to applications/processes, corresponding to services, which functionally corresponds to a service issuance process that provisions an allocation area to a service.).
Claim 14 recites similar limitations as those of claim 2. Claim 14 is rejected for similar reasons as those of claim 2.
Regarding claim 11, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Stabrawa teaches:
the CPU (Paragraph 52; “The processor 240 may be a general processor, a central processing unit (CPU)”);
and the plurality of allocation areas (Paragraph 204; “indicator(s) may be associated with and/or included in one or more data structures which identify one or more portions of the region 214 and/or of the external memory allocation” teaches implementation data stored in association with identified memory portions, corresponding to a plurality of allocation areas).
Roozbeh teaches:
perform a middleware process (Paragraph 58; “responsible for monitoring memory portions”, “keeping information regarding allocated portions”, “pre-allocating a suitable memory portion”, “updating the page table” actions are performed by the software layer of the Accelerator function which corresponds to middleware processes managing memory allocation and migration), and management of the memory is based on a command from the server apparatus(Paragraph 58; “portions of physical memory… mapped to the slices associated to the CPU core accessing that data” where the physical memory regions tracked by the Accelerator function correspond to the memory area. The Accelerator function is further “responsible for monitoring memory portions, keeping information regarding allocated and free portions, pre-allocating suitable memory portions, performing migration, and updating page table entries”, showing that the memory area is managed by the Accelerator, corresponding to the middleware).
Regarding claim 12, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 11. Stabrawa teaches:
the plurality of allocation areas (Paragraph 204; “indicator(s) may be associated with and/or included in one or more data structures which identify one or more portions of the region 214 and/or of the external memory allocation” teaches implementation data stored in association with identified memory portions, corresponding to a plurality of allocation areas).
Roozbeh teaches:
the middleware process (Paragraph 58; Accelerator function corresponds to middleware) is associated with a server apparatus (Paragraph 58; “communicating with a Memory allocator and a Slice selection function”, where the Accelerator software issues instructions and receives communications to or from other system components. The memory allocator is disclosed as “can be implemented in HW as part of server” in Paragraph 57, thereby being associated with a server apparatus.);
the management of the memory is based on communication from the server apparatus (Paragraph 58; Accelerator function performs “monitoring memory portions”, “keeping information regarding allocated portions of physical memory and their addressing”, “keeping information regarding free portions of physical memory and their addressing”, and “performs the migration of data”, demonstrating that the Accelerator manages the memory area. Paragraph 58 further discloses “communicating with a Memory allocator and a Slice selection function”, where the Accelerator software issues instructions and receives communications to or from other system components, one of the system components being the memory allocator which is disclosed as “can be implemented in HW as part of server” in Paragraph 57, thereby managing memory based on communication from a server apparatus.).
Hackborn teaches:
a command (Paragraph 41; “The application terminator 214 may, in response to receiving an appropriate command from the kernel 212, erase one or more applications 216 from memory 260.”).
It would have been obvious to employ the command-driven control of Hackborn in the memory management framework of Stabrawa in view of Roozbeh because using control commands by system components is a known technique, yielding the predictable result of enabling controlled execution of functionality.
Claims 3, 5, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa in view of Roozbeh, further in view of Hackborn, further in view of Takagi (US 20160198477 A1).
Regarding claim 3, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Stabrawa in view of Roozbeh, further in view of Hackborn does not teach wherein the first service is associated with an IC card.
However, Takagi teaches:
wherein the first service is associated with an IC card. (Paragraph 67; “The ISO-RW 3 senses, based on the response received, that the ISO application to execute is contained in the IC card 1. The ISO-RW 3 in turn transmits a selection command to select this ISO application to the IC card 1”, where the ISO application corresponds to the service providable by an IC card, thereby being associated with an IC card.).
Stabrawa, Roozbeh, Hackborn, and Takagi are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh, further in view of Hackborn to incorporate the teachings of Takagi and apply the known IC card-based services to the apparatus of Stabrawa in view of Roozbeh, further in view of Hackborn. A person of ordinary skill in the art would have recognized that the use of known methods of providing a service by an IC card would yield predictable results as IC-card systems are known to provide of secure storage, service identifiers, and access rights, and the incorporation of IC card-based services would function in the same predictable manner as in other known systems.
Regarding claim 5, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1 does not teach wherein the implementation data includes user-specific data.
However, Takagi teaches:
wherein the plurality of pieces of implementation data includes user-specific data. (Paragraph 135; “the EEPROM 316 stores user data and other data to be used by application software.” User data used by application software corresponds to user-specific data, which is among the group of data to be used by application software, corresponding to the plurality of pieces of implementation data.).
Stabrawa, Roozbeh, Hackborn, and Takagi are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh, further in view of Hackborn to incorporate the teachings of Takagi and incorporate user-specific data into the implementation data. A person of ordinary skill in the art would have recognized that the application of known techniques for enabling user-individualized service execution in the context of the apparatus taught by Stabrawa in view of Roozbeh, further in view of Hackborn would yield the predictable result of proper operation of the service for each individual user.
Regarding claim 8, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Stabrawa in view of Roozbeh, further in view of Hackborn does not teach a contactless IC chip, wherein the contactless IC chip includes the memory, and the memory is a non-volatile memory.
However, Takagi teaches:
a contactless IC chip, wherein the contactless IC chip includes the memory, and the memory is a non-volatile memory (Paragraph 135; “The IC chip 310 includes the communications processor 4, the controller 5, and the memory 6. The memory 6 includes a ROM 312, a RAM 314, and an EEPROM 316. The ROM 312 stores application software or platform operating system (OS) which does not have to be altered. The RAM 314 stores data to function as a working memory mainly for the controller 5. The EEPROM 316, a nonvolatile memory, retains data even when the supply voltage supplied to the IC card 1 becomes lower than its operating voltage.“ Paragraph 30 further describes the contactless limitation, “As used herein, “contactless” means that a terminal extended from an IC chip in the card is not connected to the reader/writer via a cable or wire. Thus, even if the IC card is put in physical contact with the reader/writer, their communication may still be called “contactless communication.” In particular, the reader/writer will be sometimes hereinafter referred to as a “device.””).
Stabrawa, Roozbeh, Hackborn, and Takagi are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh, further in view of Hackborn to incorporate the teachings of Takagi and use a memory area in non-volatile memory incorporated in a contactless IC chip. A person of ordinary skill in the art would have been motivated to use an IC chip because it is a known method to implement wireless communication and remote data exchange between devices, yielding the predictable result of enabling efficient wireless command transmission of memory management operations. Further, a person of ordinary skill in the art would have been motivated to use a non-volatile memory in a contactless IC chip because the use of non-volatile memory to retain data when power is removed is known in the art and the use of such memory in IC chips would provide the predictable results of retaining information in memory when power is removed, ensuring continuity of stored data without requiring continuous power.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa in view of Roozbeh, further in view of Hackborn, further in view of Gruber et al. (US 20130311997 A1) hereafter Gruber.
Regarding claim 4, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Roozbeh teaches:
a number of services (Paragraph 57; “The OS 80 is running on a server 5 that can host different applications; Application 1, Application 2, etc.” teaching multiple applications, corresponding to a plurality of services.).
Stabrawa in view of Roozbeh, further in view of Hackborn does not teach a service corresponds to a service provider.
However, Gruber teaches:
a service corresponds to a service provider (Paragraph 126; “user is authorized to use a software application associated with the particular third party service provider”).
Stabrawa, Roozbeh, Hackborn, and Gruber are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh, further in view of Hackborn to incorporate the teachings of Gruber and apply the service-provider association to the plurality of services of Stabrawa in view of Roozbeh, further in view of Hackborn, thereby providing a respective service provider for each service, thereby corresponding to a number of the plurality of services corresponding to a number of service providers, which would yield the predictable result of maintaining provider-specific service management.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa in view of Roozbeh, further in view of Hackborn, further in view of Rezayee et al. (US 11893581 B1) hereafter Rezayee.
Regarding claim 6, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Stabrawa teaches:
the plurality of allocation areas (Paragraph 204; “indicator(s) may be associated with and/or included in one or more data structures which identify one or more portions of the region 214 and/or of the external memory allocation” teaches implementation data stored in association with identified memory portions, corresponding to a plurality of allocation areas).
Stabrawa in view of Roozbeh, further in view of Hackborn does not teach being in a secure element.
However, Rezayee teaches:
being in a secure element (Col. 5, lines 17-22; “NFC device 12 may be an electronic device such as a smart phone, tablet, or smart watch that is capable of engaging in secure transactions with payment terminal 20 (e.g., via communications with payment reader 22). NFC device 12 may have hardware (e.g., a secure element including hardware and executable code)”).
Stabrawa, Roozbeh, Hackborn, and Rezayee are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh, further in view of Hackborn to incorporate the teachings of Rezayee and have the allocation areas be within a secure element. A person of ordinary skill in the art would have recognized that the use of secure elements are well-known in the art for providing tamper-resistant storage for sensitive data, and the usage of such would have yielded predictable benefits of enhanced data security, controlled access, and compliance with established security standards.
Regarding claim 7, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Stabrawa teaches:
the information processing apparatus (Paragraph 45; “client 130 may read, write, and/or perform other operations on the memory 210... the client-side memory access may be based on the Remote Direct Memory Access (RDMA) protocol”, and Paragraph 109; “allocation logic 412 may address region access logic requests to the region access logic 212 to which the requests are sent... [and] associated with the management servers including the allocation logic 412”, which teaches a distributed computing system comprising multiple parts which collectively perform information processing functions such as receiving requests, transmitting messages, managing memory allocation, and executing memory access operations, thereby corresponding to an apparatus configured to process information.);
the plurality of allocation areas (Paragraph 204; “indicator(s) may be associated with and/or included in one or more data structures which identify one or more portions of the region 214 and/or of the external memory allocation” teaches implementation data stored in association with identified memory portions, corresponding to a plurality of allocation areas).
Stabrawa in view of Roozbeh, further in view of Hackborn does not teach being connected to a device via a near field communication network.
However, Rezayee teaches:
being connected to a device via a near field communication network (Col. 5, lines 17-22; “NFC device 12 may be an electronic device such as a smart phone, tablet, or smart watch that is capable of engaging in secure transactions with payment terminal 20 (e.g., via communications with payment reader 22). NFC device 12 may have hardware (e.g., a secure element including hardware and executable code)”).
Stabrawa, Roozbeh, Hackborn, and Rezayee are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh, further in view of Hackborn to incorporate the teachings of Rezayee and adapt the information processing apparatus such that it is accessible by a device to be connected of communicating through NFC to access the plurality of allocation areas of Stabrawa in view of Roozbeh, further in view of Hackborn. A person of ordinary skill in the art would have recognized that the implementation of known NFC access methods to the memory structures would achieve the predictable result of allowing conventional NFC devices to read/write to memory which would include the allocation areas within the memory, thus providing the expected benefit of improving interoperability between systems.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa in view of Roozbeh, further in view of Hackborn, further in view of Romagnoli et al. (US 20120136786 A1) hereafter Romagnoli.
Regarding claim 9, Stabrawa in view of Roozbeh, further in view of Hackborn teach the apparatus of claim 1. Stabrawa teaches:
the plurality of allocation areas (Paragraph 204; “indicator(s) may be associated with and/or included in one or more data structures which identify one or more portions of the region 214 and/or of the external memory allocation” teaches implementation data stored in association with identified memory portions, corresponding to a plurality of allocation areas).
Stabrawa in view of Roozbeh, further in view of Hackborn does not teach management based on a specification defined by GlobalPlatform.
However, Romagnoli teaches:
management based on a specification defined by GlobalPlatform (Paragraph 27; “For example, in this embodiment, the secure memory 4 is compliant with the GlobalPlatform Card Specifications (available at), and accordingly includes a plurality of security domains for facilitating control of the management of and accessibility to functionality and sensitive data associated with specific areas of the secure memory”).
Stabrawa, Roozbeh, Hackborn, and Romagnoli are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh, further in view of Hackborn to incorporate the teachings of Romagnoli and manage the plurality of allocation areas in accordance with a GlobalPlatform specification. A person of ordinary skill in the art would recognize GlobalPlatform as a widely adopted well-known industry standard for secure element lifecycle management. The application of the known GlobalPlatform specification to the plurality of allocation areas would have yielded the predictable result of enabling independent allocation, storage, and management of multiple services and their associated data within memory.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Stabrawa in view of Roozbeh, further in view of Hackborn, further in view of Romagnoli, further in view of Li et al. (US 20130042244 A1) hereafter Li.
Regarding claim 10, Stabrawa in view of Roozbeh, further in view of Hackborn, further in view of Romagnoli teach the apparatus of claim 9. Roozbeh teaches:
wherein a server apparatus deletes the first service from the first allocation area (Paragraph 57; “Memory allocator is an entity that is responsible for allocating memory from available physical memory to an application upon application requests... Applications can be moved, i.e., migrated from one CPU core to another if decided by the system”, which teaches a system-level modification of resource to service assignments, i.e. removal of a prior assignment, functionally supporting a deletion/removal of a service from an allocation area.).
Stabrawa in view of Roozbeh, further in view of Hackborn, further in view of Romagnoli does not teach based on a specific command, and the server apparatus allocates the first allocation area to the first service.
However, Li teaches:
based on a specific command, and the server apparatus allocates the first allocation area to the first service (Paragraph 61; “if the authentication code of the access module 24 passes the verification of the application management module 23 and the application management module 23 is requested to delete the authentication code, and the application management module 23 directly deletes the authentication code of this access module 24, and if the access module 24 requests the application management module 23 to modify the authentication code, then the application management module 23 re-allocates an authentication code to the access module 24”, which teaches explicit deletion of assigned information associated with a service-associated identifier from an allocation-related structure based on a specific command. In response, it reallocates the authentication code back to the same allocation structure after deletion, corresponding to reassigning the allocation resource back to the same service following a delete operation.).
Stabrawa, Roozbeh, Hackborn, Romagnoli, and Li are considered to be analogous to the claimed invention because they are in the same field of memory allocation. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Stabrawa in view of Roozbeh, further in view of Hackborn, further in view of Romagnoli to include the resource lifecycle management techniques of Li, because deletion and subsequent reallocation of resources represent the application of the known technique of resource deallocation and reassignment upon request on a known system, yielding the predictable result of enabling controlled deletion and reassignment of resources.
Response to Arguments
Applicant's arguments filed 03/25/2026 have been fully considered. Applicant’s arguments are summarized below:
Amendments to claims 13-14 no longer invoke interpretation under 35 U.S.C. 112(f). Associated rejections under 35 U.S.C. 112(a) and 35 U.S.C. 112(b) should be withdrawn.
Amendments to claims 10 and 12 remedy deficiencies under 35 U.S.C. 112(b).
Rejection of claim 15 under 35 U.S.C. 101 should be withdrawn in light of the amendments to claim 15.
The prior art of record does not teach, suggest, or render obvious the limitation of “detect that a first service of the plurality of services is in a blank personalized state, wherein... the personalized-blank state is associated with a deletion of the first piece of implementation data from the first allocation area”, as recited in amended independent claims 1, and 13.
Dependent claims are submitted as allowable for at least the above reasons.
Examiner’s response:
The amendments to claims 13-14 no longer recite a command generation unit, instead directing the invention towards a CPU. Therefore, claims 13-14 no longer invoke interpretation under 35 U.S.C. 112(f). Accordingly, the rejections of claims 13-14 under 35 U.S.C. 112(a) and 35 U.S.C. 112(b) are withdrawn.
The Examiner agrees that the amendments to claims 10 and 12 remedy deficiencies under 35 U.S.C. 112(b) by removing references to “FeliCa (registered trademark)” (Claim 10) and clarifying the direction of communication with the middleware (Claim 12). Accordingly, the rejections of claims 10 and 12 under 35 U.S.C. 112(b) are withdrawn.
The Examiner agrees that the amendments to claim 15 adding “non-transitory computer-readable medium” to the preamble cause the claim to no longer be drawn to software per se. Accordingly, the rejection of claim 15 under 35 U.S.C. 101 is withdrawn.
The Examiner agrees that the prior art of record does not teach the amended limitation(s). Accordingly, the previous rejections of claims 1 and 13 under 35 U.S.C. 103 are withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Stabrawa, Roozbeh, and Hackborn, under 35 U.S.C. 103.
Independent claims 1, 13, and 15 remain rejected for the reasons stated above. Therefore, contrary to Applicant's arguments, because the dependent claims depend from an unpatentable claim and does not add limitations that overcome the rejection, it likewise remains rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Koning et al. (US 6895583 B1) teaches a memory space availability check and subsequent operations in response to the memory being saturated utilizing user task information data structures for assignment and reassignment of tasks within the same memory-mapped locations while remaining assigned to the original task.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH P TRAN whose telephone number is (571)272-6926. The examiner can normally be reached M-TH 4:30 a.m. - 12:30 p.m. PT, F 4:30 a.m. - 8:30 a.m. PT, or at Kenneth.Tran@uspto.gov.
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/KENNETH P TRAN/Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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