DETAILED ACTION
Status
1. This Office Action is responsive to claims filed for application no. 18546294 on August 14, 2023. Please note claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1-8 and 10-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20070109249 A1) in view of Yamazaki et al. (US 20060082568 A1).
Regarding claim 1, Lee discloses: A semiconductor device (see Fig. 3, discloses the liquid crystal display device) comprising:
a source driver (see Fig. 3, [0042], data driver 550), wherein the source driver comprises a plurality of shift register groups (see Fig. 4A, [0056], examiner reads the shift registers (i. e. odd numbered shift register 561) connected to clock signal CKH as a first group and shift registers (i. e., even numbered shift registers 561) connected to clock signal CKHB as a second group), each of the plurality of shift register groups comprises a plurality of shift registers (see Fig. 3, Fig. 4A, [0044]-[0046], discloses data driver 550 includes a shift register unit 560 having a plurality of shift registers 561), each of the plurality of shift registers is electrically connected to a corresponding pixel circuit through a data line (see Fig. 3, Fig. 4A, [0044]-[0046], discloses the each of the shift register unit 561 are electrically connected to corresponding pixel circuit through data line DL);
at least one data input terminal electrically connected to a first stage shift register of each of the plurality of shift register groups (see Fig. 4A, input of data voltages VR1, VG1, VB1, VR2, VG2, and VB2 electrically connected to shift registers); and
a plurality of clock lines, each of the plurality of clock lines being electrically connected to each shift register in a same one of the plurality of shift register groups (see Fig. 4A, [0056], discloses each of the odd-numbered shift registers transmits the output in synchronization with the clock signal CKH, and each of the even-numbered shift registers transmits the output in synchronization with the clock signal CKHB. In a case where the above-described j-th shift register SR(j) transmits the output signal SRout(j) in synchronization with the clock signal CKH, the shift registers SR(j-1) and SR(j+1) corresponding to the previous and next even-numbered shift registers transmit the output signals SRout(j-1) and SRout(j+1) in synchronization with the clock signal CKHB).
Lee does not explicitly teach an insulating substrate comprising a source driver.
However, it has been well known in the display device would have used a source driver over the insulating substrate. For example, Yamazaki teaches an insulating substrate comprising a source driver (see Fig. 3, [0060], discloses source signal line driver circuits 303a and 303b over the substrate 300 having an insulating surface).
Therefore, in view of teachings of Lee and Yamazaki, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device as taught by Lee with Yamazaki’s teachings of an insulating substrate comprising a source driver, as a known way to physically implement a display device that comprises a source driver, and in order to improve electrical efficiency, reduce switching loss and enhance reliability of the display device.
Regarding claim 2, Lee in view of Yamazaki teaches the limitations of parent claim 1. Lee further teaches, wherein the plurality of clock lines are configured to transmit a plurality of clock signals having a same frequency and different phases respectively (see Fig. 4A, Fig. 5, discloses the clock signals CKH and CKHB having a same frequency and different phases as shown in timing diagram in figure 5).
Regarding claim 3, Lee in view of Yamazaki teaches the limitations of parent claim 1. Lee further teaches wherein the shift registers of the plurality of shift register groups are arranged alternately in sequence (see Fig. 4A, odd-numbered shift registers connected to clock signal CKH and even-numbered shift registers connected to clock signal CKHB are arranged alternately in sequence as shown in figure).
Regarding claim 4, Lee in view of Yamazaki teaches the limitations of parent claim 2. Lee further teaches wherein a clock line of the plurality of clock lines for transmitting a clock signal with a more delayed phase is electrically connected to a shift register group of the plurality of shift register groups arranged further back (see Fig. 4A, Fig. 5, clock signals CKH and CKHB that electrically connected to shift registers and corresponding timing diagram).
Regarding claim 5, Lee in view of Yamazaki teaches the limitations of parent claim 1. Lee further teaches wherein the plurality of shift register groups comprises a first shift register group (see Fig. 4A, odd-numbered shift registers electrically connected to clock signal CKH) and a second shift register group (see Fig. 4A, even-numbered shift registers connected to clock signal CKHB), and the at least one data input terminal is electrically connected to the first shift register group and the second shift register group (see Fig. 4A, input of data voltages VR1, VG1, VB1, VR2, VG2, and VB2 electrically connected to shift registers); and
the plurality of clock lines comprises a first clock line and a second clock line (see Fig. 4A, clock signals CKH and CKHB), the first clock line is electrically connected to one of the first shift register group or the second shift register group, and the second clock line is electrically connected to another of the first shift register group or the second shift register group (see Fig. 4A, [0056], odd-numbered shift registers electrically connected to clock signal CKH, even-numbered shift registers connected to clock signal CKHB) and
Regarding claim 6, Lee in view of Yamazaki teaches the limitations of parent claim 5. Lee further teaches wherein the plurality of shift register groups comprises a first shift register and a second shift register arranged alternately in sequence, the first shift register group comprises the first shift register, and the second shift register group comprises the second shift register (see Fig. 4A, odd-numbered shift registers and even-numbered shift registers 561 alternatively arranged in data driver circuit 550); and
the first clock line is electrically connected to the first shift register group (see Fig. 4A, [0056], odd-numbered shift registers electrically connected to clock signal CKH), the second clock line is electrically connected to the second shift register group (see Fig. 4A, even-numbered shift registers connected to clock signal CKHB), the first clock line is configured to transmit a first clock signal, the second clock line is configured to transmit a second clock signal, and a phase of the second clock signal is delayed from a phase of the first clock signal (see Fig. 4A, clock signals CKH and CKHB and corresponding timing diagram in Fig. 5).
Regarding claim 7, Lee in view of Yamazaki teaches the limitations of parent claim 6. Lee further teaches wherein a frequency of the first clock signal is the same as a frequency of the second clock signal, and a difference between the phase of the first clock signal and the phase of the second clock signal is 1800 (see Fig. 4A, Fig. 5, the frequency of clock signals CKH and CKHB are same and phase difference between the clock signals CKH and CKHB are 1800 as illustrated timing diagram in Fig. 5).
Regarding claim 8, Lee in view of Yamazaki teaches the limitations of parent claim 1. Lee further teaches wherein the source driver further comprises signal processing modules, an input terminal of each of the signal processing modules is electrically connected to an output terminal of a shift register of the shift registers, and each of the signal processing modules outputs a corresponding data signal (see Figs. 4, [0044]-[0047], transmission gate units TGU connected to shift registers to output corresponding data signal through data lines DL).
Regarding claim 10, Lee in view of Yamazaki teaches the limitations of parent claim 1. Yamazaki further teaches wherein at least one of the at least one data input terminal and the plurality of clock lines is disposed in the insulating substrate (see Fig. 3, Fig. 15, [0060], input terminal 307 and source signal line driver circuits 303a and 303b comprising clock signals are disposed in the substrate 300 having an insulating surface).
Regarding claim 11, Lee in view of Yamazaki teaches the limitations of parent claim 1. Yamazaki further teaches: A display panel (see Fig. 3) comprising the semiconductor device according to claim 1 (see rejection in claim 1 above), wherein the data input terminal is configured to transmit a digital signal ([0035], discloses the data driver 500 receives the digital image signals DAT for a row (group) of pixels PX and selects the gray voltages corresponding to the individual digital image signals DAT).
Regarding claims 12-18 and 20: claims 12-18 and 20 each recites the similar limitations as in claims 2-8 and 10 respectively. Therefore, claims 12-18 and 20 are also rejected on the same ground of obviousness as used above in claims 2-8 and 10.
6. Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20070109249 A1) in view of Yamazaki et al. (US 20060082568 A1), further in view of Chung et al. (US 20110199353 A1).
Regarding claim 9, Lee in view of Yamazaki teaches the limitations of parent claim 8. Lee in view of Yamazaki does not explicitly teach wherein each of the signal processing modules comprises a latch, a level converter, a digital-to-analog converter, and an amplifier that is electrically connected in sequence, an input terminal of the latch is electrically connected to an output terminal of the shift register, a trigger terminal of the latch is electrically connected to a data enable line, and the amplifier is configured to output a corresponding data signal.
However, in the same field of endeavor of data/source driver circuit of the display device, Chung teaches wherein each of the signal processing module comprises a latch (see Fig. 6, first and second latch circuits), a level converter (see Fig. 6, [0057], level shifter circuit 400), a digital-to-analog converter (see Fig. 6, decoder DEC), and an amplifier that is electrically connected in sequence (see Fig. 6, amplifier AMP), an input terminal of the latch is electrically connected to an output terminal of the shift register (see Fig. 6, input terminal of the first latch/second latch circuits are connected to output terminal of the shift registers S/R1a to S/Rna respectively), a trigger terminal of the latch is electrically connected to a data enable line (see Fig. 6, S_LAT signal line connected to second latch circuit 300), and the amplifier is configured to output a corresponding data signal (see Fig. 6, AMP that output data/source signal through S1-Sn).
Therefore, in view of teachings of Lee, Yamazaki and Chung, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the source driver circuit of semiconductor device as taught by Lee and Yamazaki with Chung’s teachings of signal processing modules of source driver circuit comprises a latch, a level converter, a digital-to-analog converter, and an amplifier that is electrically connected in sequence, an input terminal of the latch is electrically connected to an output terminal of the shift register, a trigger terminal of the latch is electrically connected to a data enable line, and the amplifier is configured to output a corresponding data signal, in order to efficiently deliver data signal to the pixels of the display panel, reduce the current consumption and reduce circuit size (Chung, [0079]).
Regarding claim 19: claim 19 recites the similar limitations as in claim 9. Therefore, claim 19 is also rejected on the same ground of obviousness as used above in claim 9.
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (US 20090278779 A1) teaches similar disclosure of the source driver circuit of display device (see Figs. 2-5).
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KRISHNA P. NEUPANE whose telephone number is (571)270-7291. The examiner can normally be reached on Monday - Friday, 8:30am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BENJAMIN C. LEE can be reached on (571) 272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KRISHNA P NEUPANE/Primary Examiner, Art Unit 2629