DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 and 11-13, due to their dependency, recite the limitation “the cladding layer includes a central portion and a peripheral portion that have a lower resistance than the peripheral portion of the tunnel junction layer.” It is unclear whether the limitation requires the resistance of both the central portion and the peripheral portion of the cladding layer to be lower than the peripheral portion of the tunnel junction layer or, alternatively, between the central portion and the peripheral portion of the cladding layer a resistance value lower than the peripheral portion of the tunnel junction layer. With the second interpretation as long as either the peripheral portion or the central portion has a lower resistance then the other portion could have a higher resistance and still meet the claim language. For purposes of claim interpretation, either is assumed to be valid. If the applicant desires the more restrictive claim interpretation where both the resistance of the central portion and the resistance of the peripheral portion of the cladding layer are lower than the peripheral portion of the tunnel junction layer, claim 10 should be amended to clarify the requirement.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 6-8, 10-12, 14, 16-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2009/0213892 (Onishi).
For claim 1, Onishi teaches a surface emitting laser (fig. 1 and 2B) comprising:
a first reflector and a second reflector (fig. 1 and 2B, 13 and 25, [0021]); and
a resonator between the first reflector and the second reflector (fig. 1 and 2B, 13 and 25 define a resonator; vertical cavity), the resonator including an active layer (fig. 1 and 2B, 15, [0021]) and a tunnel junction layer (fig. 1 and 2B, 21 is a tunnel junction layer as it forms a tunnel junction with a second tunnel junction layer 19, [0026]), wherein
the tunnel junction layer includes a central portion (fig. 1 and 2B, central portion of 21 above 19), and a peripheral portion that surrounds the central portion of the tunnel junction layer (fig. 1 and 2B, peripheral portion of 21 on sides of 19),
the peripheral portion of the tunnel junction layer has a higher resistance than the central portion of the tunnel junction layer at least in an entire region (“an entire region” may be the portion of the device under electrode 33a) in a thickness direction of the tunnel junction layer (fig. 2B, tunnel junction layer 21 blocks current along with layer where the tunnel junction is not formed with layer 19, [0024]; note that while a tunnel junction is not formed in the peripheral portion, the tunnel junction layer is present),
the active layer includes a central portion (fig. 2B, 17 in 35a), and a peripheral portion that surrounds the central portion of the active layer (fig. 2B, 17 in 37a), and
the peripheral portion of the active layer has a higher resistance than the central portion of the active layer at least in a portion of the active layer ([0034], high resistivity from ion implantation on lower side of tunnel junction layer) on a side of the tunnel junction layer (fig. 2B, active layer 15 is on a lower side of tunnel junction layer 21).
For claim 2, Onishi teaches the resonator includes a cladding layer between the tunnel junction layer and the active layer (fig. 1 and 2B, 17),
a portion of the cladding layer includes a central portion (fig. 2B, 35), and a peripheral portion that surrounds the central portion of the portion (fig. 2B, 37),
the portion of the cladding layer is on the side of the tunnel junction layer (fig. 2B, cladding layer 17 is on the lower side of tunnel junction layer 21), and
the peripheral portion of the portion on the side of the tunnel junction layer has a higher resistance than the central portion of the portion (fig. 2B, resistance of 37 greater than resistance of 35, [0035]).
For claim 3, Onishi teaches the cladding layer is a p-type semiconductor layer ([0021]).
For claim 6, Onishi teaches the resonator includes a cladding layer (fig. 2B, 23) on a side of the active layer (top side of active layer 15) opposite to the side of the tunnel junction layer (fig. 2B, 23 is on the top side of layer 21 and “the side of the tunnel junction layer” has antecedent basis in claim 1 and was defined as the lower side of 21; therefore, 23 is “opposite to the side of the tunnel junction layer”), and
The cladding layer includes a central portion (23 above 19) and a peripheral portion (23 above 37a) have a lower resistance than the peripheral portion of the tunnel junction layer (fig. 2B current passes through the central and peripheral portion of 23 from electrode 33a to tunnel junction between 19 and 21 while the peripheral portion of tunnel junction layer blocks current [0024]; a resistance of layer 23 in central and peripheral portions is therefore lower a resistance of the peripheral portion of the tunnel junction layer).
For claim 7, Onishi teaches an electrode on the cladding layer (fig. 2B, 33a).
For claim 8, Onishi teaches the cladding layer is an n-type semiconductor layer ([0028]).
For claim 10, Onishi teaches the resonator includes a cladding layer (fig. 2B, 29) on the side of the tunnel junction layer (“the side of the tunnel junction layer” has antecedent basis in claim 1 and was defined as the lower side of 21; 29 is on the lower side of 21) opposite to a side of the active layer (fig. 2B, 29 is opposite to the top side of active layer 15), and
the cladding layer includes a central portion (fig. 2B, 29 in 35a) and a peripheral portion (fig. 2B, 29 in 37a) that have a lower resistance than the peripheral portion of the tunnel junction layer (fig. 2B current passes through the central 29 while the peripheral portion of tunnel junction layer blocks current [0024]; a resistance of cladding layer 29 is therefore lower a resistance of the peripheral portion of the tunnel junction layer).
For claim 11, Onishi teaches an electrode on the cladding layer (fig. 2B, 33a is on cladding layer 29 along with intervening layers).
For claim 12, Onishi teaches the cladding layer is an n-type semiconductor layer ([0031]).
For claim 14, Onishi teaches a peripheral portion of the resonator is increased in resistance by ion implantation at least in the entire region in the thickness direction of the tunnel junction layer ([0034]).
For claim 16, Onishi teaches an impurity in the ion implantation includes at least one of H, B, C, or O ([0034]).
For claim 17, Onishi teaches the tunnel junction layer further includes a p-type semiconductor region (fig. 1 and 2B, 19, [0025]) and an n-type semiconductor region (fig. 1 and 2B, 21, [0026]), and
each of the p-type semiconductor region and the n-type semiconductor region includes one of an InP-based compound semiconductor, an AlGaInAs-based compound semiconductor, or an AlGaInSbAs-based compound semiconductor body ([0025]-[0026]).
For claim 20, Onishi is applied according to the rejection of claim 1 above. Onishi’s device of fig. 1 and 2B is an electronic device.
Claim Rejections - 35 USC § 103
Claim 4, 9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0213892 (Onishi) in view of US 6,810,064 (Coldren).
For claim 4, Onishi teaches the cladding layer includes a p-type compound semiconductor ([0021]).
Onishi does not teach the p-type compound semiconductor cladding layer is InP.
However, Coldren teaches a cladding layer (fig. 1, 4 and 6) may be made of InP (col. 3, l. 59) with the benefit of high thermal conductivity (col. 4, l. 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the InP of Coldren as a simple substitution for the compound semiconductor of Onishi as the substituted components and their functions were known in the art and the substitution would have yielded predictable results. In the present case, the substituted component provides an alternative cladding layer with the alternative benefit of high thermal conductivity. See MPEP 2143 I.B.
For claim 9, Onishi teaches the cladding layer includes a n-type compound semiconductor ([0028]).
Onishi does not teach the n-type compound semiconductor cladding layer is InP.
However, Coldren teaches a cladding layer (fig. 1, 4 and 6) may be made of InP (col. 3, l. 59) with the benefit of high thermal conductivity (col. 4, l. 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the InP of Coldren as a simple substitution for the compound semiconductor of Onishi as the substituted components and their functions were known in the art and the substitution would have yielded predictable results. In the present case, the substituted component provides an alternative cladding layer with the alternative benefit of high thermal conductivity. See MPEP 2143 I.B.
For claim 13, Onishi teaches the cladding layer includes an n-type semiconductor layer ([0031]).
Onishi does not teach the n-type compound semiconductor cladding layer is InP.
However, Coldren teaches a cladding layer (fig. 1, 4 and 6) may be made of InP (col. 3, l. 59) with the benefit of high thermal conductivity (col. 4, l. 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the InP of Coldren as a simple substitution for the compound semiconductor of Onishi as the substituted components and their functions were known in the art and the substitution would have yielded predictable results. In the present case, the substituted component provides an alternative cladding layer with the alternative benefit of high thermal conductivity. See MPEP 2143 I.B.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0213892 (Onishi).
For claim 15, Onishi does not teach an impurity concentration in the ion implantation is less than 1 × 1019 cm-3. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to determine the required impurity concentration including less than 1 × 1019 cm-3 in order to form Onishi’s resistance region, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0213892 (Onishi) in view of US 2022/0045476 (Fujii).
For claim 18, Onishi further teaches a substrate (fig. 2B, 27) and a reflector (fig. 2B, 13) closer to the active layer (fig. 2B, 15) than the tunnel junction layer (fig. 2B, 21) among the first reflector and the second reflector (fig. 2B, 13 and 25).
Onishi does not teach the substrate between the resonator and the reflector closer to the active layer, wherein the reflector is a concave multilayer film reflector. However, Fujii does teach a VCSEL (fig. 7) comprising a substrate (fig. 7, 11) between the resonator (fig. 7, layers above substrate 11 and below mirror 42; note this usage of the term resonator is consistent with applicant’s resonator R shown in fig. 1 of the instant application) and the lower reflector, wherein the reflector is a concave multilayer film reflector (fig. 1, 41, [0118]) in order to avoid diffraction loss ([0119]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the substrate and concave mirror configuration of Fujii with the invention of Onishi in order to avoid diffraction loss.
For claim 19, Onishi further teaches the substrate is GaAs (fig. 2B, 27; table 1) which inherently has a thermal conductivity that is 40 W/m · K or more.
Response to Arguments
Applicant's arguments filed 7/8/2026 have been fully considered but they are not persuasive. Regarding Onishi, see page 10, applicant argues that Onishi has no peripheral portion of the tunnel junction layer with a higher resistance. While the applicant is correct in stating that the tunnel junction is only formed in the central region, the tunnel junction layer 21 does extend into a peripheral portion with a high resistance as described at [0024] of Onishi. Claim 1 as written requires a tunnel junction layer in the peripheral portion and not a tunnel junction per se. Applicant could amend independent claim 1 to require the tunnel junction itself to extend into the peripheral portion which would distinguish the claimed invention from Onishi. However, an updated search and consideration would be required before determining patentability.
The rejections of independent claim 1 over Coldren or Inoue have been withdrawn based on applicant’s amendment to claim 1 and are therefore moot.
Applicant’s discussion of official notice beginning at page 15 is moot as the current rejection does not rely upon official notice.
Applicant argues that the remaining claims are allowable due to their dependency; however, as claim 1 is not deemed allowable, the remaining claims cannot be allowable based solely on their dependency.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael W Carter whose telephone number is (571)270-1872. The examiner can normally be reached M-F, 9:00-5:30.
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/Michael Carter/Primary Examiner, Art Unit 2828
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