DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is made in response to applicant’s amendment filed on 03/02/2026. Claims 1-3, 6, 7, 9-12, 14-16, 18, 20, 21, 23 and 26 are currently pending in the application. Claims 3, 11, 20, 21, 23 and 26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species as indicated by the applicant, there being no allowable generic or linking claim. Claims 1, 2, 6, 7, 9, 10, 12, 14-16 and 18 are considered as follows:
Response to Arguments
In response to the first set of rejections under 35 U.S.C. 102 and 103 in the previous Office action dated 11/28/2025, Applicant has amended independent claim 1 and provided on pages 11-13 of the amendment arguments, which have been fully considered but they are not persuasive as follows:
(a) Applicant’s argument, “First … driving circuit” on page 12 of the amendment, not persuasive because (i) the current claim 1 does not limit the pixel circuit driven at a low frequency or a second driving frequency and the Applicant has tried to argue Chai’s features different from the current claim and the application; and (ii) as discussed in the previous Office action and repeated below, Chai, at Figs. 3B and 4, explicitly discloses the transistor MS1 turned on and off under the control of the signal VC and at ¶ 114 “… during the second period T2, the first stabilizing transistor MS1 is set to the turn-on state …,” i.e., when the signal VC [[as the claimed second scan signal]] has a low level voltage, the [[compensation]] N-type transistor MS1 [[as the claimed transistor T1 of this application]] is not previously turned on in the first/initialization period T1 and when the signal VC [[as the claimed second scan signal]] has a high level voltage, the [[compensation]] N-type transistor MS1 [[as the claimed transistor T1 of this application]] is set to turn on from and during the second period T2 [[as the claimed write-in compensation phase]] to conduct between a first terminal of the driving circuit [M1] and the connection node [[a connection node between the elements [MS1, M3] in order to connect these two elements].
(b) Applicant’s argument, “Second, no connection node is provided between MS 1 and M3 in Chai … present application” on page 12 of the amendment, not persuasive because (i) as discussed in the above response (a) a connection node between the elements [MS1, M3] must be existed in order to connect a terminal of the element MS1 to a terminal of the element M3 and (ii) in response to applicant's argument that the present application solves one of the technical problems, the fact that applicant has recognized another problem and another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
(c) Applicant’s argument, “Third, MS1 in Chai is controlled to be turned on/off by the control power source VC, with its gate electrode connected to the control power source VC … It is well known to those skilled in the art that the control power source VC and a scanning line are two completely different concepts in the display field and cannot be regarded as equivalent. Moreover, Chai also discloses a second scanning line S2i connected to M4. It can thus be seen that Chai has already distinguished between a scanning line and the control power supply VC, which confirms that they cannot be equivalent” on pages 12-13 of the amendment, not persuasive because since it is well known to those skilled in the semiconductor/ display art that the N-type transistor MS1 is controlled to be turned on when a signal provided to a gate electrode of the transistor MS1 has a high level and to be turned off when the signal provided to the gate electrode of the transistor MS1 has a low level and Chai, specifically at ¶ 114, discloses “… during the second period T2, the first stabilizing transistor MS1 is set to the turn-on state …,” i.e., when the signal VC has a low level voltage, the N-type transistor MS1 is not previously turned on in the first period T1 and when the signal VC has a high level voltage, the N-type transistor MS1 is set to turn on from and during the second period T2, the control power source line VC carries a voltage signal having a high level and a low level and the second scan signal [S2] of this application similarly has a high level and a low level (see at least Fig. 4 of this application.)
Further, note that it is well known to those skilled in the semiconductor/ display art that since a control power source is a source for generating a power/voltage and a scanning line is an electrical wiring, it is nonsense to compare a control power source with a scanning line. Instead, a control power source signal line is compared with a scanning line.
Further, as noted in the previous Office action and repeated below, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
In response to the second set of rejections under 35 U.S.C. 103 in the previous Office action, Applicant has amended independent claim 1 and provided on pages 13-17 of the amendment arguments, which have been fully considered but they are not persuasive as follows:
(a) Applicant’s argument, “First, Chai has already disclosed that MS1 is turned on (conducting) during the initialization phase … With reference to Paragraph [0094] of the specification of Chai: the control power source VC is set to a gate-on voltage such that the first stabilization transistor MS1 is turned on when the pixel PXL is driven at a first driving frequency
… With reference to Paragraph [0121] of the specification of Chai: During first and second periods T1 and T2 in which a data signal is supplied to the pixel PXL, the voltage of the control power source VC is set such that the first stabilizing transistor MS1 is turned on. It can also be seen from Fig. 5 of Chai that during T1 and T2, VC is at a high level and MS 1 is in a conducting state … regarded as equivalent” on pages 14-15 of the amendment, not persuasive because (i) Chai discloses two different driving scenarios of the pixel circuit, a first scenario driven with a first frequency and a second scenario driven with a second frequency and while the Office action provides citations of the pixel circuit driven with the first frequency, the Applicant has provided argument(s) with respect to the citations of the pixel circuit driven with the second frequency, such as Fig. 5 and paragraph [0121] indicated by the Applicant. In the instant case, the above paragraph [0094] indicated by the Applicant does not explicitly disclose the first stabilization transistor MS1 turned on from the initialization phase when the pixel PXL is driven at a first driving frequency; however, Chai at paragraph [0114] discloses ““… during the second period T2, the first stabilizing transistor MS1 is set to the turn-on state …,” i.e., the N-type transistor MS1 is not previously turned on in the first period T1 and is set to turn on from and during the second period T2.
(b) Applicant’s argument, “Second, Cho discloses that the compensation transistor TR3 is turned off during the initialization phase P2 and turned on during the data writing phase P3. However, it is not turned on throughout the entire data writing phase P3 … Cho” on page 15 of the amendment, not persuasive because Applicant is attacking references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In the instant case, the feature, “the compensation transistor or the compensation control circuit is turned on throughout the entire data writing phase,” is already taught by Chai and the feature, “the compensation transistor or the compensation control circuit is turned off in the entire initialization phase,” is learned from Cho. As such, the combination of Chai and Cho obviously renders the features, “the compensation transistor or the compensation control circuit is turned on throughout the entire data writing phase and the compensation transistor or the compensation control circuit is turned off in the entire initialization phase,” as required by the current claim 1.
Applicant has amended claim 1 to include the limitations, “a display period of the pixel circuit comprises an initialization phase, a bias compensation phase and a writing-in compensation phase arranged in sequence” and “a reset circuit, wherein the reset circuit is respectively coupled to a third scanning line, a reset voltage line and the second terminal of the driving circuit, is configured to be turned on to connect the reset voltage line and the second terminal of the driving circuit under a control of a third scanning signal provided by the third scanning line,” and provided on pages 16-17 of the amendment an argument that Cho fails to disclose the above underlined limitations of the currently amended claim 1. The argument is not persuasive because Applicant is attacking references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In the instant case, the combination of Chai and Cho obviously renders the above underlined limitations. features, “the compensation transistor or the compensation control circuit is turned on throughout the entire data writing phase and the compensation transistor or the compensation control circuit is turned off in the entire initialization phase,” as required by the current claim 1. See the below detailed rejections for these limitations rendered by the modified Chai in view of Cho.
Claim Objections
Claim 16 is objected to because of the following informalities: “a reset circuit” in line 6 should be changed to -- the reset circuit -- because this limitation is recited in claim 1. Appropriate correction is required.
Notice to Applicant(s)
Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968).
Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
FIRST SET OF REJECTIONS:
Claims 1, 2, 6, 9, 10, 12, 14, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chai et al. (US 2018/0158407 A1; hereinafter Chai) in view of Cho et al. (US 2021/0225282 A1; hereinafter Cho.)
As per claim 1, Chai discloses a pixel circuit (see at least Fig. 3B) comprising: a driving circuit (see at least Fig. 3B, disclosing a driving circuit comprising a transistor M1 and its connections;) a data writing-in circuit (see at least Fig. 3B, disclosing a data writing-in circuit comprising a transistor M2 and its connections;) a compensation control circuit (see at least Fig. 3B, disclosing a compensation control circuit comprising a transistor MS1 and its connections;) and a first control circuit (see at least Fig. 3B, disclosing a first control circuit comprising a transistor M3 and its connections,) wherein:
a display period of the pixel circuit comprises an initialization phase, a bias compensation phase, and a writing-in compensation phase arranged in sequence, wherein the writing-in compensation phase comprises a non-writing-in control phase and a writing-in control phase arranged in sequence (see at least Fig. 4, disclosing a display period of the pixel circuit comprising an initialization phase [T1], a bias compensation phase [a period between a period T1 and a period T2], and a writing-in compensation phase [T2] arranged in sequence; further this application, specifically Fig. 4 and the limitations of this claim, requires “the compensation control circuit [[13/T1]] is respectively coupled to a second scanning line [[S2]], a first terminal of the driving circuit [[11/ T3]] and a connection node [[N0]] and is configured to be, in the entire writing-in compensation phase [[P3]], turned on to connect the first terminal of the driving circuit and the connection node under a control of a second scanning signal provided by the second scanning line” in lines 11-17; and Chai, discussed below or at least Fig. 4 and ¶ 114 “… during the second period T2, the first stabilizing transistor MS1 is set to the turn-on state …”, i.e., the [[compensation]] transistor MS1 is turned on during the second period T2 and is not turned on in the first/initialization period T1, also discloses the same. Therefore, while Chai is silent to the writing-in compensation phase [T2] divided into a non-writing-in control phase and a writing-in control phase arranged in sequence, as presently claimed, one of ordinary skill in the art would have found it obvious to modify/ divide the writing-in compensation phase [T2 of Chai] into a non-writing-in control phase and a writing-in control phase arranged in sequence, to obtain the same teachings [[the above underlined limitations]];)
the data writing-in circuit is respectively coupled to a first scanning line [Sl1], a data line [Dm], and a second terminal of the driving circuit [a second terminal corresponding to a [[first]] electrode of the transistor M1 connected to a node N1; Fig. 3B] (see at least Fig. 3B,) and is configured to, merely in the writing-in control phase, control to connect the data line and the second terminal of the driving circuit under the control of a first scanning signal provided by the first scanning line (see at least Figs. 3B, 4;)
the compensation control circuit is respectively coupled to a second scanning line [VC], a first terminal of the driving circuit [a first terminal corresponding to a [[second]] electrode of the transistor M1 connected to transistors [MS1, M7]; Fig. 3B] and a connection node [a node between two transistors [MS1, M3]; Fig. 3B] (see at least Fig. 3B,) and is configured to be, in the entire writing-in compensation phase, turned on to connect the first terminal of the driving circuit and the connection node under a control of a second scanning signal provided by the second scanning line (see at least Figs. 3B, 4,) and the compensation control circuit is configured to be, in the entire initialization phase, turned off to not connect the first terminal of the driving circuit and the connection node under the control of the second scanning signal provided by the second scanning line (see at least Fig. 4; ¶ 114 disclosing “… during the second period T2, the first stabilizing transistor MS1 is set to the turn-on state …”, i.e., the [[compensation]] transistor MS1 is turned on during the second period T2 and is not turned on in the first/initialization period T1; ¶¶ 109-111 disclosing, during the first/initialization period T1, the initialization transistor M4 required to be turned on to supply the [initialization]] voltage Vint to the second node N2 and not discussing the [[compensation]] transistor MS1; in other words, Chai discloses the compensation transistor MS1 or the compensation control circuit configured to be, in the entire initialization phase T1, turned off to not connect the first terminal of the driving circuit and the connection node under the control of the second scanning signal VC provided by the second scanning line VC;) and
the first control circuit is respectively coupled to the first scanning line, a control terminal of the driving circuit [a control terminal corresponding to a gate electrode of the transistor M1 connected to the elements [N2, M3]; Fig. 3B], and the connection node (see at least Fig. 3B,) and is configured to be, in the writing-in control phase [T2], turned on to connect the control terminal of the driving circuit and the connection node under the control of the first scanning signal (see at least Figs. 3B, 4.)
Accordingly, the above modified Chai obviously renders all limitations of this claim except for a reset circuit, as claimed.
However, in the same field of endeavor, Cho discloses a related pixel circuit (see at least Figs. 2, 12) comprising a reset circuit (see at least Figs. 2, 12, disclosing a reset circuit comprising a transistor TR8 and its connections,) wherein the reset circuit is respectively coupled to a third scanning line [GB[n]], a reset voltage line [VEH] and the second terminal of the driving circuit [the second terminal connected to at least the node N2 and the transistor TR2 of the data writing-in circuit; see at least Figs. 2, 12] is configured to be turned on to connect the reset voltage line [VEH] and the second terminal of the driving circuit under a control of a third scanning signal provided by the third scanning line [GB[n]] (see at least Figs. 2, 12,) thereby at least reducing a stress of the driving transistor [TR1] of the driving circuit (see at least ¶ 82.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the Chai pixel circuit to include a reset circuit, in view of the teaching in the Cho reference, to improve the above modified pixel circuit of the Chai reference for the predictable result of at least reducing a stress of the driving transistor of the driving circuit.
As per claim 2, Chai discloses: wherein the pixel circuit further comprises: a first initialization circuit (see at least Fig. 3B, disclosing a first initialization circuit comprising a transistor M4 and its connections,) the first initialization circuit is respectively coupled to an initialization control line [S2i], a first initialization voltage line [Vint], and the control terminal of the driving circuit (see at least Fig. 3B,) and is configured to be turned on to connect the first initialization voltage line and the control terminal of the driving circuit under the control of an initialization control signal provided by the initialization control line (see at least Fig. 3B.)
As per claim 6, Chai discloses: wherein the pixel circuit further comprises: a light emitting control circuit (see at least Fig. 3B, disclosing a light emitting control circuit comprising transistors [M6, M7] and their connections,) an energy storage circuit (see at least Fig. 3B, disclosing an energy storage circuit comprising a capacitor Cst and its connections,) and a light emitting element (see at least Fig. 3B, disclosing a light emitting element OLED,) wherein:
the light emitting control circuit is respectively coupled to a light emitting control line {Ei], the first terminal of the driving circuit and the light emitting element (see at least Fig. 3B,) and is configured to be turned on to connect the first terminal of the driving circuit and the light emitting element under a control of a light emitting control signal provided by the light emitting control line (see at least Fig. 3B,)
the light emitting control circuit is also coupled to a first voltage line [ELVDD] and the second terminal of the driving circuit (see at least Fig. 3B,) and is configured to be turned on to connect the first voltage line and the second terminal of the driving circuit under the control of the light emitting control signal (see at least Fig. 3B,) and
the energy storage circuit is respectively coupled to the control terminal of the driving circuit and the first voltage line (see at least Fig. 3B.)
As per claim 9, Chai discloses wherein:
the compensation control circuit comprises a first transistor [MS1] (see at least Fig. 3B,)
the driving circuit comprises a third transistor [M1] (see at least Fig. 3B,)
the data writing-in circuit comprises a fourth transistor [M2] (see at least Fig. 3B,)
the first control circuit comprises a ninth transistor [M3] (see at least Fig. 3B,)
a gate electrode of the first transistor [MS1] is coupled to the second scanning line [VC], a first electrode of the first transistor is coupled to a second electrode of the third transistor [M1], and a second electrode of the first transistor is coupled to the connection node (see at least Fig. 3B,)
a gate electrode of the fourth transistor [M2] is coupled to the first scanning line, a first electrode of the fourth transistor is coupled to the data line, and a second electrode of the fourth transistor is coupled to a first electrode of the third transistor (see at least Fig. 3B,) and
a gate electrode of the ninth transistor [M3] is coupled to the first scanning line, a first electrode of the ninth transistor is coupled to the connection node, and a second electrode of the ninth transistor is coupled to a gate electrode of the third transistor (see at least Fig. 3B.)
As per claim 10, Chai further discloses: wherein the first initialization circuit comprises a second transistor [M4], a gate electrode of the second transistor is coupled to the initialization control line [S2i], a first electrode of the second transistor is coupled to the first initialization voltage line [Vint], and a second electrode of the second transistor is coupled to the control terminal of the driving circuit (see Chai at least Fig. 3B.)
As per claim 12, the above modified Chai in view of Cho obviously renders: wherein the reset circuit comprises an eighth transistor (see Cho at least Fig. 12, disclosing the reset circuit comprising an eighth transistor TR8;) a gate electrode of the eighth transistor is coupled to the third scanning line (see Cho at least Fig. 12, disclosing the third scan line GB[n] connected to both a gate electrode of the eighth transistor TR8 and a gate electrode of the [seventh]] transistor TR7 of the [[second]] initialization circuit,) a first electrode of the eighth transistor is coupled to the reset voltage line [VEH] (see Cho at least Fig. 12,) and a second electrode of the eighth transistor is coupled to the second terminal of the driving circuit (see Cho at least Fig. 12.)
As per claim 14, Chai discloses: wherein the light emitting control circuit [M6, M7] comprises a fifth transistor [M6] and a sixth transistor [M7]; a gate electrode of the fifth transistor is coupled to the light emitting control line {Ei], a first electrode of the fifth transistor is coupled to the first voltage line [ELVDD], and a second electrode of the fifth transistor is coupled to the second terminal of the driving circuit; a gate electrode of the sixth transistor is coupled to the light emitting control line, a first electrode of the sixth transistor is coupled to one terminal of the driving circuit, and a second electrode of the sixth transistor is coupled to the light emitting element [OLED].(see at least Fig. 3B.)
As per claim 16, the above modified Chai in view of Cho obviously renders an associated driving method (see at least Figs. 3B, 4), applied to the pixel circuit according to claim 1, wherein in the non-writing-in control phase, the data writing-in circuit being turned off to not connect the data line and the second terminal of the driving circuit under the control of the first scanning signal; the first control circuit controlling to not connect the control terminal of the driving circuit and the connection node under the control of the first scanning signal (see the discussion in the rejection of claim 1 and Figs. 3B, 4;) and in the bias compensation phase, a reset circuit being turned on to connect a reset voltage line and the second terminal of the driving circuit under the control of a third scanning signal (see the Cho reset circuit discussed in the rejection of claim 1; Cho further discloses the associated driving method comprising: in the bias compensation phase, the reset circuit being turned on to connect a reset voltage line [VEH] and the second terminal of the driving circuit [the second terminal connected to at least the node N2 and the transistor TR2 of the data writing-in circuit; see at least Figs. 2, 12] under the control of a third scanning signal [GB[n]] (see at least Figs. 2, 12.).)
As per claim 18, Chai discloses: wherein the driving method (see at least Figs. 3B, 4) further comprises: in the initialization phase [T1], the first initialization circuit [M4] in the pixel circuit controlling to connect the first initialization voltage line [Vint] and the control terminal of the driving circuit under the control of the initialization control signal [S2i] (see at least Fig. 3B.)
In the alternative of claim 18, Chai further discloses: wherein the driving method comprises: in the light emitting phase [T3], a light emitting control circuit [M6, M7] in the pixel circuit (see at least Fig. 3B) being turned on to connect the first voltage line [ELVDD] and the second terminal of the driving circuit under a control of the light emitting control signal [Ei] (see at least Fig. 3B,) and being turned on to connect the first terminal of the driving circuit and the light emitting element [OLED], and the driving circuit driving the light emitting element to emit light (see at least Figs. 3B, 4; ¶ ¶ 117-119.)
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chai in view of Cho as applied to claim 1, and further in view of Gao et al. (US 2018/0130410 A1; hereinafter Gao.)
As per claim 7, the above modified Chai in view of Cho, as discussed in the rejection of claim 4, obviously renders: wherein the pixel circuit further comprises: a second initialization circuit (see Chai at least Fig. 3B, disclosing a second initialization circuit comprising a transistor M5 and its connections; also see at Cho at least Fig. 12, disclosing a second initialization circuit comprising a transistor TR7 and its connections;) and a light emitting element (see Chai at least Fig. 3B, disclosing a light emitting element OLED; also see at Cho at least Fig. 12, disclosing a light emitting element OLED;)
the second initialization circuit is respectively coupled to the third scanning line, a second initialization voltage line and the light emitting element (see Chai at least Fig. 3B, disclosing the second initialization circuit respectively coupled to the third scanning line [S3i], a second initialization voltage line [Vint] and the light emitting element [OLED]; also see Cho at least Fig. 12, disclosing the second initialization circuit respectively coupled to the third scanning line [GB[n]], a second initialization voltage line [Vint2] and the light emitting element [OLED],) and is configured to be turned on to connect the second initialization voltage line and the light emitting element under the control of the third scanning signal provided by the third scanning line (see Chai at least Fig. 3B; also see Cho at least Fig. 12,)
wherein the pixel circuit further comprises a first initialization circuit, the first initialization circuit is coupled to a first initialization voltage line (see Chai at least Fig. 3B, disclosing a first initialization circuit comprising a transistor M4 and its connections and coupled to a first initialization voltage line [Vint]; also see Cho at least Fig. 12, disclosing a first initialization circuit comprising a transistor TR4 and its connections and coupled to a first initialization voltage line [Vint1].)
Accordingly, the above modified Chai in view of Cho obviously renders all limitations of this claim, but is silent to “the first initialization voltage line is reused as the reset voltage line,” as claimed.
However, in the same field of endeavor, Gao discloses a related pixel circuit (see at least Fig. 3) comprising a reset circuit coupled to a reset voltage line (see at least Fig. 3, disclosing a reset circuit coupled to a reset voltage line VREF2;) and a first initialization circuit coupled to a first initialization voltage line (see at least Fig. 3, disclosing a first initialization circuit comprising a transistor T1 and its connections and coupled to a first initialization voltage line VREF1,) wherein the first initialization voltage line is reused as the reset voltage line (see at least ¶ 32, disclosing a potential signal at the line VREF1 being same as a potential signal at the line VREF2, i.e., the first initialization voltage line VREF1 reused as the reset voltage line VREF2,) thereby obviously simplifying the pixel circuit and the display device because there is no need a separate power circuit for generating the potential VREF1/ VREF2.
Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the Chai pixel circuit to have the first initialization voltage line reused as the reset voltage line, in view of the teaching in the Gao reference, to improve the above modified pixel circuit of the Chai reference for the predictable result of at least simplifying the pixel circuit and the display device.
As per claim 15, the above modified Chai obviously renders: wherein the second initialization circuit comprises a seventh transistor, a gate electrode of the seventh transistor is coupled to the third scanning line, a first electrode of the seventh transistor is coupled to the second initialization voltage line, and a second electrode of the seventh transistor is coupled to the light emitting element (see Chai at least Fig. 3B, disclosing the second initialization circuit comprising a seventh transistor [M5], a gate electrode of the seventh transistor coupled to the third scanning line [S3i], a first electrode of the seventh transistor coupled to the second initialization voltage line [Vint], and a second electrode of the seventh transistor coupled to the light emitting element [OLED]; also see Cho at least Fig. 12, similarly disclosing the second initialization circuit comprising a seventh transistor [TR7], a gate electrode of the seventh transistor coupled to the third scanning line [GB[n]], a first electrode of the seventh transistor coupled to the second initialization voltage line [Vint2], and a second electrode of the seventh transistor coupled to the light emitting element [OLED].)
SECOND/ ALTERNATIVE SET OF REJECTIONS:
Claims 1, 2, 6, 9, 10, 12, 14, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Chai in view of Cho.
As per claim 1, Chai discloses a pixel circuit (see at least Fig. 3B) comprising: a driving circuit (see at least Fig. 3B, disclosing a driving circuit comprising a transistor M1 and its connections;) a data writing-in circuit (see at least Fig. 3B, disclosing a data writing-in circuit comprising a transistor M2 and its connections;) a compensation control circuit (see at least Fig. 3B, disclosing a compensation control circuit comprising a transistor MS1 and its connections;) and a first control circuit (see at least Fig. 3B, disclosing a first control circuit comprising a transistor M3 and its connections,) wherein:
a display period of the pixel circuit comprises an initialization phase, a bias compensation phase, and a writing-in compensation phase arranged in sequence, wherein the writing-in compensation phase comprises a non-writing-in control phase and a writing-in control phase arranged in sequence (see at least Fig. 4, disclosing a display period of the pixel circuit comprising an initialization phase [T1], a bias compensation phase [a period between a period T1 and a period T2], and a writing-in compensation phase [T2] arranged in sequence; further this application, specifically Fig. 4 and the limitations of this claim, requires “the compensation control circuit [[13/T1]] is respectively coupled to a second scanning line [[S2]], a first terminal of the driving circuit [[11/ T3]] and a connection node [[N0]] and is configured to be, in the entire writing-in compensation phase [[P3]], turned on to connect the first terminal of the driving circuit and the connection node under a control of a second scanning signal provided by the second scanning line” in lines 11-17; and Chai, discussed below or at least Fig. 4 and ¶ 114 “… during the second period T2, the first stabilizing transistor MS1 is set to the turn-on state …”, i.e., the [[compensation]] transistor MS1 is turned on during the second period T2 and is not turned on in the first/initialization period T1, also discloses the same. Therefore, while Chai is silent to the writing-in compensation phase [T2] divided into a non-writing-in control phase and a writing-in control phase arranged in sequence, as presently claimed, one of ordinary skill in the art would have found it obvious to modify/ divide the writing-in compensation phase [T2 of Chai] into a non-writing-in control phase and a writing-in control phase arranged in sequence, to obtain the same teachings [[the above underlined limitations]];)
the data writing-in circuit is respectively coupled to a first scanning line [Sl1], a data line [Dm], and a second terminal of the driving circuit [a second terminal corresponding to a [[first]] electrode of the transistor M1 connected to a node N1; Fig. 3B] (see at least Fig. 3B,) and is configured to, merely in the writing-in control phase, control to connect the data line and the second terminal of the driving circuit under the control of a first scanning signal provided by the first scanning line (see at least Figs. 3B, 4;)
the compensation control circuit is respectively coupled to a second scanning line [VC], a first terminal of the driving circuit [a first terminal corresponding to a [[second]] electrode of the transistor M1 connected to transistors [MS1, M7]; Fig. 3B] and a connection node [a node between two transistors [MS1, M3]; Fig. 3B] (see at least Fig. 3B,) and is configured to be, in the entire writing-in compensation phase, turned on to connect the first terminal of the driving circuit and the connection node under a control of a second scanning signal provided by the second scanning line (see at least Figs. 3B, 4; ¶ 114 disclosing “… during the second period T2, the first stabilizing transistor MS1 is set to the turn-on state …”, i.e., the [[compensation]] transistor MS1 is turned on during the second period T2 and is not turned on in the first/initialization period T1;) and
the first control circuit is respectively coupled to the first scanning line, a control terminal of the driving circuit [a control terminal corresponding to a gate electrode of the transistor M1 connected to the elements [N2, M3]; Fig. 3B], and the connection node (see at least Fig. 3B,) and is configured to be, in the writing-in control phase [T2], turned on to connect the control terminal of the driving circuit and the connection node under the control of the first scanning signal (see at least Figs. 3B, 4.)
Regarding to the limitations, “the compensation control circuit is configured to be, in the entire initialization phase, turned off to not connect the first terminal of the driving circuit and the connection node under the control of the second scanning signal provided by the second scanning line,” Chai discloses:
(i) at ¶ 114 “… during the second period T2, the first stabilizing transistor MS1 is set to the turn-on state …”, i.e., the [[compensation]] transistor MS1 or the compensation control circuit as a whole is set to be turned on during the second period T2;
(ii) at ¶¶ 109-111, during the first/initialization period T1, the initialization transistor M4 required to be turned on to supply the [initialization]] voltage Vint to the second node N2, but does not discuss the [[compensation]] transistor MS1 or the compensation control circuit as a whole, during the first/initialization period T1; and
(iii) at Fig. 3B, the compensation transistor MS1 or compensation control circuit as a whole is configured to be turned off to not connect the first terminal of the driving circuit and the connection node N0 under the control of the second scanning signal [VC] provided by the second scanning line [VC].
In other words, Chai discloses all limitations of this claim except that Chai is silent to the compensation transistor MS1 or compensation control circuit as a whole is configured to be turned off in the entire initialization phase, as claimed.
However, in the same field of endeavor, Cho discloses a related pixel circuit (see at least Figs. 2, 12) comprising a driving circuit (see at least Figs. 2, 12, disclosing a driving circuit comprising a transistor TR1 and its connections;) and a compensation control circuit (see at least Figs. 2, 12, disclosing a compensation control circuit comprising a transistor TR3 and its connections,) wherein a display period of the pixel circuit comprises an initialization phase [P2/ P2, P1] and a writing-in compensation phase [P3], and the writing-in compensation phase [P3] comprises a writing-in control phase [a period when the signal GC[n] is high during P3; see Fig. 3] and a non-writing-in control phase [a period when the signal GC[n] is low during P3; see Fig. 3] and the compensation control circuit is configured to be, in the entire initialization phase, turned off under the control of the second scanning signal provided by the second scanning line (see at least Figs. 2/12 and 3, disclosing the compensation transistor TR3 or the compensation control circuit as a whole configured to be, in the entire initialization phase [P2/ P2, P1], turned off under the control of the second scanning signal GC[n] provided by the second scanning line GC[n],) thereby at least initializing the gate voltage of the driving transistor [TR1] with a low level voltage (see at least ¶ 84,) and thus reducing a stress of the driving transistor of the driving circuit (see at least ¶ 82.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the Chai pixel circuit to turn off the compensation control circuit in the entire initialization phase, in view of the teaching in the Cho reference, to improve the above modified pixel circuit of the Chai reference for the predictable result of initializing the gate voltage of the driving transistor with a low level voltage and thus reducing a stress of the driving transistor of the driving circuit.
Regarding to the claimed reset circuit in last 4 lines of claim 1, Cho further discloses a related pixel circuit (see at least Figs. 2, 12) comprising a reset circuit (see at least Figs. 2, 12, disclosing a reset circuit comprising a transistor TR8 and its connections,) wherein the reset circuit is respectively coupled to a third scanning line [GB[n]], a reset voltage line [VEH] and the second terminal of the driving circuit [the second terminal connected to at least the node N2 and the transistor TR2 of the data writing-in circuit; see at least Figs. 2, 12] is configured to be turned on to connect the reset voltage line [VEH] and the second terminal of the driving circuit under a control of a third scanning signal provided by the third scanning line [GB[n]] (see at least Figs. 2, 12,) thereby at least reducing a stress of the driving transistor [TR1] of the driving circuit (see at least ¶ 82.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the Chai pixel circuit to include a reset circuit, in view of the teaching in the Cho reference, to improve the above modified pixel circuit of the Chai reference for the predictable result of at least reducing a stress of the driving transistor of the driving circuit. Accordingly, the above modified Chai in view of Cho obviously renders all limitations of this claim.
As per claim 2, Chai discloses: wherein the pixel circuit further comprises: a first initialization circuit (see at least Fig. 3B, disclosing a first initialization circuit comprising a transistor M4 and its connections,) the first initialization circuit is respectively coupled to an initialization control line [S2i], a first initialization voltage line [Vint], and the control terminal of the driving circuit (see at least Fig. 3B,) and is configured to be turned on to connect the first initialization voltage line and the control terminal of the driving circuit under the control of an initialization control signal provided by the initialization control line (see at least Fig. 3B.)
As per claim 6, Chai discloses: wherein the pixel circuit further comprises: a light emitting control circuit (see at least Fig. 3B, disclosing a light emitting control circuit comprising transistors [M6, M7] and their connections,) an energy storage circuit (see at least Fig. 3B, disclosing an energy storage circuit comprising a capacitor Cst and its connections,) and a light emitting element (see at least Fig. 3B, disclosing a light emitting element OLED,) wherein:
the light emitting control circuit is respectively coupled to a light emitting control line {Ei], the first terminal of the driving circuit and the light emitting element (see at least Fig. 3B,) and is configured to be turned on to connect the first terminal of the driving circuit and the light emitting element under a control of a light emitting control signal provided by the light emitting control line (see at least Fig. 3B,)
the light emitting control circuit is also coupled to a first voltage line [ELVDD] and the second terminal of the driving circuit (see at least Fig. 3B,) and is configured to be turned on to connect the first voltage line and the second terminal of the driving circuit under the control of the light emitting control signal (see at least Fig. 3B,) and
the energy storage circuit is respectively coupled to the control terminal of the driving circuit and the first voltage line (see at least Fig. 3B.)
As per claim 9, Chai discloses wherein:
the compensation control circuit comprises a first transistor [MS1] (see at least Fig. 3B,)
the driving circuit comprises a third transistor [M1] (see at least Fig. 3B,)
the data writing-in circuit comprises a fourth transistor [M2] (see at least Fig. 3B,)
the first control circuit comprises a ninth transistor [M3] (see at least Fig. 3B,)
a gate electrode of the first transistor [MS1] is coupled to the second scanning line [VC], a first electrode of the first transistor is coupled to a second electrode of the third transistor [M1], and a second electrode of the first transistor is coupled to the connection node (see at least Fig. 3B,)
a gate electrode of the fourth transistor [M2] is coupled to the first scanning line, a first electrode of the fourth transistor is coupled to the data line, and a second electrode of the fourth transistor is coupled to a first electrode of the third transistor (see at least Fig. 3B,) and
a gate electrode of the ninth transistor [M3] is coupled to the first scanning line, a first electrode of the ninth transistor is coupled to the connection node, and a second electrode of the ninth transistor is coupled to a gate electrode of the third transistor (see at least Fig. 3B.)
As per claim 10, Chai discloses: wherein the first initialization circuit comprises a second transistor [M4], a gate electrode of the second transistor is coupled to the initialization control line [S2i], a first electrode of the second transistor is coupled to the first initialization voltage line [Vint], and a second electrode of the second transistor is coupled to the control terminal of the driving circuit (see at least Fig. 3B.)
As per claim 12, the above modified Chai in view of Cho obviously renders: wherein the reset circuit comprises an eighth transistor (see Cho at least Fig. 12, disclosing the reset circuit comprising an eighth transistor TR8;) a gate electrode of the eighth transistor is coupled to the third scanning line (see Cho at least Fig. 12, disclosing the third scan line GB[n] connected to both a gate electrode of the eighth transistor TR8 and a gate electrode of the [seventh]] transistor TR7 of the [[second]] initialization circuit,) a first electrode of the eighth transistor is coupled to the reset voltage line [VEH] (see Cho at least Fig. 12,) and a second electrode of the eighth transistor is coupled to the second terminal of the driving circuit (see Cho at least Fig. 12.)
As per claim 14, Chai discloses: wherein the light emitting control circuit [M6, M7] comprises a fifth transistor [M6] and a sixth transistor [M7]; a gate electrode of the fifth transistor is coupled to the light emitting control line {Ei], a first electrode of the fifth transistor is coupled to the first voltage line [ELVDD], and a second electrode of the fifth transistor is coupled to the second terminal of the driving circuit; a gate electrode of the sixth transistor is coupled to the light emitting control line, a first electrode of the sixth transistor is coupled to one terminal of the driving circuit, and a second electrode of the sixth transistor is coupled to the light emitting element [OLED].(see at least Fig. 3B.)
As per claim 16, the above modified Chai in view of Cho obviously renders an associated driving method (see at least Figs. 3B, 4), applied to the pixel circuit according to claim 1, wherein in the non-writing-in control phase, the data writing-in circuit being turned off to not connect the data line and the second terminal of the driving circuit under the control of the first scanning signal; the first control circuit controlling to not connect the control terminal of the driving circuit and the connection node under the control of the first scanning signal (see the discussion in the rejection of claim 1 and Figs. 3B, 4;) and in the bias compensation phase, a reset circuit being turned on to connect a reset voltage line and the second terminal of the driving circuit under the control of a third scanning signal (see the Cho reset circuit discussed in the rejection of claim 1; Cho further discloses the associated driving method comprising: in the bias compensation phase, the reset circuit being turned on to connect a reset voltage line [VEH] and the second terminal of the driving circuit [the second terminal connected to at least the node N2 and the transistor TR2 of the data writing-in circuit; see at least Figs. 2, 12] under the control of a third scanning signal [GB[n]] (see at least Figs. 2, 12.).)
As per claim 18, Chai discloses: wherein the driving method (see at least Figs. 3B, 4) further comprises: in the initialization phase [T1], the first initialization circuit [M4] in the pixel circuit controlling to connect the first initialization voltage line [Vint] and the control terminal of the driving circuit under the control of the initialization control signal [S2i] (see at least Fig. 3B.)
In the alternative of claim 18, Chai further discloses: wherein the driving method comprises: in the light emitting phase [T3], a light emitting control circuit [M6, M7] in the pixel circuit (see at least Fig. 3B) being turned on to connect the first voltage line [ELVDD] and the second terminal of the driving circuit under a control of the light emitting control signal [Ei] (see at least Fig. 3B,) and being turned on to connect the first terminal of the driving circuit and the light emitting element [OLED], and the driving circuit driving the light emitting element to emit light (see at least Figs. 3B, 4; ¶ ¶ 117-119.)
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Chai in view of Cho as applied to claim 1, and further in view of Gao et al. (US 2018/0130410 A1; hereinafter Gao.)
As per claim 7, the above modified Chai in view of Cho, as discussed in the rejection of claim 4, obviously renders: wherein the pixel circuit further comprises: a second initialization circuit (see Chai at least Fig. 3B, disclosing a second initialization circuit comprising a transistor M5 and its connections; also see at Cho at least Fig. 12, disclosing a second initialization circuit comprising a transistor TR7 and its connections;) and a light emitting element (see Chai at least Fig. 3B, disclosing a light emitting element OLED; also see at Cho at least Fig. 12, disclosing a light emitting element OLED;)
the second initialization circuit is respectively coupled to the third scanning line, a second initialization voltage line and the light emitting element (see Chai at least Fig. 3B, disclosing the second initialization circuit respectively coupled to the third scanning line [S3i], a second initialization voltage line [Vint] and the light emitting element [OLED]; also see Cho at least Fig. 12, disclosing the second initialization circuit respectively coupled to the third scanning line [GB[n]], a second initialization voltage line [Vint2] and the light emitting element [OLED],) and is configured to be turned on to connect the second initialization voltage line and the light emitting element under the control of the third scanning signal provided by the third scanning line (see Chai at least Fig. 3B; also see Cho at least Fig. 12,)
wherein the pixel circuit further comprises a first initialization circuit, the first initialization circuit is coupled to a first initialization voltage line (see Chai at least Fig. 3B, disclosing a first initialization circuit comprising a transistor M4 and its connections and coupled to a first initialization voltage line [Vint]; also see Cho at least Fig. 12, disclosing a first initialization circuit comprising a transistor TR4 and its connections and coupled to a first initialization voltage line [Vint1].)
Accordingly, the above modified Chai in view of Cho obviously renders all limitations of this claim, but is silent to “the first initialization voltage line is reused as the reset voltage line,” as claimed.
However, in the same field of endeavor, Gao discloses a related pixel circuit (see at least Fig. 3) comprising a reset circuit coupled to a reset voltage line (see at least Fig. 3, disclosing a reset circuit coupled to a reset voltage line VREF2;) and a first initialization circuit coupled to a first initialization voltage line (see at least Fig. 3, disclosing a first initialization circuit comprising a transistor T1 and its connections and coupled to a first initialization voltage line VREF1,) wherein the first initialization voltage line is reused as the reset voltage line (see at least ¶ 32, disclosing a potential signal at the line VREF1 being same as a potential signal at the line VREF2, i.e., the first initialization voltage line VREF1 reused as the reset voltage line VREF2,) thereby obviously simplifying the pixel circuit and the display device because there is no need a separate power circuit for generating the potential VREF1/ VREF2.
Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the Chai pixel circuit to have the first initialization voltage line reused as the reset voltage line, in view of the teaching in the Gao reference, to improve the above modified pixel circuit of the Chai reference for the predictable result of at least simplifying the pixel circuit and the display device.
As per claim 15, the above modified Chai obviously renders: wherein the second initialization circuit comprises a seventh transistor, a gate electrode of the seventh transistor is coupled to the third scanning line, a first electrode of the seventh transistor is coupled to the second initialization voltage line, and a second electrode of the seventh transistor is coupled to the light emitting element (see Chai at least Fig. 3B, disclosing the second initialization circuit comprising a seventh transistor [M5], a gate electrode of the seventh transistor coupled to the third scanning line [S3i], a first electrode of the seventh transistor coupled to the second initialization voltage line [Vint], and a second electrode of the seventh transistor coupled to the light emitting element [OLED]; also see Cho at least Fig. 12, similarly disclosing the second initialization circuit comprising a seventh transistor [TR7], a gate electrode of the seventh transistor coupled to the third scanning line [GB[n]], a first electrode of the seventh transistor coupled to the second initialization voltage line [Vint2], and a second electrode of the seventh transistor coupled to the light emitting element [OLED].)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Jimmy H Nguyen/
Primary Examiner, Art Unit 2626
Prosecution Insights