DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 16 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Ono et al (Fig. 5); 6,876,270].
Regarding claim 1, Ono et al discloses an amplifier circuit comprising an input terminal (81) which receives a high frequency signal (RF IN) from an outside, an MMIC (1, C51, 17, Tr1) which receives the high frequency signal (RF IN) via the input terminal (81) and amplifies the high frequency signal (RF IN), input matching circuit (2, C54, 18), a transistor (Tr2) which receives via the input matching circuit (2, C54, 18) and wherein the high frequency signal (RF IN) amplified by the MMIC (1, C51, 17, Tr1) and amplifies the high frequency signal (RF IN), output matching circuit (19, C57, 20), an output terminal (86) which receives a drain voltage (the voltage applying to the upper terminal of the element 96) of the transistor (Tr2) from the outside receives via the output matching circuit (19, C57, 20) and the high frequency signal (RF IN) amplified by the transistor (Tr2) and outputs the high frequency signal (RF IN) to the outside, and a drain bias circuit board (Vd1, 84, C53, 93, Vd2, 85, C56, 95) which connects a drain (drain of Tr2) of the transistor (Tr2) and a drain (drain of Tr1) of the MMIC (1, C51, 17, Tr1). It should be noted that the limitation of “the transistor and the MMIC are conjugately matched at impedance smaller than 50 ohm” is intended use of the invention.
Regarding claim 2, wherein a gate voltage (Vg1) of the MMIC (1, C51, 17, Tr1) is input to the input terminal (82) from the outside.
Regarding claim 3, wherein the power amplifier (Fig. 5) includes only the input terminal (81) and the output terminal (86) as terminals.
Regarding claim 4, wherein the drain bias circuit board (Vd1, 84, C53, 93, Vd2, 85, C56, 95) and a chock inductor (inductor in 93, inductor in 95) is provided on a line connecting the drain (drain terminal of 95) of the transistor (Tr2) and the drain (drain terminal of 93) of the MMIC (1, C51, 17, Tr1).
Regarding claim 5, wherein a path connecting the drain (drain terminal of Tr2) of the transistor (Tr2) and the drain (drain terminal of Tr1) of the MMIC (1, C51, 17, Tr1) via the drain bias circuit board (Vd1, 84, C53, 93, Vd2, 85, C56, 95) is connected to a terminal for grounding by a first capacitor (C53, C56).
Regarding claim 16, the limitation recited in claim 16 is intended use of the invention.
Regarding claim 17, Ono et al further comprising a drain bias supply point (85) for supplying the drain voltage (Vd2) to the output terminal (86) wherein a path connecting the drain (drain terminal of Tr2) of the transistor (Tr2) and the drain (drain terminal of Tr1) of the MMIC (1, C51, 17, Tr1) via the drain bias circuit board (Vd1, 84, C53, 93, Vd2, 85, C56, 95) is connected to a terminal for ground by a first capacitor (C53), and a path connecting the drain bias supply point (85) and the output terminal (86) is connected to the terminal for grounding by a second capacitor (C56).
Allowable Subject Matter
Claims 6-15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HENRY CHOE/ Primary Examiner, Art Unit 2843
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