DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, and 8 are rejected under 35 U.S.C. § 103 as being unpatentable over Nagafuji et al. (US20090225791A1) in view of Ikeda et al. (US20110200146A1).
Regarding claim 1, Nagafuji teaches A receiving device comprising:
a memory that holds past signal data; a hint information extraction circuit that extracts hint information from newly received signal data; and a reception processing circuit that reads the past signal data held in the memory based on the hint information to perform predetermined reception processing. (Nagafuji [0057]– [0063], Fig. 6) Nagafuji teaches a receiving device that includes a memory for temporarily storing received signal data, and a reception processing circuit configured to apply FEC decoding based on control information parsed from newly received packets. Nagafuji further discloses extracting timing and control fields (e.g., PCR, RTP, or FEC triggers) from incoming headers to determine when and how to reprocess the stored signal data, effectively guiding reception behavior using information from new signals.
However, Nagafuji does not explicitly teach using a “hint information extraction circuit” to extract “hint information” as a trigger. (Ikeda [0112]– [0120], Fig. 6) Ikeda teaches extracting specific flag patterns (bits 2–4, 2–17) from incoming signals to generate a control signal (the “early detection flag”) that determines whether to perform further processing.
One of ordinary skill in the art would have combined Ikeda’s explicit flag-based parsing mechanism with Nagafuji’s buffered reception system to enable selective processing of stored signal data based on extracted hint information. Such a combination represents a predictable use of known header field extraction to trigger reception processing, resulting in improved resource efficiency and reduced unnecessary decoding.
Regarding claim 2, Nagafuji teaches the receiving device according to claim 1,
wherein the reception processing circuit performs error correction processing as the predetermined reception processing, the memory holds data in the middle of the error correction processing as the past signal data, and the hint information extraction circuit extracts, as the hint information, information indicating whether transmission has been performed at a timing of the past signal data, and if the transmission has been performed at the timing of the past signal data, the hint information extraction circuit causes the reception processing circuit to continue the error correction processing. (Nagafuji [0057]– [0065], [0071]– [0076], Figs. 6–8) Nagafuji teaches that received signal data is temporarily stored in memory to enable forward error correction (FEC) decoding, and that such processing can occur in stages using buffered data along with updated header or timestamp fields from newly received packets. The device maintains partial decoding results (i.e., in the middle of error correction processing) and resumes or continues FEC when new packets indicate proper alignment or redundancy, such as based on RTP or PCR information.
However, Nagafuji does not explicitly teach using extracted “hint information” to determine whether transmission was performed at the earlier time and trigger continued decoding.(Ikeda [0112]– [0120], Fig. 6) Ikeda teaches extracting specific patterns or flags (e.g., early detection flags) from incoming bits to signal whether data is valid, aligned, or redundant, which in turn controls whether additional decoding or data processing occurs.
One of ordinary skill in the art would have combined Ikeda’s flag-based control logic with Nagafuji’s buffered error correction framework to enable continuation of decoding based on extracted indications of prior transmission activity. This would represent a predictable use of known header flag analysis to optimize staged FEC decoding, reduce redundant processing, and improve throughput efficiency.
Regarding claim 8, Nagafuji teaches the receiving device according to claim 1,
wherein the hint information extraction circuit further extracts information indicating whether the hint information is enabled or not, and if the information indicating whether the hint information is enabled or not indicates that the hint information is enabled, extracts the hint information. (Nagafuji [0057]– [0065], [0071], Fig. 6) Nagafuji teaches that a receiving device extracts control information from newly received packets and uses that to perform reception processing, including reading previously stored signal data. Fields such as RTP timestamps or PCR values act as implicit control signals that trigger decoding of buffered data.
However, Nagafuji does not explicitly teach extracting an additional flag or control field that determines whether hint information is enabled or should be extracted. (Ikeda [0112]– [0120], Fig. 6) Ikeda teaches a bitstream parsing system where specific bit patterns (e.g., “early detection flags”) are extracted to determine whether further decoding should proceed. If the flag is not set or indicates “disable,” the receiver does not extract or use the remaining information.
One of ordinary skill in the art would have combined Ikeda’s enable/disable logic with Nagafuji’s hint-based reception system to allow conditional extraction of hint information based on system status or flag evaluation. This would be a predictable design choice to reduce unnecessary signal processing and to implement adaptive power-saving or load-balancing features in modern communication systems
Claim 3 is rejected under 35 U.S.C. § 103 as being unpatentable over Nagafuji et al. (US20090225791A1) in view of Ishii et al. (US20180288810A1).
Regarding claim 3, Nagafuji teaches the receiving device according to claim 1,
wherein the hint information extraction circuit extracts information on backoff of the past signal data as the hint information and causes the reception processing circuit to perform the predetermined reception processing on signal data at a timing according to the information on the backoff. (Nagafuji [0057]– [0065], [0071]– [0076], Figs. 6–8) Nagafuji discloses that control information such as RTP timestamps, sequence numbers, and header fields is extracted from newly received packets and used to schedule reception processing (e.g., FEC decoding) on buffered signal data. This enables the receiver to selectively process past data when aligned timing indicators are present.However, Nagafuji does not explicitly teach extracting backoff-related information—such as contention-based delays or retransmission deferrals—as hint information. (Ishii [0073]– [0079], [0083]– [0087], Fig. 7) Ishii teaches a “Backoff Indicator” field in the packet header that indicates whether backoff has occurred in transmission timing. The receiver extracts this information and uses it to adjust reception processing timing, ensuring data is processed with awareness of deferred transmission conditions.
One of ordinary skill in the art would have combined Ishii’s Backoff Indicator-based timing control with Nagafuji’s buffered signal decoding to enable reception decisions that respect prior backoff conditions. This represents a predictable enhancement that improves timing accuracy, reduces misaligned decoding, and conserves resources by avoiding unnecessary processing during contention windows.
Claims 4-5 are rejected under 35 U.S.C. § 103 as being unpatentable over Nagafuji et al. (US20090225791A1).
Regarding claim 4, Nagafuji teaches the receiving device according to claim 1,
wherein the hint information extraction circuit extracts information on an amount of deviation in time domain of the past signal data as the hint information and causes the reception processing circuit to perform the predetermined reception processing on signal data at a timing according to the information on the amount of deviation in time domain. (Nagafuji [0057]– [0063], [0071]– [0076], Figs. 6–8) Nagafuji teaches that control fields such as Program Clock Reference (PCR) and RTP timestamps are extracted from incoming packets and used to calculate time alignment or deviation of previously buffered signal data. This time-deviation information allows the reception processing circuit to determine whether stored signal data is still valid or needs to be processed at a delayed timing to ensure proper synchronization, especially for FEC.
Thus, Nagafuji clearly supports using time-domain deviation information as hint information to trigger or schedule reception processing on previously received data.
One of ordinary skill in the art would have found it obvious to use the time deviation information (e.g., from PCR and RTP timestamps) disclosed in Nagafuji as "hint information" to schedule decoding of stored signal data, since Nagafuji already uses this timing information to align and validate buffered data. Treating such timing deviation as a processing trigger is a predictable optimization of an existing decoding technique to improve synchronization accuracy.
Regarding claim 5, Nagafuji teaches the receiving device according to claim 1,
wherein the hint information extraction circuit extracts information on a sequence number of the past signal data as the hint information and causes the reception processing circuit to perform the predetermined reception processing on signal data of a timing according to the information on the sequence number. (Nagafuji [0059]– [0063], [0071], Fig. 6) Nagafuji discloses that the receiving device extracts sequence numbers from incoming packets, such as RTP headers, and uses those values to determine the position and timing of stored past signal data in memory. The processing circuit then aligns decoding and error correction operations (e.g., FEC) based on whether earlier sequence numbers are missing, misaligned, or now recoverable using the newly received data.
Thus, the sequence number functions as hint information to trigger or adjust the timing of predetermined reception processing on previously received signal data.
One of ordinary skill in the art would have found it obvious to use the extracted sequence number from incoming packets as "hint information" to determine which past data to reprocess, because Nagafuji already uses sequence numbers to organize buffered data and detect gaps or errors. Recasting this known use as a triggering mechanism for reception processing represents a routine application of known techniques for improving error recovery and decoding precision.
Claim 6-7 is rejected under 35 U.S.C. § 103 as being unpatentable over Nagafuji et al. (US20090225791A1) in view of Park et al. (US20210306864A1).
Regarding claim 6, Nagafuji teaches the receiving device according to claim 1,
wherein the hint information extraction circuit extracts, as the hint information, information on a moving speed of a transmitting device that has transmitted the past signal data and causes the reception processing circuit to perform the predetermined reception processing according to the information on the moving speed. (Nagafuji [0057]– [0063], [0071], Fig. 6) Nagafuji discloses a receiver that performs predetermined reception processing (e.g., FEC) on buffered signal data based on header information or time synchronization fields extracted from newly received data. These fields guide timing and alignment, allowing for selective reprocessing of past signal data.
However, Nagafuji does not explicitly teach extracting moving speed information of the transmitting device to guide the timing of reception processing. (Park [0045]– [0055], Fig. 4–5) Park teaches determining the relative speed of a transmitting device based on frequency shifts (e.g., Doppler shift) and using this mobility information to adjust timing and synchronization during reception, improving processing accuracy in high-speed scenarios.
One of ordinary skill in the art would have combined Park’s mobility-aware signal analysis with Nagafuji’s buffered processing architecture to enhance the timing accuracy of decoding or correction steps, especially in dynamic environments. This represents a predictable improvement using known motion-based adaptation techniques to compensate for Doppler effects and ensure reliable decoding.
Regarding claim 7, Nagafuji teaches the receiving device according to claim 1,
wherein the hint information extraction circuit extracts, as the hint information, information on part of a payload of the past signal data and causes the reception processing circuit to perform the predetermined reception processing using the information on the part of the payload as known data. (Nagafuji [0057]– [0065], [0071]– [0076], Fig. 6) Nagafuji teaches a receiver that uses control information (e.g., RTP timestamps or PCR fields) extracted from newly received packets to perform decoding (e.g., FEC) on stored signal data. These parsed headers guide how and when the stored data is processed, particularly to maintain timing alignment and error correction accuracy.
However, Nagafuji does not explicitly teach treating a portion of the payload itself as known data for use during reception processing. (Park [0045]– [0055], Fig. 4–5) Park teaches embedding demodulation reference signals (DMRS) and pilot sequences directly within the data payload. These known sequences are extracted and used by the receiver to assist with channel estimation, synchronization, and error correction — effectively treating part of the payload as known information during processing.
One of ordinary skill in the art would have combined Park’s payload-embedded known signal structures with Nagafuji’s memory-buffered processing approach to enhance decoding of stored data by leveraging known reference segments. This represents a predictable use of embedded known sequences to improve signal integrity and reception efficiency in systems involving deferred or buffered decoding.
Claim 9-10 is rejected under 35 U.S.C. § 103 as being unpatentable over Nagafuji et al. (US20090225791A1) in view of Mendes Alves da Costa et al. (US20140226677A1).
Regarding claim 9, Nagafuji teaches A communication system comprising:
a transmitting device; a plurality of receiving devices each including a memory that holds past signal data having been transmitted from the transmitting device, a hint information extraction circuit that extracts hint information from newly received signal data, and a reception processing circuit that reads the past signal data held in the memory based on the hint information to perform predetermined reception processing; and a server that acquires the hint information from any one of the plurality of receiving devices and supplies the hint information to another one of the plurality of the receiving devices. (Nagafuji [0056]– [0065], [0071]– [0076], Fig. 6–8) Nagafuji teaches a communication system with a transmitting device and multiple receiving devices, each having a memory for storing past signal data and circuits for extracting control information from newly received signals to guide reception processing. Each receiving device determines when and how to decode stored data based on parsed header fields such as RTP or PCR.
However, Nagafuji does not explicitly teach a server that acquires hint information from one receiver and provides it to another. (Mendes Alves da Costa [0030]– [0040], [0060]– [0066], Figs. 1 & 2) Mendes Alves da Costa teaches a centralized server that receives feedback or state information from one receiver (e.g., decoding status, channel conditions, or timing indicators) and uses that information to adjust or assist transmission or processing for other receivers in a coordinated fashion. This includes relaying decoding-related information from one node to others.
One of ordinary skill in the art would have combined Mendes Alves da Costa’s server-based feedback distribution mechanism with Nagafuji’s multi-receiver architecture to facilitate cross-device optimization of reception processing. This would be a predictable extension to enhance decoding success rates, reduce redundancy, and synchronize receivers by leveraging shared hint information in a networked environment.
Regarding claim 10, Nagafuji teaches A communication system comprising:
a transmitting device; a plurality of receiving devices each including a hint information extraction circuit that extracts hint information from newly received signal data; and server including a memory that holds past signal data having been received from the receiving device, and a reception processing circuit that acquires the hint information from any one of the plurality of receiving devices and reads the past signal data held in the memory based on the hint information to perform predetermined reception processing. (Nagafuji [0056]– [0065], [0071]– [0076], Figs. 6–8)Nagafuji teaches a communication system in which signal data is received and temporarily stored in memory, and reception processing is performed using control information—such as RTP timestamps, PCR fields, or FEC headers—extracted from subsequently received packets. While Nagafuji focuses on local processing at the receiving devices, it describes a modular architecture in which functional components could be extended beyond individual devices.
However, Nagafuji does not explicitly teach a centralized server that both stores received signal data and performs the reception processing using hint information acquired from other receivers. (Mendes Alves da Costa [0030]– [0042], [0060]– [0066], Figs. 1–2) Mendes Alves da Costa teaches a communication system that includes a central server which receives hint-like feedback from receivers—such as decoding status, timing offset, or channel conditions—and uses this feedback to process, decode, or redistribute signal data. In certain configurations, Mendes Alves da Costa’s server includes both a memory that stores incoming data and a processing circuit that performs signal-level operations based on the received hints.
One of ordinary skill in the art would have combined Mendes Alves da Costa’s centralized, feedback-driven server architecture with Nagafuji’s hint-guided reception model to implement a system in which the server acquires hint information from distributed receivers and performs the corresponding processing centrally. This integration would be a predictable system-level optimization that supports scalable processing, enables multi-device coordination, and reduces the computational burden on individual receiving devices.
Conclusion
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/ANNABELLA CHRISTOPHE/ Examiner, Art Unit 2415
/JEFFREY M RUTKOWSKI/Supervisory Patent Examiner, Art Unit 2415