Prosecution Insights
Last updated: May 29, 2026
Application No. 18/549,307

COOLED SYSTEM-ON-WAFER WITH MEANS FOR REDUCING THE EFFECTS OF ELECTROSTATIC DISCHARGE AND/OR ELECTROMAGNETIC INTERFERENCE

Non-Final OA §103
Filed
Sep 06, 2023
Priority
Mar 08, 2021 — provisional 63/158,201 +1 more
Examiner
NGUYEN, HAI L
Art Unit
2842
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tesla Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
814 granted / 935 resolved
+19.1% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
9 currently pending
Career history
943
Total Applications
across all art units

Statute-Specific Performance

§101
1.5%
-38.5% vs TC avg
§103
30.5%
-9.5% vs TC avg
§102
28.2%
-11.8% vs TC avg
§112
21.8%
-18.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 935 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Examiner Notes Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: the reference signs “31” is not shown in Figure 3, as mentioned in paragraph [0043]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The abstract of the disclosure is objected to because of exceeding 150 words in length (or 15 lines of text), and it is not limited to a single paragraph. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-9, 12, 20 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 2020/0395257; hereinafter referred to as Chun) in view of Wright et al. (US 2015/0245533; hereinafter referred to as Wright). With regard to claim 1, Chun teaches a system on a wafer (SoW) assembly (see paragraphs [0051] – [0062] and Figs. 14-18) comprising a plurality of integrated circuit dies 50 and one or more routing layers 108 providing electrical connections for the IC dies; a thermal system 200, the thermal system configured to cool the SoW (see paragraphs [0051] – [0062] and Figs. 14-18). Thus, Chun is shown to teach all of the features of the claim with the exception of the thermal system comprises a conductive structure at a ground potential; and a plurality of conductive features in electrical paths between contacts on a surface of the SoW and the conductive structure of the thermal system. Wright shows that it is known in the art to provide a thermal system comprising a conductive structure at a ground potential; and a plurality of conductive features in electrical paths between contacts on a surface of the SoW and the conductive structure of the thermal system (see paragraphs [0006], [0030], [0034], [0050], [0061]-[0065] and in conjunction with Figs. 1-2C). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to implement the thermal system in the system of Chun that comprises a conductive structure at a ground potential; and a plurality of conductive features in electrical paths between contacts on a surface of the SoW and the conductive structure of the thermal system as taught by Wright in order to improve the efficiency for dissipating the heat generated in the system. With regard to claims 2 and 3, the plurality of conductive features ground the SoW to the conductive structure of the thermal system of Chun in view of Wright are also inherently configured to provide electrostatic discharge protection and electromagnetic interference shielding, respectively. With regard to claim 4, the plurality of conductive features of Chun in view of Wright would be obvious positioned around a periphery of the SoW as well. With regard to claims 5-7, the plurality of conductive features of Chun in view of Wright can be used with different type conductive elements such as a conductive foam or a wire bond or a spring loaded clip as well. With regard to claim 8, it would have been obvious that the SoW of Chun can be used as an Integrated Fan-Out wafer. With regard to claim 9, it would have been obvious that the system on a wafer (SoW) assembly of Chun in view of Wright can further comprises voltage regulating modules positioned between the IC dies and the conductive structure of the thermal system which is in each case optimally matched to its application. With regard to claim 12, it would have been obvious that the system on a wafer (SoW) assembly of Chun in view of Wright can set the SoW has a diameter of at least 12 inches as well. Claim 20 is similarly rejected because claim 20 corresponds in substance to apparatus Claim 1, note the above rejection with regard to claim 1. With regard to claim 21, it would have been obvious that the electrically connecting provides electrical connections between the conductive structure and the contacts by way of components on the contacts. Allowable Subject Matter Claims 10, 11 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 13-19 are allowed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAI L NGUYEN whose telephone number is (571)272-1747. The examiner can normally be reached Monday-Friday from 09:00am to 06:00pm Eastern time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached on 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAI L NGUYEN/Primary Examiner, Art Unit 2842 February 13, 2026
Read full office action

Prosecution Timeline

Sep 06, 2023
Application Filed
Feb 20, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
97%
With Interview (+9.5%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 935 resolved cases by this examiner. Grant probability derived from career allowance rate.

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