Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 6, 7 objected to because of the following informalities:
Claims 6, 7 are duplication of claims 3, 4 respectively and so it is assumed that Applicant means to say that claims 6, 7 depend on claim 5. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davids et al. (US 9391225 B1) hereafter referred to as Davids in view of Prineas et al. (US 20110260278 A1) hereafter referred to as Prineas
In regard to claim 1 Davids teaches a light receiving element [see Fig. 1] comprising:
a semiconductor layer [“device 10 may comprise a silicon substrate 12, an insulating layer 14 and a relatively thin (e.g., less than one micron) silicon surface layer 16”] that is formed on a substrate and is formed with a semiconductor;
a p-type p-region [“region 18 may comprise a p-type, conductivity doped silicon region (Si) or “charge” region for short”], an i-type i-region [“Region 28 may comprise an intrinsic, non-doped (non-conductive) silicon region”], and an n-type n-region [“layer 16 may still further comprise a second, or n-type silicon contact region 30 that may function as the second electrical terminal “B” ”] that are formed in the semiconductor layer and form a pin [see Fig. 1] junction in a planar direction of the substrate;
a light absorbing layer [“device 10 may further comprise a germanium (Ge), photon absorption layer 20 which may be positioned over region 18”] that is formed on the p-region of the semiconductor layer;
a contact layer [“A p-type silicon contact area or first electrical contact region 26 may be formed over the germanium layer 20”] that is formed on the light absorbing layer and is formed with a p- type semiconductor;
but does not teach that the light absorbing layer “is formed with a p-type semiconductor” and a p-electrode that is formed to be electrically connected to the contact layer; and an n-electrode that is formed to be electrically connected to the n-region of the semiconductor layer.
See Davids Fig. 1 “In the presence of a strong reverse bias voltage (V.sub.BV) applied between terminals A and B (e.g., tens of volts or higher), the germanium layer 24 may be operable to receive and absorb photons”.
It is noted that a person of ordinary skill in the art is aware that hole mobility in Si is lower than electron mobility and this is related to carrier diffusion length.
However advantages of a p-type absorber are known in the art, see Prineas Fig. 2 see “An advantage of a relatively thick (e.g., between about 3-7 .mu.m or about 5 .mu.m thick) p-doped semiconductor layer 100 is that minority carrier diffusion lengths are longer and so the absorbing region can be thicker and/or detector responsivity can be higher”, see “contact 220' is disposed above contact layer 140' and between patterned dopant regions 210'. In some embodiments, contact 220' has a Pd/Ge/Au/Pt/Au structure” “Hole carriers are collected at a common contact 260' connected to the bottom side of the detector elements 240'. The common contact 260' can have a Ti/Pt/Au structure”, see also that absorption material choice is based on wavelenth, see “The p-doped semiconductor layer 100' can include an antimony-containing III-V semiconductor, including quaternary alloys such as GaInAsSb and/or an InAs/Ga(In)Sb superlattice. By changing the concentration of the constituent elements, the cut-off wavelength of a bulk Ga.sub.1-xIn.sub.xAs.sub.ySb.sub.1-y quaternary alloy (e.g., p-doped semiconductor layer 100') can in principle be tuned from 1.7 .mu.ms to 4.9 .mu.ms while remaining lattice matched or with intentional small strains to a GaSb substrate (e.g., substrate 112')”. See paragraphs 0022-0052, see that III-V material system are a plurality of materials and compositions which gives excellent range of adjustable bandgaps to fine tune the electrical and optical performance of the device.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Davids to include that the light absorbing layer “is formed with a p-type semiconductor” and a p-electrode that is formed to be electrically connected to the contact layer; and an n-electrode that is formed to be electrically connected to the n-region of the semiconductor layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use electrons as minority carrier so as to obtain best absorption and detector responsivity and because electrodes can be used to apply voltage to make the device operate.
In regard to claim 2 Davids and Prineas as combined does not state further comprising: a diffusion barrier layer that is formed between the light absorbing layer and the contact layer and is formed with a semiconductor having a band gap larger than a band gap of the light absorbing layer.
However see that “A p-type silicon contact area or first electrical contact region 26 may be formed over the germanium layer 20” and see that silicon has a higher bandgap than Ge, thus under broadest reasonable interpretation, the lower portion of 26 may be called as “diffusion barrier layer” and the upper portion of 26 may be called as “contact layer” because the claim does not state that the “diffusion barrier layer” and the “contact layer” are made of different materials.
See that carrier blocking is known in the art, see Prineas Fig. 2 see “n-doped semiconductor layer 120' can be n-GaSb and can function as a passivating layer, for example, by inhibiting minority carriers (i.e., holes)”, see band gap of contact, see “contact layer 140' can include n-InAs”, thus because Prineas uses III-V system of materials, Prineas has more flexibility in material choice.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Davids to include further comprising: a diffusion barrier layer that is formed between the light absorbing layer and the contact layer and is formed with a semiconductor having a band gap larger than a band gap of the light absorbing layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to perform both the roles of “diffusion barrier layer” and “contact layer” by the silicon layer 26 for group IV system of materials.
In regard to claim 3 Davids and Prineas as combined teaches wherein the semiconductor is formed [see claim 1 it is silicon] with a group IV element.
In regard to claim 4 Davids and Prineas as combined does not state wherein the semiconductor is a group III-V compound semiconductor.
However see claim 1 see combination, see Prineas, see that absorption material choice is based on wavelenth, see “The p-doped semiconductor layer 100' can include an antimony-containing III-V semiconductor, including quaternary alloys such as GaInAsSb and/or an InAs/Ga(In)Sb superlattice. By changing the concentration of the constituent elements, the cut-off wavelength of a bulk Ga.sub.1-xIn.sub.xAs.sub.ySb.sub.1-y quaternary alloy (e.g., p-doped semiconductor layer 100') can in principle be tuned from 1.7 .mu.ms to 4.9 .mu.ms while remaining lattice matched or with intentional small strains to a GaSb substrate (e.g., substrate 112')”. See paragraphs 0022-0052, see that III-V material system are a plurality of materials and compositions which gives excellent range of adjustable bandgaps to fine tune the electrical and optical performance of the device.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Davids to include wherein the semiconductor is a group III-V compound semiconductor.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that a group III-V compound semiconductor system materials is known to give excellent results in photodiodes to obtain tunable absorption and good electrical performance.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Davids et al. (US 9391225 B1) hereafter referred to as Davids in view of Prineas et al. (US 20110260278 A1) hereafter referred to as Prineas and further in view of Takimoto et al. (US 20200028019 A1) hereafter referred to as Takimoto
In regard to claim 5 Davids teaches a method for manufacturing a light receiving element [see Fig. 1], the method comprising:
a first step of forming, on a substrate, [“device 10 may comprise a silicon substrate 12, an insulating layer 14 and a relatively thin (e.g., less than one micron) silicon surface layer 16”] a semiconductor layer formed with a semiconductor;
a second step of forming, on the semiconductor layer, a light absorbing layer [“device 10 may further comprise a germanium (Ge), photon absorption layer 20 which may be positioned over region 18”] and a contact layer formed [“A p-type silicon contact area or first electrical contact region 26 may be formed over the germanium layer 20”] with a p-type semiconductor;
a p-type p-region [“region 18 may comprise a p-type, conductivity doped silicon region (Si) or “charge” region for short”] in the semiconductor layer under the light absorbing layer;
in the semiconductor layer, an i-type i-region [“Region 28 may comprise an intrinsic, non-doped (non-conductive) silicon region”] and an n- type n-region [“layer 16 may still further comprise a second, or n-type silicon contact region 30 that may function as the second electrical terminal “B” ”] that form a pin junction [see Fig. 1] together with the p-region in a planar direction of the substrate; and
but does not teach a third step of forming, a fourth step of forming, and a fifth step of forming,
and does not teach that the light absorbing layer is “formed with a p-type semiconductor” and a p-electrode that is electrically connected to the contact layer and an electrode that is electrically connected to the n-region of the semiconductor layer.
See Davids Fig. 1 “In the presence of a strong reverse bias voltage (V.sub.BV) applied between terminals A and B (e.g., tens of volts or higher), the germanium layer 24 may be operable to receive and absorb photons”.
It is noted that a person of ordinary skill in the art is aware that hole mobility in Si is lower than electron mobility and this is related to carrier diffusion length.
However advantages of a p-type absorber are known in the art, see Prineas Fig. 2 see “An advantage of a relatively thick (e.g., between about 3-7 .mu.m or about 5 .mu.m thick) p-doped semiconductor layer 100 is that minority carrier diffusion lengths are longer and so the absorbing region can be thicker and/or detector responsivity can be higher”, see “contact 220' is disposed above contact layer 140' and between patterned dopant regions 210'. In some embodiments, contact 220' has a Pd/Ge/Au/Pt/Au structure” “Hole carriers are collected at a common contact 260' connected to the bottom side of the detector elements 240'. The common contact 260' can have a Ti/Pt/Au structure”, see also that absorption material choice is based on wavelenth, see “The p-doped semiconductor layer 100' can include an antimony-containing III-V semiconductor, including quaternary alloys such as GaInAsSb and/or an InAs/Ga(In)Sb superlattice. By changing the concentration of the constituent elements, the cut-off wavelength of a bulk Ga.sub.1-xIn.sub.xAs.sub.ySb.sub.1-y quaternary alloy (e.g., p-doped semiconductor layer 100') can in principle be tuned from 1.7 .mu.ms to 4.9 .mu.ms while remaining lattice matched or with intentional small strains to a GaSb substrate (e.g., substrate 112')”. See paragraphs 0022-0052, see that III-V material system are a plurality of materials and compositions which gives excellent range of adjustable bandgaps to fine tune the electrical and optical performance of the device.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Davids to include that the light absorbing layer is “formed with a p-type semiconductor” and a p-electrode that is electrically connected to the contact layer and an electrode that is electrically connected to the n-region of the semiconductor layer .
The motivation is to use electrons as minority carrier so as to obtain best absorption and detector responsivity and because electrodes can be used to apply voltage to make the device operate.
Davids and Prineas as combined does not state a third step of forming, a fourth step of forming, and a fifth step of forming.
See in Prineas the “contact 220' is disposed above contact layer 140' and between patterned dopant regions 210'. In some embodiments, contact 220' has a Pd/Ge/Au/Pt/Au structure” “Hole carriers are collected at a common contact 260' connected to the bottom side of the detector elements 240'. The common contact 260' can have a Ti/Pt/Au structure”.
See Takimoto teaches that implants can be done in any order, see Fig. 1, see that implants are from the top down see “low-concentration P-type diffusion layer 2 is formed by ion implantation of boron (.sup.11B+). For example, boron (.sup.11B+) is implanted under the following three-stage ion implantation conditions” “Subsequently, a low-concentration N-type diffusion layer 3” “This low-concentration N-type diffusion layer 3 is also formed by ion implantation” “Subsequently, a high-concentration N-type buried diffusion layer 5 serving as an N-type diffusion layer of the avalanche junction is formed. For example, ion implantation of phosphorus (.sup.31P+) is performed” “Subsequently, a high-concentration N-type buried diffusion layer 6 is formed deeper than the N-type buried diffusion layer 5 so as to connect to the low-concentration N-type diffusion layer 3” “This N-type buried diffusion layer 6 is formed by, for example, ion implantation of phosphorus (.sup.31P+) at an ion implantation energy of 1.5 MeV at a dose of 6.0E+12 cm.sup.−2, and subsequent heat treatment such as annealing at 800° C. to 900° C”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Davids to include a third step of forming, a fourth step of forming, and a fifth step of forming.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that this is an easy way to place the P doping under the Germanium layer and the N layer a desired distance away and also easy to save space in this way.
In regard to claim 6 [see claim objection] Davids Prineas and Takimoto as combined teaches wherein the semiconductor is formed [see claim 5 it is silicon] with a group IV element.
In regard to claim 7 [see claim objection] Davids Prineas and Takimoto as combined does not state wherein the semiconductor is a group III-V compound semiconductor.
However see claim 5 see combination, see Prineas, see that absorption material choice is based on wavelenth, see “The p-doped semiconductor layer 100' can include an antimony-containing III-V semiconductor, including quaternary alloys such as GaInAsSb and/or an InAs/Ga(In)Sb superlattice. By changing the concentration of the constituent elements, the cut-off wavelength of a bulk Ga.sub.1-xIn.sub.xAs.sub.ySb.sub.1-y quaternary alloy (e.g., p-doped semiconductor layer 100') can in principle be tuned from 1.7 .mu.ms to 4.9 .mu.ms while remaining lattice matched or with intentional small strains to a GaSb substrate (e.g., substrate 112')”. See paragraphs 0022-0052, see that III-V material system are a plurality of materials and compositions which gives excellent range of adjustable bandgaps to fine tune the electrical and optical performance of the device.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Davids to include wherein the semiconductor is a group III-V compound semiconductor.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that a group III-V compound semiconductor system materials is known to give excellent results in photodiodes to obtain tunable absorption and good electrical performance.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893