Prosecution Insights
Last updated: October 23, 2026
Application No. 18/550,025

METHOD FOR CONTROLLING A DEVICE, AND CIRCUIT DEVICE

Non-Final OA §102
Filed
Sep 11, 2023
Priority
Apr 30, 2021 — DE 10 2021 204 358.5 +1 more
Examiner
KIM, TAE W
Art Unit
2876
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Robert Bosch GmbH
OA Round
1 (Non-Final)
55%
Grant Probability
Moderate
1-2
OA Rounds
7m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 55% of resolved cases
55%
Career Allowance Rate
194 granted / 354 resolved
-13.2% vs TC avg
Strong +37% interview lift
Without
With
+36.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
14 currently pending
Career history
373
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
55.7%
+15.7% vs TC avg
§102
15.9%
-24.1% vs TC avg
§112
23.9%
-16.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 354 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 10-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHIMOMURA (US 20180131178 A1). Re Claim 10: SHIMOMURA discloses a method for controlling a device for enabling and interrupting a flow of electric current between a battery and a load or a charging device (p21: controls a system that supplies power of a battery mounted in the vehicle to a motor through an inverter.), the device including at least one transistor (fig. 1: 3, p26: switching device 3 is a P-channel MOSFET), the method comprising: setting a gate voltage of the at least one transistor based on: i) a current flowing through the at least one transistor (p49: the driving control device 5 may adjust the gate voltage such that the current flowing through the current path does not exceed an allowed current value of each device connected to the current path.), and/or a temperature of the at least one transistor. Re Claim 11: SHIMOMURA discloses the method according to claim 10, further comprising: increasing the gate voltage when the current flowing through the at least one transistor exceeds a first predetermined value (p49: the driving control device 5 may adjust the gate voltage such that the current flowing through the current path does not exceed an allowed current value of each device connected to the current path.). Re Claim 12: SHIMOMURA discloses the method according to claim 10, further comprising: reducing the gate voltage when the current flowing through the at least one transistor falls below a second predetermined value (p49: the driving control device 5 may adjust the gate voltage such that the current flowing through the current path does not exceed an allowed current value of each device connected to the current path.). Re Claim 13: SHIMOMURA discloses the method according to claim 10, further comprising: setting the gate voltage to a negative value for a predetermined period of time as soon as the device has been switched on (p47: the driving voltage of the switching device 3 is gradually raised from a low state from time t3) and the current flowing through the at least one transistor is not constant (p44: the driving control device 5 raises the driving voltage... from VOFF... at time t3... to time t4). Re Claim 14: SHIMOMURA discloses the method according to claim 10, further comprising: setting the gate voltage is set to a negative value for a further predetermined period of time as soon as the device has been switched off (p66: lowers the driving voltage of the switching device 3 from VON to VOFF... switching the switching device 3 from the On state to the Off state) and the current flowing through the at least one transistor is greater than 0 amperes (p64: in a state in which the current flows through the current path... the driving control device 5 sets the switching device 3 and the relay 4 to the Off states). Re Claim 15: SHIMOMURA discloses the method according to claim 10, further comprising: setting the gate voltage 0 volts or to a negative value when the device has been switched off and the current flowing through the at least one transistor is equal to 0 A (p66: the driving control device 5... lowers the driving voltage of the relay 4 from VON to VOFF... switching the relay 4 from the On state to the Off state). Re Claim 16: SHIMOMURA discloses the method according to claim 15, wherein the at least one transistor is a metaloxide-semiconductor field-effect transistor (MOSFET) or a traction inverter (p26: switching device 3 is a P-channel MOSFET). Re Claim 17: SHIMOMURA discloses the method according to claim 10, wherein the device is controlled in an electric vehicle, or in a hybrid vehicle, or in a plug-in hybrid vehicle (p21: The power supply control apparatus according to this embodiment is disposed in a vehicle). Re Claim 18: SHIMOMURA discloses a circuit device, comprising: an arrangement configured to control a device (p34: The driving control device 5 is a controller that controls On/Off of the switching device 3 and the relay 4) for enabling and interrupting a flow of electric current between a battery and a load or a charging device (p21: controls a system that supplies power of a battery mounted in the vehicle to a motor through an inverter.), the device including at least one transistor (fig. 1: 3, p26: switching device 3 is a P-channel MOSFET), the arrangement configured to: set a gate voltage of the at least one transistor based on: i) a current flowing through the at least one transistor (p49: the driving control device 5 may adjust the gate voltage such that the current flowing through the current path does not exceed an allowed current value of each device connected to the current path.), and/or a temperature of the at least one transistor. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAE W KIM whose telephone number is (571)272-5971. The examiner can normally be reached M-F 9:30AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven S Paik can be reached at 5712722404. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAE W KIM/Examiner, Art Unit 2876 /THIEN M LE/Primary Examiner, Art Unit 2876
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Prosecution Timeline

Sep 11, 2023
Application Filed
Sep 30, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
55%
Grant Probability
92%
With Interview (+36.7%)
3y 9m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 354 resolved cases by this examiner. Grant probability derived from career allowance rate.

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