Prosecution Insights
Last updated: April 19, 2026
Application No. 18/550,252

METHOD FOR PRODUCING WIRING CIRCUIT BOARD

Non-Final OA §102§103
Filed
Sep 12, 2023
Examiner
BAREFORD, KATHERINE A
Art Unit
1718
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Nitto Denko Corporation
OA Round
3 (Non-Final)
13%
Grant Probability
At Risk
3-4
OA Rounds
4y 11m
To Grant
42%
With Interview

Examiner Intelligence

Grants only 13% of cases
13%
Career Allow Rate
123 granted / 925 resolved
-51.7% vs TC avg
Strong +28% interview lift
Without
With
+28.3%
Interview Lift
resolved cases with interview
Typical timeline
4y 11m
Avg Prosecution
77 currently pending
Career history
1002
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
43.6%
+3.6% vs TC avg
§102
9.6%
-30.4% vs TC avg
§112
35.8%
-4.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 925 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 2, 2025 has been entered. The amendment filed with the RCE submission of December 2, 2025 has been received and entered. With the entry of the amendment, claims 1-4 are pending for examination. Claim Rejections - 35 USC § 102 The rejection of claim 1 under 35 U.S.C. 102(a)(1) as being anticipated by Japan 2016-027521 (hereinafter ‘521) is withdrawn due to the amendment of December 2, 2025, changing the scope of the claims. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Japan 2016-027521 (hereinafter ‘521) in view of Ookawa et al (US 2002/0100609), EITHER alone OR further in view of Japan 2006-186281 (hereinafter ‘281). Claim 1: ‘281 teaches a method for producing a wiring circuit board (note the page 3, translation, the wiring/circuits on a substrate support that can be considered a board). This circuit board can be used for a hard disk drive (note page 3, translation). The method includes a first step of forming an insulating layer 23 on one surface of a substrate (metal support substrate 21) in a thickness direction of the substrate (note figure 10(a), translation page 6). A second step is provided of forming a plurality of wirings (note 11A, 11B, 12A, 12B) on one surface of the insulating layer in the thickness direction of the insulating layer (note figure 10(a)-(b), translation, page 6). A third step is provided of forming a first opening portion in the substrate when projected in the thickness direction of the substrate, the first opening portion including width below the plurality of wirings (note figure 11(g), translation, page 6, note opening regions 22). A fourth step is provided of forming a resist pattern 42 having a second opening portion having a pattern shape below the plurality of wirings on the other surface of the insulating layer in the thickness direction of the insulating layer (note figure 11(h), and translation page 6). There is a fifth step that is provided of forming a metal support portion by depositing a metal material on the other surface of the insulating layer in the thickness direction of the insulating layer inside the second opening portion (note figure 11(i), where metal plating film layer 17A, which can be copper, applied, which can be considered a metal support portion, as a metal layer provided, with no limit as to what thickness in claim 1 needed as a “support” portion, where the plating can be electrolytic plating, note translation, page 6). Thereafter, there is a sixth step of removing this resist (note, Figure 11(j) and translation page 6). As to in the fourth step, forming the resist pattern to have a plurality of second opening portions separated from each other with a pattern shape below the plurality of wirings, and in the fifth step depositing metal material inside the plurality of second opening portions separated from one another, ‘521 describes forming a metal plating film layer 17A that extends across and under the area of multiple of the wirings 11A, 11B, 12A, 12B, so that only one second opening is shown in the resist pattern (note figure 11(i), figure 5). However, Ookawa also teaches producing a wiring circuit board, which can also be used for a hard disk drive (note figures 1, 2, 5, 0002). Ookawa teaches that the resulting structure of the circuit board has an insulating layer 22 with a plurality of wirings 23 (note 23a, 23b) formed on the insulating layer and a metal layer formed on the other side of the insulating layer 22 in a thickness direction of the insulting layer, where the metal layer 27 is formed below the wirings (note figures 2, 5, 0036, 0041, 0045-0046). The metal layer 27 can be formed by electroless or electroplating (electrolytic) plating of metal such as copper, nickel, gold, etc. (note 0046). Ookawa teaches that there can be a single layer 27 that extends across multiple wirings (note figure 2, 0060), or the metal layer 27 can be spaced apart so that there are multiple separate layers 27, one under each wiring that is separated from other layers 27 (note figure 5), where this has the benefit of reducing characteristic impedance (note figure 5, 0061). The metal layer 27 thickness can be 100 Angstrom to 50 microns in thickness (note 0049). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify ‘521 to provide that the fourth step includes forming the resist pattern to have a plurality of second opening portions separated from each other with a pattern shape below the plurality of wirings, and in the fifth step depositing metal material inside the plurality of second opening portions separated from one another as suggested by Ookawa with the expectation of providing a desirable metal support layer pattern with reduced characteristic impedance, since ‘521 is making a circuit board system for a hard disk drive with an insulating layer with a first service with a plurality of wirings and a metal plating layer/metal support portion on the other side of the wirings/insulating layer to be under the wirings, and Ookawa teaches that for a similar such system, with a similar plating layer of similar material, either a single metal plating layer can be provided extending across multiple wirings, or separate separated metal plating layers can be provided so that there is a separate metal plating layer under each wiring to give a desired reduced characteristic impedance. To provide the plating in the desired area, ‘521 shows covering the area of the other surface of the insulating layer, etc. not to be plated with resist 42 (note figures 11(h), 11(i), page 6, translation), and therefore, when not wanting to plate over additional areas between the overlaying wiring patterns as suggested by the combination with Ookawa, it would have been further suggested to apply additional resist in those areas not desired to be coated, giving a resist pattern that has a plurality of second opening portions separated from one another as claimed where the metal plating will occur in the second opening portions separated from one other, based on where the plating is to occur, since the resist will act in the same form and be used for the same desired masking treatment, just be applied in the specific pattern desired for achieving the desired separate plating layers under each metal wiring. Note as well, MPEP 2144.04(VI) where duplication of parts (here more resist) and/or rearrangement of parts (here different pattern of resist) would be obvious expedients. Optionally, further using ‘281, additionally as to providing the resist to give a plurality of second opening portions separated from one another, where the metal plating layers/metal support portions are deposited in the second openings, when using the suggestion of ‘521 in view of Ookawa to provide separate metal plating layers under each wiring, ‘281 describes a process for forming a circuit board (abstract), where multiple wirings 5 (conductor pattern) are applied over an insulating layer 4 (note figure 4(d), and separate metal plating layers 14 are to be separately provided below each wiring (note figure 6 (i)-(l) and translation, pages 4-5, where it is indicated to provide resist coatings over the surfaces where plating not desired, which would give a resist pattern having a plurality of second opening positions separated from one another to give second openings where plating desired, and then providing plating inside the plurality of second opening portions (note figure 6(i)-(1), and translation, page 5). Therefore, it further would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify ‘521 in view of Ookawa to additionally provide the resist to give a plurality of second opening portions separated from one another, where the metal plating layers are deposited in the second openings as suggested by ‘281 with an expectation of providing a desired separately patterned plating layer, since as discussed above, Ookawa would suggest the desire to plate separate metal plating layers on the back surface of the insulating layer under the separate wiring layers, so that the different metal plating layers/metal support portions are separated from each other, and ‘281 indicates that when providing such a pattern of metal plating layers under wiring layers that area separated from each other, it would be conventionally known in the art to provide resist over all the areas where plating not desired on the surface, such that in the process of ‘521 in view of Ookawa, the resist pattern would be applied to give a plurality of second opening portions separated from one another, where the metal plating layers are deposited in the second openings, Claim 4: Furthermore, as to the thickness of metal support portion (metal plating film layer 17A), ‘521 teaches that the metal support portion/metal plating film layer 17A (described as first conductor film) can have any thickness that can form inductive or capacitive coupling with the wiring and contribute to the reduction of the differential impedance, and can be for example, 1 micron or more (note page 6, translation). Additionally, Ookawa indicates that in a similar structure, the metal plating layer can be 100 Angstroms to 50 microns in thickness (note 0049), also overlapping the claimed range. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify ‘521 in view of Ookawa, EITHER alone OR further in view of ‘281 to optimize the thickness of the metal support portion /first conductor film to provide the best thickness greater than 1 micron for the specific article formed from the teaching of ‘521 and also Ookawa as noted above as to the possible thicknesses that can be used, giving a value in the claimed range. Note "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over ‘521 in view of Ookawa, EITHER alone OR further in view of ‘281 as applied to claims 1 and 4 above, and further in view of Fujimura et al (US 2016/0270216). Claims 2-3, as to providing that the insulating layer has a thick/thicker portion and a thin/thinner portion than the thick/thicker portion, where the wiring is formed on the thicker portion (as in claim 3), with a seventh step of forming a third opening portion in the insulating layer (claim 2), where the third opening portion is performed by removing the thin portion by an etching process by an etching process from the other side in the thickness direction with respect to the insulating layer (claim 3), Fujimura describes a desired forming of a wiring circuit board (note 0010) used for a hard disk drive (note 0003). The process includes providing a metal supporting substrate, and forming an insulating layer on one surface in a thickness dimension of the substrate (note figures 5A-C, 7A-C, 0162, 0168-0169). Furthermore, a plurality of wirings/conductive pattern are formed on one surface of the substrate/insulating layer in a thickness direction of the insulting layer (note on upper surface area) (note figures 8A-C, 0170-0172). Fujimura also indicates how the substrate can be removed in sections after the wirings formed, and further how sections (patterns) would be formed where the metal supporting substrate thickness remains under the wiring, where the supporting board can act as an electrical conductor (note figures 3B, 12B, 0184-0188). The board can be stainless steel, aluminum, copper-beryllium etc. and have a thickness of 50 microns or less, preferably 25 microns or less (note 0119). Fujimura further describes (for the wirings/conductive pattern) how nickel or gold can be provided in a thickness of 3-30 microns, for example (note 0145-0146). Fujimura further describes where the insulating layer can be one thickness (note figures 7A, 7C) or where the insulating layer can have thick/thicker portions and relatively thin/thinner portions (note figure 7B, 0168-0169), where the wiring can be formed on the thicker portion (and also some on the thinner portions, which is not prevented) (note figure 8B). Fujimura provides that the insulating layer can be polyimide, for example (note 0125). It is further indicated that substrate can be removed leaving the exposed insulting layer under thinner portions (note figure 10B, 0177). It is further indicated that after processing, the insulating layer can be removed at these thinner portions (that is, forming a third opening portion in the insulating layer between the wirings adjacent to each other ) (note figures 11B, 3B, 0181-0182), where it is indicated that the insulating layer (section 47) can be removed by etching, including wet etching (note 0179-0182). Therefore, if further would have been obvious to modify ‘521 in view of Ookawa, EITHER alone OR further in view of ‘281 to provide that the insulating layer has relatively thick and thin portions as claimed with wiring layers formed on the thick portion as claimed as suggested by Fujimura with an expectation of predictably acceptable results, since ‘521 is forming a wiring/circuit board structure with wiring applied on an insulating layer on a substrate for use for a hard disk drive, and Fujimura indicates the conventionality, when forming wiring/circuit boards with wiring forming on an insulating layer over a substrate for use for hard disk drives, of the form of providing that the insulating layer has relatively thick and thin portions as claimed with wiring layers formed on the thick portion, as well as using insulating layers of one thickness. Furthermore, as to forming a third opening layer in the insulating layer between the wirings adjacent to each other, Fujimura would further suggest this as conventional in forming a desired pattern of wirings on circuit boards. Furthermore as to removing the thin portion of the insulating layer by an etching process from the other side in the thickness direction with respect to the insulating layer, Fujimura shows the desire to provide openings through the layers between the wirings (as shown in figure 3B), which would be through thin portions of the insulating layer, where ‘521 shows that there can be exposed area on the other side of the insulating layer 23 after the resist removing sixth step, where these openings would be apart from the wirings (there is also a layer 24 on the upper surface of layer 23, but both layer 23, 24 can be polyimide, where Fujimura also notes the insulating layers can be polyimide), for example, so understood to be removable in the same fashion, note translation, page 6, figure 11(j)), and therefore, to provide the opening through layers, it would be understood that the layer 23 (and layer 24) in thin separating portions (as in Fujimura) can be etched where the opening desired, with Fujimura noting the conventional use of wet etching on such a layer, material where since the etching would be to remove the insulating layer(s), it would have been obvious to one of ordinary skill in the art to provide the etching on both sides of the insulating layer(s) to more quickly and efficiently provide the etching, and thus providing at least some removal of the thin portion by etching from the other side of the insulting layer. Alternatively, Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ookawa et al (US 2002/0100609) in view of Japan 2016-027521 (hereinafter ‘521), EITHER alone OR further in view of Japan 2006-186281 (hereinafter ‘281). Claim 1: Ookawa also teaches producing a wiring circuit board, which can also be used for a hard disk drive (note figures 1, 2, 5, 0002). Ookawa teaches that the resulting structure of the circuit board has an insulating layer 22 with a plurality of wirings 23 (note 23a, 23b) formed on one surface of the insulating layer in a thickness direction of the insulating layer and a metal layer formed on the other side of the insulating layer 22 in a thickness direction of the insulting layer, where the metal layer 27 is formed below the wirings (note figures 2, 5, 0036, 0041, 0045-0046). The metal layer 27 can be formed by depositing electroless or electroplating (electrolytic) plating of metal such as copper, nickel, gold, etc. (note 0046). Ookawa teaches that there can be a single layer 27 that extends across multiple wirings (note figure 2, 0060), or the metal layer 27 can be spaced apart so that there are multiple separate layers 27, one under each wiring that is separated from other layers 27 (note figure 5), where this has the benefit of reducing characteristic impedance (note figure 5, 0061). The metal layer 27 thickness can be 100 Angstrom to 50 microns in thickness (note 0049), overlapping that described in present claim 4, so can be understood to be acceptably providing a metal support portion. Ookawa does not teach the specific method of forming the structure, where the insulating layer is formed on a one surface of a substrate in a thickness direction of the substrate, a step of forming a first opening portion in the substrate when projected in the thickness direction of the substrate, where the first opening portion includes a width below the plurality of wirings, a step of forming a resist pattern having a plurality of second opening portions separated from one another and having a pattern shape below the plurality of wirings on another surface of the insulating layer in the thickness direction of the insulating layer, and forming a metal support portion by depositing metal material on the other surface of the insulating layer in the thickness direction of the insulating layer inside the plurality of second opening portions separated from one another, and removing the resist pattern, ‘281 teaches a method for producing a wiring circuit board (note the page 3, translation, the wiring/circuits on a substrate support that can be considered a board). This circuit board can be used for a hard disk drive (note page 3, translation). The method includes a first step of forming an insulating layer 23 on one surface of a substrate (metal support substrate 21) in a thickness direction of the substrate (note figure 10(a), translation page 6). A second step is provided of forming a plurality of wirings (note 11A, 11B, 12A, 12B) on one surface of the insulating layer in the thickness direction of the insulating layer (note figure 10(a)-(b), translation, page 6). A third step is provided of forming a first opening portion in the substrate when projected in the thickness direction of the substrate, the first opening portion including width below the plurality of wirings (note figure 11(g), translation, page 6, note opening regions 22). A fourth step is provided of forming a resist pattern 42 having a second opening portion having a pattern shape below the plurality of wirings on the other surface of the insulating layer in the thickness direction of the insulating layer (note figure 11(h), and translation page 6). There is a fifth step that is provided of forming a metal support portion by depositing a metal material on the other surface of the insulating layer in the thickness direction of the insulating layer inside the second opening portion (note figure 11(i), where metal plating film layer 17A, which can be copper, applied, which can be considered a metal support portion, as a metal layer provided, with no limit as to what thickness in claim 1 needed as a “support” portion, where the plating can be electrolytic plating, note translation, page 6). Thereafter, there is a sixth step of removing this resist (note, Figure 11(j) and translation page 6). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ookawa to provide forming the wiring board structure a method such that the insulating layer is formed on a one surface of a substrate in a thickness direction of the substrate, a plurality of wirings is formed on one surface of the insulating layer in a thickness direction of the insulating layer, a step of forming a first opening portion in the substrate when projected in the thickness direction of the substrate, where the first opening portion includes a width below the plurality of wirings, a step of forming a resist pattern having a plurality of second opening portions separated from one another and having a pattern shape below the plurality of wirings on another surface of the insulating layer in the thickness direction of the insulating layer, and forming a metal support portion by depositing metal material on the other surface of the insulating layer in the thickness direction of the insulating layer inside the plurality of second opening portions separated from one another, and removing the resist pattern, as suggested by ‘521 with an expectation of predictably acceptable results, since Ookawa wants to provide a circuit board structure for hard disk drives with a resulting insulation layer with a plurality of wirings formed on one surface of the insulating layer in a thickness direction of the insulating layer, with a pattern of metal support portion on the other side of the insulating layer in a plurality of separate metal layers each under a wiring pattern (or a single layer overlapping all wiring), applied by electroplating, and ‘521 indicates how a similar such structure can be provided by forming the wiring board structure a method such that the insulating layer is formed on a one surface of a substrate in a thickness direction of the substrate, a plurality of wirings is formed on one surface of the insulating layer in a thickness direction of the insulating layer, a step of forming a first opening portion in the substrate when projected in the thickness direction of the substrate, where the first opening portion includes a width below the plurality of wirings, a step of forming a resist pattern having an opening portion below the plurality of wirings on another surface of the insulating layer in the thickness direction of the insulating layer, and forming a metal support portion by depositing metal material on the other surface of the insulating layer in the thickness direction of the insulating layer inside the opening portion, and removing the resist pattern; further as to providing the resist pattern with the second opening portions as claimed and the plating inside the second opening portions, Ookawa indicates providing a single metal portion layer (as also described by ‘521) or a plurality of separate plating layers, each under a corresponding wiring and separated from each other, and provide the plating in the desired area, ‘521 shows covering the area of the other surface of the insulating layer, etc. not to be plated with resist 42 (note figures 11(h), 11(i), page 6, translation), and therefore, when not wanting to plate over additional areas between the overlaying wiring patterns as described by the combination with Ookawa, it would have been further suggested to apply additional resist in those areas not desired to be coated, giving a resist pattern that has a plurality of second opening portions separated from one another as claimed where the metal plating will occur in the second opening portions separated from one other, based on where the plating is to occur, since the resist will act in the same form and be used for the same desired masking treatment, just be applied in the specific pattern desired for achieving the desired separate plating layers under each metal wiring. Note as well, MPEP 2144.04(VI) where duplication of parts (here more resist) and/or rearrangement of parts (here different pattern of resist) would be obvious expedients. Optionally, further using ‘281, additionally as to providing the resist to give a plurality of second opening portions separated from one another, where the metal plating layers/metal support portions are deposited in the second openings, when using the suggestion of Ookawa in view of ‘521 to provide separate metal plating layers under each wiring, ‘281 describes a process for forming a circuit board (abstract), where multiple wirings 5 (conductor pattern) are applied over an insulating layer 4 (note figure 4(d), and separate metal plating layers 14 are to be separately provided below each wiring (note figure 6 (i)-(l) and translation, pages 4-5, where it is indicated to provide resist coatings over the surfaces where plating not desired, which would give a resist pattern having a plurality of second opening positions separated from one another to give second openings where plating desired, and then providing plating inside the plurality of second opening portions (note figure 6(i)-(1), and translation, page 5). Therefore, it further would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ookawa in view of ‘521 to additionally provide the resist to give a plurality of second opening portions separated from one another, where the metal plating layers are deposited in the second openings as suggested by ‘281 with an expectation of providing a desired separately patterned plating layer, since as discussed above, Ookawa would suggest the desire to plate separate metal plating layers on the back surface of the insulating layer under the separate wiring layers, so that the different metal plating layers/metal support portions are separated from each other, and ‘281 indicates that when providing such a pattern of metal plating layers under wiring layers that area separated from each other, it would be conventionally known in the art to provide resist over all the areas where plating not desired on the surface, such that in the process of Ookawa in view of ‘521, the resist pattern would be applied to give a plurality of second opening portions separated from one another, where the metal plating layers are deposited in the second openings, Claim 4: Furthermore, as to the thickness of metal support portion (metal plating film layer 17A), ‘521 teaches that the metal support portion/metal plating film layer 17A (described as first conductor film) can have any thickness that can form inductive or capacitive coupling with the wiring and contribute to the reduction of the differential impedance, and can be for example, 1 micron or more (note page 6, translation). Additionally, Ookawa indicates that in a similar structure, the metal plating layer can be 100 Angstroms to 50 microns in thickness (note 0049), also overlapping the claimed range. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ookawa in view of ‘521, EITHER alone OR further in view of ‘281 to optimize the thickness of the metal support portion /first conductor film to provide the best thickness greater than 1 micron for the specific article formed from the teaching of ‘521 and also Ookawa as noted above as to the possible thicknesses that can be used, giving a value in the claimed range. Note "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Ookawa in view of ‘521, EITHER alone OR further in view of ‘281 as applied to claims 1 and 4 above, and further in view of Fujimura et al (US 2016/0270216). Claims 2-3, as to providing that the insulating layer has a thick/thicker portion and a thin/thinner portion than the thick/thicker portion, where the wiring is formed on the thicker portion (as in claim 3), with a seventh step of forming a third opening portion in the insulating layer (claim 2), where the third opening portion is performed by removing the thin portion by an etching process by an etching process from the other side in the thickness direction with respect to the insulating layer (claim 3), Fujimura describes a desired forming of a wiring circuit board (note 0010) used for a hard disk drive (note 0003). The process includes providing a metal supporting substrate, and forming an insulating layer on one surface in a thickness dimension of the substrate (note figures 5A-C, 7A-C, 0162, 0168-0169). Furthermore, a plurality of wirings/conductive pattern are formed on one surface of the substrate/insulating layer in a thickness direction of the insulting layer (note on upper surface area) (note figures 8A-C, 0170-0172). Fujimura also indicates how the substrate can be removed in sections after the wirings formed, and further how sections (patterns) would be formed where the metal supporting substrate thickness remains under the wiring, where the supporting board can act as an electrical conductor (note figures 3B, 12B, 0184-0188). The board can be stainless steel, aluminum, copper-beryllium etc. and have a thickness of 50 microns or less, preferably 25 microns or less (note 0119). Fujimura further describes (for the wirings/conductive pattern) how nickel or gold can be provided in a thickness of 3-30 microns, for example (note 0145-0146). Fujimura further describes where the insulating layer can be one thickness (note figures 7A, 7C) or where the insulating layer can have thick/thicker portions and relatively thin/thinner portions (note figure 7B, 0168-0169), where the wiring can be formed on the thicker portion (and also some on the thinner portions, which is not prevented) (note figure 8B). Fujimura provides that the insulating layer can be polyimide, for example (note 0125). It is further indicated that substrate can be removed leaving the exposed insulting layer under thinner portions (note figure 10B, 0177). It is further indicated that after processing, the insulating layer can be removed at these thinner portions (that is, forming a third opening portion in the insulating layer between the wirings adjacent to each other ) (note figures 11B, 3B, 0181-0182), where it is indicated that the insulating layer (section 47) can be removed by etching, including wet etching (note 0179-0182). Therefore, if further would have been obvious to modify Ookawa in view of ‘521, EITHER alone OR further in view of ‘281 to provide that the insulating layer has relatively thick and thin portions as claimed with wiring layers formed on the thick portion as claimed as suggested by Fujimura with an expectation of predictably acceptable results, since Ookawa and ‘521 are forming a wiring/circuit board structure with wiring applied on an insulating layer on a substrate for use for a hard disk drive, and Fujimura indicates the conventionality, when forming wiring/circuit boards with wiring forming on an insulating layer over a substrate for use for hard disk drives, of the form of providing that the insulating layer has relatively thick and thin portions as claimed with wiring layers formed on the thick portion, as well as using insulating layers of one thickness. Furthermore, as to forming a third opening layer in the insulating layer between the wirings adjacent to each other, Fujimura would further suggest this as conventional in forming a desired pattern of wirings on circuit boards. Furthermore as to removing the thin portion of the insulating layer by an etching process from the other side in the thickness direction with respect to the insulating layer, Fujimura shows the desire to provide openings through the layers between the wirings (as shown in figure 3B), which would be through thin portions of the insulating layer, where ‘521 shows that there can be exposed area on the other side of the insulating layer 23 after the resist removing sixth step, where these openings would be apart from the wirings (there is also a layer 24 on the upper surface of layer 23, but both layer 23, 24 can be polyimide, where Fujimura also notes the insulating layers can be polyimide), for example, so understood to be removable in the same fashion, note translation, page 6, figure 11(j)), and therefore, to provide the opening through layers, it would be understood that the layer 23 (and layer 24) in thin separating portions (as in Fujimura) can be etched where the opening desired, with Fujimura noting the conventional use of wet etching on such a layer, material where since the etching would be to remove the insulating layer(s), it would have been obvious to one of ordinary skill in the art to provide the etching on both sides of the insulating layer(s) to more quickly and efficiently provide the etching, and thus providing at least some removal of the thin portion by etching from the other side of the insulting layer. Oshima et al (US 2018/0047661) notes forming a circuit board with insulating films, and wiring patterns, and removal of a substrate portion under the wiring (note abstract, figure 4). It is noted that ‘281 was provided with the PTO-892 of March 31, 2025. Response to Arguments Applicant's arguments filed December 2, 2025 have been fully considered. Note the adjustment to the rejections due to the amendments to the claims. Applicant has argued that ‘’521 would not provide the features now claimed as to a resist pattern with a plurality of second opening portions and plating in the plurality of second opening portions. The Examiner notes these arguments. The new reference to Ookawa has been provided as to the suggestion to provide the multiple separate metal platings for the metal support portion, and the resist and plating features as claimed, and additionally, optionally, ‘281 is further cited as to the known use of resist placement to provide the separated metal platings. Therefore, the rejections above are maintained. Any other previous responses that apply to the claims as now worded and the rejections now used are also maintained for the reasons previously given, and the discussion above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KATHERINE A BAREFORD whose telephone number is (571)272-1413. The examiner can normally be reached M-Th 6:00 am -3:30 pm, 2nd F 6:00 am -2:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GORDON BALDWIN can be reached at 571-272-5166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KATHERINE A BAREFORD/Primary Examiner, Art Unit 1718
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Prosecution Timeline

Sep 12, 2023
Application Filed
Mar 25, 2025
Non-Final Rejection — §102, §103
Jun 26, 2025
Response Filed
Aug 30, 2025
Final Rejection — §102, §103
Dec 02, 2025
Request for Continued Examination
Dec 04, 2025
Response after Non-Final Action
Jan 13, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
13%
Grant Probability
42%
With Interview (+28.3%)
4y 11m
Median Time to Grant
High
PTA Risk
Based on 925 resolved cases by this examiner. Grant probability derived from career allow rate.

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