DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murakami ( US 2022 / 0262970 - also published as JP 2021/027084 ) in view of Kasuga ( US 2020 / 0106982 – also published as WO 2018/216400 ). Regarding Claim 1, Murakami teaches a sensor element [ Fig 3, 4 ] comprising: a sensor substrate in which a single photon avalanche diode (SPAD) is provided on a semiconductor substrate for each pixel [ #22, #31 of Fig 3, 4; 0053-58; 0062-81 ; 0090-0100 ] ; a logic substrate laminated on the sensor substrate and provided with a logic circuit [ #33 of Fig 3, 4; 0053-58; 0062-81 ; 0090-0100 ] ; and a plurality of transistors used to output a signal according to a cathode voltage or an anode voltage of the SPAD [ #23, #24 of Fig 3, 4; 0053-58; 0062-81; 0090-0100 ] . Murakami does not explicitly teach – but Kasuga does teach wherein at least some of the plurality of the transistors are provided in a well formed in the semiconductor substrate of the sensor substrate [ #3, #4, #8 of Fig 5; 0078; 0081; 0084-88; 0103-05 ] . It would have been obvious to modify the sensor of Murakami to include some transistors in a well as the opening area can be increased up to the size of the pixel cell, thus allowing an increase in photoelectric conversion efficiency. Regarding Claim 15, Murakami teaches ranging system [ Fig 16 ] comprising: a lighting device that emits irradiation light [ #211 of Fig 16; 0132-37 ] ; and a sensor element that detects reflected light with respect to the irradiation light [ #203 of Fig 16; 0132-37 ] , wherein the sensor element includes: a sensor substrate in which a single photon avalanche diode (SPAD) is provided on a semiconductor substrate for each pixel [ #22, #31 of Fig 3, 4; 0053-58; 0062-81 ] ; a logic substrate laminated on the sensor substrate and provided with a logic circuit [ #33 of Fig 3, 4; 0053-58; 0062-81; 0090-0100 ] ; and a plurality of transistors used to output a signal according to a cathode voltage or an anode voltage of the SPAD [ #23, #24 of Fig 3, 4; 0053-58; 0062-81; 0090-0100 ] , and at least some of the plurality of the transistors are provided in a well formed in the semiconductor substrate of the sensor substrate [#3, #4, #8, #41 of Fig 5; 0078; 0081; 0084-88; 0103-05 ] . It would have been obvious to modify the sensor of Murakami to include some transistors in a well as the opening area can be increased up to the size of the pixel cell, thus allowing an increase in photoelectric conversion efficiency. Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murakami ( US 2022 / 0262970 - also published as JP 2021/027084 ) in view of Kasuga ( US 2020 / 0106982 – also published as WO 2018/216400 ) , as applied to claim 1 above, and further in view of Takatsuka ( US 2021 / 0183930 – also published as JP 2019/114728). Regarding Claim 11, Murakami does not explicitly teach – but Takatsuka does teach wherein an anode region that applies an anode voltage to the pixel is disposed on a back surface side of the semiconductor substrate [Fig 15; 0134-39]. It would have been obvious to modify the element of Murakami to include a pixel on the back of a semiconductor substrate as the route wiring of the anode contact performs a light-shielding function, and a common anode can be dropped with respect to the SPADs of pixels . Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murakami ( US 2022 / 0262970 - also published as JP 2021/027084 ) in view of Kasuga ( US 2020 / 0106982 – also published as WO 2018/216400 ) , as applied to claim 1 above, and further in view of Nishino ( US 2021 / 0325538 – also published as JP 2020/034521 ). Regarding Claim 14, Murakami also teaches a first PMOS transistor for quenching or recharging, a second PMOS transistor constituting an inverter, and the first PMOS transistor, and the second PMOS transistor are individually disposed in four of the pixels [#22, #24 of Fig 3, 4; 0053-58; 0062-81; 0090-0100 ] . Murakami does not explicitly teach – but Nishino does teach wherein the transistors provided in the sensor substrate are a first NMOS transistor that deactivates the SPAD, and a second NMOS transistor and the first NMOS transistor, the second NMOS transistor, are individually disposed in four of the pixels [0061-73; Fig 3]. It would have been obvious to modify the sensor of Murakami to include an inverter and 2 NMOS and PMOS transistors so that a transistor performs passive quench by functioning as a quenching resistor , while a drain is connected to the cathode, the input terminal of the inverter, and the drain of the transistor , thus allowing the power supply voltage to be also supplied to the cathode of the SPAD . Claim Objections Claims 2-10, and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JAMES R HULKA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-7553 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-R: 9am-6pm, F: 10am-2pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Helal Algahaim can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712705227 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT JAMES R. HULKA Primary Examiner Art Unit 3645 /JAMES R HULKA/ Primary Examiner, Art Unit 3645