Prosecution Insights
Last updated: July 17, 2026
Application No. 18/550,628

MEMS RESONATOR AND MEMS RESONATOR PROCESSING METHOD

Final Rejection §103
Filed
Sep 14, 2023
Priority
Mar 17, 2021 — CN 202110285274.X +1 more
Examiner
PERKINS, THEODORE L
Art Unit
2834
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Huawei Technologies Co., Ltd.
OA Round
2 (Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
62 granted / 84 resolved
+5.8% vs TC avg
Strong +22% interview lift
Without
With
+22.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
28 currently pending
Career history
112
Total Applications
across all art units

Statute-Specific Performance

§103
89.2%
+49.2% vs TC avg
§102
4.0%
-36.0% vs TC avg
§112
6.7%
-33.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 84 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments, page 6 whole page to page 8 lines 1 – 12, filed 02/12/2026 have been fully considered but they are not persuasive. Applicant argues that Wu et al. does not disclose the amended claim limitation, “the conducting layer is connected to the first conducting structure that is outside the barrier layer through the barrier layer” because Wu et al.’s conducting layer (germanium layer 508) is connected directly to the first conducting structure (re-doped polysilicon 512) that is outside the barrier layer (cover silicon wafer 510) and does not connect through the barrier layer. However, in Wu et al.’s Fig. 5 – 2, the re-doped polysilicon 512 is shown to be both outside and extended through the cover silicon wafer 510, such that the germanium layer 508 is connected to the re-doped polysilicon 512 that is outside the cover silicon wafer 510 through the cover silicon wafer 510. Applicant's arguments, page 8 lines 13 – 31 to page 9 lines 1 – 10, filed 02/12/2026 have been fully considered but they are not persuasive. Applicant argues that Chodavarapu et al. does not disclose or suggest that the harmonic oscillator generates an offset in a fixed direction that is a direction of the capacitor. However, Chodavarapu et al. Para [0085] lines 6 – 10 and Fig. 4 disclose that a direct current bias voltage is provided to a harmonic oscillator (square resonator disk 410) using a functional electrode (bias electrodes 450) creating a tunable, direct current bias voltage-controlled capacitor. This enables the square resonator disk 410 to generate an offset in a fixed direction between the bias electrodes 450 such that the resonance frequency changes, based on the direct current bias voltage-controlled capacitor. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 20 – 25, 27, 32 – 35, and 37 – 39 are rejected under 35 U.S.C. 103 as being unpatentable over Inaba et al. in view of Wu et al. (CN 110289823 A) and further in view of Kawai et al. Regarding Claim 20, Inaba et al. discloses a micro electro mechanical system (MEMS) resonator (1) (below in annotated Inaba et al. Fig. 1), comprising: a substrate (21) (below in annotated Inaba et al. Fig. 1), a barrier layer (wiring layer 65, surface protective film 66, and a sealing layer 67) (below in annotated Inaba et al. Fig. 1), a conducting layer (24) (below in annotated Inaba et al. Fig. 1), a dielectric isolation layer (62) (below in annotated Inaba et al. Fig. 1), a harmonic oscillator (vibrating element 5) (below in annotated Inaba et al. Fig. 1 and Fig. 2A), the substrate and the barrier layer are combined to form a cavity (S) (below in annotated Inaba et al. Fig. 1), a junction between the substrate and the barrier layer comprises the conducting layer (below in annotated Inaba et al. Fig. 1), PNG media_image1.png 289 484 media_image1.png Greyscale and the dielectric isolation layer is configured to isolate electrical connection between the conducting layer and the barrier layer (below in annotated Inaba et al. Fig. 1). Inaba et al. does not disclose: a first electrical isolation structure, and a first conducting structure, wherein: the harmonic oscillator is connected to the conducting layer and is suspended in the cavity; the conducting layer is connected to the first conducting structure that is outside the barrier layer through the barrier layer, and the first electrical isolation structure is comprised between the first conducting structure and the barrier layer; and the barrier layer and the dielectric isolation layer are configured to isolate the first electrical isolation structure from the cavity. Wu et al. discloses: a first electrical isolation structure (first portion of silicon oxide 513) (below in annotated Wu et al. Fig. 5 -1), and a first conducting structure (first portion of heavily doped polycrystalline silicon 512) (below in annotated Wu et al. Fig. 5 – 1), wherein: the conducting layer (germanium layer 508) is connected to the first conducting structure that is outside the barrier layer through the barrier layer (cover plate silicon wafer 10) (below in annotated Wu et al. Fig. 5 – 2), PNG media_image2.png 432 319 media_image2.png Greyscale and the first electrical isolation structure is comprised between the first conducting structure and the barrier layer (below in annotated Wu et al. Fig. 5 – 1). Inaba et al. and Wu et al. discloses: and the barrier layer and the dielectric isolation layer (of annotated Inaba et al. Fig. 1 shown above) are configured to isolate the first electrical isolation structure (of annotated Wu et al. Fig. 5 – 1 shown above) from the cavity (of annotated Inaba et al. Fig. 1 shown above). Kawai et al. discloses: the harmonic oscillator (120) is connected to the conducting layer (236A – 236D) and is suspended in the cavity (below in annotated Kawai et al. Fig. 7). PNG media_image3.png 636 424 media_image3.png Greyscale Inaba et al., Wu et al., and Kawai et al. disclose resonators therefore, Wu et al., and Kawai et al. constitute prior art. Wu et al. discloses a micromechanical resonator having a conducting layer, a barrier layer, a first electrical isolation structure and a first conducting structure and Kawai et al. discloses a microelectromechanical resonator having a vibrating element connected to a conducting layer and being suspended in the cavity. It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have a first electrical isolation structure, and a first conducting structure, wherein: the conducting layer is connected to the first conducting structure that is outside the barrier layer through the barrier layer, and the first electrical isolation structure is comprised between the first conducting structure and the barrier layer of Inaba et al., and the barrier layer and the dielectric isolation layer are configured to isolate the first electrical isolation structure from the cavity of structurally disclosed Inaba et al. and Wu et al., and the harmonic oscillator is connected to the conducting layer and is suspended in the cavity of Kawai et al. for the purpose of 1) preventing high voltages to occur from within the resonator and 2) amplify oscillations of the harmonic oscillator. Regarding Claim 21, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 20, wherein: the barrier layer comprises a first barrier layer (wiring layer 65) and a second barrier layer (sealing layer 67 of Inaba et al.) (above in annotated Inaba et al. 1); breather holes (652 of Inaba et al.) are disposed on the first barrier layer (above in annotated Inaba et al. 1); and the second barrier layer is configured to seal the breather holes to seal the harmonic oscillator in the cavity (above in annotated Inaba et al. 1). Regarding Claim 22, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 21, wherein a material of the second barrier layer is polycrystalline silicon or amorphous silicon (Inaba et al. Para [0121] whole paragraph discloses the material of the sealing layer 67 can be a silicon oxide film which is known to be an amorphous silicon). Regarding Claim 23, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 21. Inaba et al., Wu et al., and Kawai et al. do not disclose: wherein a material of the first barrier layer is different from a material of the first electrical isolation structure. Inaba et al. and Wu et al. structurally disclose: wherein a material of the first barrier layer (of Inaba et al. Para [0066] lines 2 – 4 discloses the wiring layer 65 is composed of aluminum) is different from a material of the first electrical isolation structure (of Wu et al. Para [0081] first sentence discloses a silicon oxide layer 513). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein a material of the first barrier layer is different from a material of the first electrical isolation structure of structurally disclosed Inaba et al. and Wu et al. for the purpose of enabling mechanical vibration and electrical connections. Regarding Claim 24, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 21, wherein a material of the second barrier layer is the same as a material of the first barrier layer (Inaba et al. Para [0121] whole paragraph discloses the material of the wiring layer 65 and sealing layer 67 can be composed of a metal such as aluminum). Regarding Claim 25, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 20, wherein: the harmonic oscillator comprises an upper electrode layer (53) (Inaba et al. Fig. 1), and a lower electrode layer (51) (Inaba et al. Fig. 1). Inaba et al. does not disclose: a piezoelectric layer, the piezoelectric layer is located between the upper electrode layer and the lower electrode layer; and the dielectric isolation layer covers the upper electrode layer and the piezoelectric layer. Wu et al. discloses: a piezoelectric layer (505) (Wu et al. Fig. 5 – 1), the piezoelectric layer is located between the upper electrode layer (506) and the lower electrode layer (504) (Wu et al. Fig. 5 – 1). Kawai et al. discloses: the dielectric isolation layer (protective film 235) covers the upper electrode layer (E2) and the piezoelectric layer (F3) (Kawai et al. Fig. 5C). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein a piezoelectric layer is located between the upper electrode layer and the lower electrode layer of Wu et al. the dielectric isolation layer covers the upper electrode layer and the piezoelectric layer of Kawai et al. for the purpose of 1) converting mechanical energy into electrical energy for the MEMS resonator and 2) preventing galvanic corrosion to the upper electrode and the piezoelectric layer. Regarding Claim 27, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 20. Inaba et al. and Wu et al. do not disclose: wherein a thickness of the dielectric isolation layer is 0.01 µm to 2 µm. Kawai et al. discloses: wherein a thickness of the dielectric isolation layer is 0.01 µm to 2 µm (Kawai et al. Para [0093] last sentence discloses the protective film 235 can have a thickness of 0.2 µm). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein a thickness of the dielectric isolation layer is 0.01 µm to 2 µm of Kawai et al. for the purpose of controlling impedance, signal integrity, and flexibility in the MEMS resonator. Regarding Claim 32, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 20. Inaba et al. does not disclose: wherein the MEMS resonator further comprises a support beam; and the harmonic oscillator is connected to the conducting layer through the support beam and is suspended in the cavity. Wu et al. discloses: wherein the MEMS resonator further comprises a support beam (32) (Wu et al. Fig. 3 – 1). Kawai et al. discloses: the harmonic oscillator is connected to the conducting layer through the support beam (135A – 135D) and is suspended in the cavity (space inside holding portion 140) (Kawai et al. Fig. 7). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the MEMS resonator further comprises a support beam of Wu et al. and the harmonic oscillator is connected to the conducting layer through the support beam and is suspended in the cavity of Kawai et al. for the purpose of securing the harmonic oscillator in the MEMS resonator upon mechanical vibration. Regarding Claim 33, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 20. Inaba et al. and Kawai et al. does not disclose: wherein the MEMS resonator further comprises a protective layer above the barrier layer. Wu et al. discloses: wherein the MEMS resonator further comprises a protective layer (silicon oxide 511) above the barrier layer (Wu et al. Fig. 5 – 1). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the MEMS resonator further comprises a protective layer above the barrier layer of Wu et al. for the purpose of protecting the barrier layer from external surface impact and exposure. Regarding Claim 34, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 33. Inaba et al. and Kawai et al. do not disclose: an electrical through-hole is disposed on the protective layer; an electrode pad is deposited on the electrical through-hole; and the electrode pad is connected to the first conducting structure. Wu et al. discloses: wherein an electrical through-hole is disposed on the protective layer (below in annotated Wu et al. Fig. 5 – 1); an electrode pad (metal pad 514) is deposited on the electrical through-hole (Wu et al. Fig. 5 – 1); and the electrode pad is connected to the first conducting structure (Wu et al. Fig. 5 – 1). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein an electrical through-hole is disposed on the protective layer; an electrode pad is deposited on the electrical through-hole; and the electrode pad is connected to the first conducting structure of Wu et al. for the purpose of facilitating transfer of electrical signals from the MEMs resonator to external circuits. Regarding Claim 35, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 20, wherein a surface of the substrate comprises a silicon oxide layer (22) (Inaba et al. Fig. 1). Regarding Claim 37, Inaba et al. discloses an electronic device (personal computer 1100) (Inaba et al. Fig. 9), comprising a micro electro mechanical system (MEMS) resonator (1) (above in annotated Inaba et al. Fig. 1), comprising: a substrate (21) (above in annotated Inaba et al. Fig. 1), a barrier layer (wiring layer 65, surface protective film 66, and a sealing layer 67) (above in annotated Inaba et al. Fig. 1), a conducting layer (24) (above in annotated Inaba et al. Fig. 1), a dielectric isolation layer (62) (above in annotated Inaba et al. Fig. 1), a harmonic oscillator (vibrating element 5) (above in annotated Inaba et al. Fig. 1), the substrate and the barrier layer are combined to form a cavity (S) (above in annotated Inaba et al. Fig. 1), a junction between the substrate and the barrier layer comprises the conducting layer (above in annotated Inaba et al. Fig. 1), and the dielectric isolation layer is configured to isolate electrical connection between the conducting layer and the barrier layer (above in annotated Inaba et al. Fig. 1). Inaba et al. does not disclose: a first electrical isolation structure, and a first conducting structure, wherein: the harmonic oscillator is connected to the conducting layer and is suspended in the cavity; the conducting layer is connected to the first conducting structure that is outside the barrier layer through the barrier layer, and the first electrical isolation structure is comprised between the first conducting structure and the barrier layer; and the barrier layer and the dielectric isolation layer are configured to isolate the first electrical isolation structure from the cavity. Wu et al. discloses: a first electrical isolation structure (first portion of silicon oxide 513) (above in annotated Wu et al. Fig. 5 -1), and a first conducting structure (first portion of heavily doped polycrystalline silicon 512) (above in annotated Wu et al. Fig. 5 – 1), wherein: the conducting layer (germanium layer 508) is connected to the first conducting structure that is outside the barrier layer through the barrier layer (cover plate silicon wafer 10) (above in annotated Wu et al. Fig. 5 – 2), and the first electrical isolation structure is comprised between the first conducting structure and the barrier layer (above in annotated Wu et al. Fig. 5 – 1). Inaba et al. and Wu et al. discloses: and the barrier layer and the dielectric isolation layer (of annotated Inaba et al. Fig. 1 shown above) are configured to isolate the first electrical isolation structure (of annotated Wu et al. Fig. 5 – 1 shown above) from the cavity (of annotated Inaba et al. Fig. 1 shown above). Kawai et al. discloses: the harmonic oscillator (120) is connected to the conducting layer (236A – 236D) and is suspended in the cavity (above in annotated Kawai et al. Fig. 7). Inaba et al., Wu et al., and Kawai et al. disclose resonators therefore, Wu et al., and Kawai et al. constitute prior art. Wu et al. discloses a micromechanical resonator having a conducting layer, a barrier layer, a first electrical isolation structure and a first conducting structure and Kawai et al. discloses a microelectromechanical resonator having a vibrating element connected to a conducting layer and being suspended in the cavity. It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have a first electrical isolation structure, and a first conducting structure, wherein: the conducting layer is connected to the first conducting structure that is outside the barrier layer through the barrier layer, and the first electrical isolation structure is comprised between the first conducting structure and the barrier layer of Inaba et al., and the barrier layer and the dielectric isolation layer are configured to isolate the first electrical isolation structure from the cavity of structurally disclosed Inaba et al. and Wu et al., and the harmonic oscillator is connected to the conducting layer and is suspended in the cavity of Kawai et al. for the purpose of 1) preventing high voltages to occur from within the resonator and 2) amplify oscillations of the harmonic oscillator. Regarding Claim 38, Inaba et al., Wu et al., and Kawai et al. discloses the electronic device of claim 37, wherein: the barrier layer comprises a first barrier layer (wiring layer 65) and a second barrier layer ( sealing layer 67) (above in annotated Inaba et al. 1); breather holes (652) are disposed on the first barrier layer (above in annotated Inaba et al. 1); and the second barrier layer is configured to seal the breather holes to seal the harmonic oscillator in the cavity (above in annotated Inaba et al. 1). Regarding Claim 39, Inaba et al., Wu et al., and Kawai et al. discloses the electronic device of claim 38, wherein a material of the second barrier layer is polycrystalline silicon or amorphous silicon (Inaba et al. Para [0121] whole paragraph discloses the material of the sealing layer 67 can be a silicon oxide film which is known to be an amorphous silicon). Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Inaba et al. in view of Wu et al., Kawai et al., and further in view of Kubena et al. Regarding Claim 26, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 20. Inaba et al., Wu et al., and Kawai et al. do not disclose: wherein a material of the dielectric isolation layer is aluminum oxide Al2O3. Kubena et al. discloses: wherein a material of the dielectric isolation layer is aluminum oxide Al2O3 (Kubena et al. c. 8, l. 11 – 13 discloses the dielectric film can be aluminum oxide). Inaba et al., Wu et al., Kawai et al., Kubena et al. discloses resonators therefore, Kubena et al. constitutes as prior art. Kubena et al. discloses a dielectric substrate that is composed of aluminum oxide. It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein a material of the dielectric isolation layer is aluminum oxide Al2O3 of Kubena et al. for the purpose of acting as an electrical insulator and protective layer for the MEMS resonator. Claims 28 – 31 are rejected under 35 U.S.C. 103 as being unpatentable over Inaba et al. in view of Wu et al., Kawai et al., and further in view of Chodavarapu et al. Regarding Claim 28, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 20. Inaba et al. does not disclose: wherein the MEMS resonator further comprises a functional electrode; the functional electrode and the harmonic oscillator form a capacitor; and in response to at least that a direct current bias voltage is applied to the functional electrode, the harmonic oscillator generates an offset in a fixed direction, wherein the fixed direction is a direction of the capacitor. Wu et al. discloses: wherein the MEMS resonator further comprises a functional electrode (metal pad 514) (Wu et al. Fig. 5 – 1). Kawai et al. discloses: the functional electrode (driving electrodes E4, E5) and the harmonic oscillator form a capacitor (see below in annotated Kawai et al. Fig. 5). Chodavarapu et al. discloses: and in response to at least that a direct current bias voltage is applied to the functional electrode (bias electrode 450), the harmonic oscillator (square resonating disk 410) generates an offset in a fixed direction, wherein the fixed direction is a direction of the capacitor (Chodavarapu et al. Para [0085] lines 6 – 10 discloses the resonating mass/square resonating disk 410 can have its frequency tuned by way of a DC bias voltage using a fifth electrode/bias electrode 450, which can create an offset in motion of the capacitor, which is formed between the square resonating disk 410 and the bias electrodes 450). PNG media_image4.png 478 442 media_image4.png Greyscale Inaba et al., Wu et al., Kawai et al., and Chodavarapu et al. disclose resonators, therefore Chodavarapu et al. constitute as prior art. Chodavarapu et al. discloses a MEMS resonator equipped with an electrode that utilizes DC bias voltage to frequency tune a resonating mass. It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the MEMS resonator further comprises a functional electrode of Wu et al., the functional electrode and the harmonic oscillator form a capacitor of Kawai et al. and in response to at least that a direct current bias voltage is applied to the functional electrode, the harmonic oscillator generates an offset in a fixed direction, wherein the fixed direction is a direction of the capacitor of Chodavarapu et al. for the purpose of 1) storing electrical energy, and 2) enhancing performance and reduce noise in the MEMS resonator. Regarding Claim 29, Inaba et al., Wu et al., Kawai et al., and Chodavarapu et al. disclose the MEMS resonator of claim 28. Inaba et al., Wu et al., and Chodavarapu et al. do not disclose: wherein the functional electrode comprises a first functional electrode and a second functional electrode; the first functional electrode and the harmonic oscillator form a first capacitor; the second functional electrode and the harmonic oscillator form a second capacitor; and the first capacitor and the second capacitor are distributed symmetric about the harmonic oscillator. Kawai et al. discloses: wherein the functional electrode comprises a first functional electrode (E4) and a second functional electrode (E5) (Kawai et al. Fig. 12); the first functional electrode and the harmonic oscillator form a first capacitor (see above in annotated Kawai et al. Fig. 12); the second functional electrode and the harmonic oscillator form a second capacitor (see above in annotated Kawai et al. Fig. 12); and the first capacitor and the second capacitor are distributed symmetric about the harmonic oscillator (see above in annotated Kawai et al. Fig. 12). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the functional electrode comprises a first functional electrode and a second functional electrode; the first functional electrode and the harmonic oscillator form a first capacitor; the second functional electrode and the harmonic oscillator form a second capacitor; and the first capacitor and the second capacitor are distributed symmetric about the harmonic oscillator of Kawai et al. for the purpose of storing electrical energy on both sides of the harmonic oscillator for the MEMS resonator. Regarding Claim 30, Inaba et al., Wu et al., Kawai et al., and Chodavarapu et al. discloses the MEMS resonator of claim 28. Inaba et al., Kawai et al., and Chodavarapu et al. do not disclose: wherein the functional electrode is connected to a second conducting structure that is inside the barrier layer; a second electrical isolation structure is comprised between the second conducting structure and the barrier layer; and the barrier layer and the dielectric isolation layer are configured to isolate the second electrical isolation structure from the cavity. Wu et al. discloses: wherein the functional electrode is connected to a second conducting structure that is inside the barrier layer (see below in annotated Wu et al. Fig. 5 – 1); a second electrical isolation structure is comprised between the second conducting structure and the barrier layer (see below in annotated Wu et al. Fig. 5 – 1). Inaba et al. and Wu et al. discloses: and the barrier layer and the dielectric isolation layer (of annotated Inaba et al. Fig. 1 shown above) are configured to isolate the second electrical isolation structure (of annotated Wu et al. Fig. 5 – 1 shown below) from the cavity (of annotated Inaba et al. Fig. 1 shown above). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the functional electrode is connected to a second conducting structure that is inside the barrier layer and a second electrical isolation structure is comprised between the second conducting structure and the barrier layer of Wu et al., and the barrier layer and the dielectric isolation layer are configured to isolate the second electrical isolation structure from the cavity of structurally disclosed Inaba et al. and Wu et al. for the purpose of preventing high voltage within the MEMS resonator. Regarding Claim 31, Inaba et al., Wu et al., Kawai et al., and Chodavarapu et al. discloses the MEMS resonator of claim 28. Inaba et al., Kawai et al., and Chodavarapu et al. do not disclose: wherein in response to at least that an alternating current voltage is applied to the functional electrode, the harmonic oscillator vibrates based on the alternating current voltage. Wu et al. discloses: wherein in response to at least that an alternating current voltage is applied to the functional electrode (driving electrode) (Wu et al. Para [0071] first sentence). Inaba et al. and Wu et al. structurally disclose: the harmonic oscillator (of Inaba et al. Fig. 1) vibrates based on the alternating current voltage (of Wu et al. Para [0071] first sentence). It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein in response to at least that an alternating current voltage is applied to the functional electrode of Wu et al. and the harmonic oscillator vibrates based on the alternating current voltage of structurally disclosed Inaba et al. and Wu et al. for the purpose of improving performance and stability from within the MEMS resonator. Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Inaba et al. in view of Wu et al., Kawai et al., and further in view of Allegato et al. Regarding Claim 36, Inaba et al., Wu et al., and Kawai et al. discloses the MEMS resonator of claim 21. Inaba et al., Wu et al., and Kawai et al. do not disclose: wherein a processing temperature of the second barrier layer is greater than 500 degrees (Celsius). Allegato et al. discloses: wherein a processing temperature of the second barrier layer (6) is greater than 500 degrees (Celsius) (Allegato et al. Para [0028] lines 3 – 6 discloses the insulating layer 6 is formed from between 650°C to 750°C). Inaba et al., Wu et al., Kawai et al., Allegato et al. discloses insulating layers therefore, Allegato et al. constitutes as prior art. Allegato et al. discloses an oscillator device having an insulating layer of tetraethyl orthosilicate formed at a temperature of 650°C to 750°C. It would be obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein a processing temperature of the second barrier layer is greater than 500 degrees (Celsius) of Allegato et al. for the purpose of enhancing the durability of the second barrier layer of the MEMS resonator. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THEODORE L PERKINS whose telephone number is (703)756-4629. The examiner can normally be reached 8:00am- 17:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christopher Koehler can be reached on (571) 272-3560. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THEODORE L PERKINS/Examiner, Art Unit 2834 /TERRANCE L KENERLY/Primary Examiner, Art Unit 2834
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Prosecution Timeline

Sep 14, 2023
Application Filed
Nov 26, 2025
Non-Final Rejection mailed — §103
Feb 12, 2026
Response Filed
Jun 09, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
96%
With Interview (+22.2%)
2y 7m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
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