DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are subject to examination and rejected.
Claim Objections
Claim 1 is objected to because of the following informalities: The recited ACRONYMS such as PHY must be defined within the claims. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites a first network node performing the steps of configuring PHY circuitries of a reference node and a nominated node to initiate sending a measurement pulse and to determine a reference PHY time delay and a nominated PHY time delay. Claim 1 further recites the steps of initiating sending multiple measurement pulses, detecting response pulses in response to the measurement pulses, and determining a network topology using the response pulses. The former steps of configuring, initiating, and determining focus on determining a reference PHY time delay and a nominated PHY time delay. The latter steps of initiating, detecting and determining focus on determining a network topology. However, the claim fails to clearly specify how the determined a reference PHY time delay and a nominated PHY time delay are related to the determination of the network topology. This kind of discrepancy renders the claims indefinite because the claims include elements not actually related, thereby rendering the scope of the claim unascertainable. Appropriate correction is required.
Claim 1 recites the limitation “the network node”. There is insufficient antecedent basis for this limitation in the claims. Examiner suggests to use “the first network node” for the consistency. The term “the network node” does not have a proper antecedent basis in the referenced claim 1. Appropriate correction is required.
Claim 1 recites the limitations “sending a measurement pulse on the reference node TX/RX loop” as well as “sending a measurement pulse on the nominated node TX/RX loop” respectively. It is not clear if “a measurement pulse” sent to the reference node TX/RX loop is the same feature of “a measurement pulse” sent to the nominated node TX/RX loop. If these limitations indicate the same features, the latter one should be amended with sufficient antecedent basis. If these limitations are different, then the limitations should be amended to be distinguished each other. Appropriate correction is required.
Claim 9 recites a reference network node performing the steps of configuring PHY circuitry of the reference node and determining a PHY time delay. Claim 9 further recites the steps of sending a command to enter a discovery mode, sending multiple measurement pulses, returning response pulses and determining a network topology using the response pulses. The former steps of configuring and determining focus on determining a PHY time delay of the reference node. The latter steps of sending, sending, returning and determining focus on determining a network topology. However, the claim fails to clearly specify how the determined a PHY time delay is related to the determination of the network topology. This kind of discrepancy renders the claims indefinite because the claims include elements not actually related, thereby rendering the scope of the claim unascertainable. Appropriate correction is required.
Claim 9 recites the limitations “one or more measurement pulses” as well as “multiple measurement pulses” respectively. It is not clear if “one or more measurement pulses” are the same features of “multiple measurement pulses”. If these limitations indicate the same features, the latter one should be amended with sufficient antecedent basis. If these limitations are different, then the limitations should be amended to be distinguished each other. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pearce (US PGPub 2002/0110155).
Regarding claim 1, Pearce teaches a multi-drop network including multiple network nodes (Pearce, see paragraph 0030, first and second nodes in communication with the central controller), the network including:
a first network node (Pearce, see paragraph 0030, This system for motion control includes a central controller) including:
physical layer (PHY) circuitry for connecting the network node to a shared network link of the multi-drop network (Pearce, see paragraph 0030, first and second nodes in communication with the central controller); and
processing circuitry operatively coupled to the PHY circuitry (Pearce, see paragraph 0070, the most common implementation of a motion control system is a “motion controller” that includes a program running on a central processor unit) and configured to:
designate a reference node and a nominated node from among the multiple network nodes (Pearce, see paragraph 0097, The discovery phase 60 describes operations whereby the nodes (such as, e.g., node 32 and 24 of FIG. 3) are discovered and enumerated (e.g., assigned address and other network parameters) by the master 36);
configure PHY circuitry of the reference node into a reference node transmit/receive (TX/RX) loop internal to the reference node that includes a PHY transceiver of the reference node (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT);
initiate sending a measurement pulse on the reference node TX/RX loop and determine a reference PHY time delay using a count of the reference node TX/RX loops completed during a time duration (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT);
configure PHY circuitry of the nominated node PHY circuitry into a nominated node transmit/receive (TX/RX) loop internal to the nominated node that includes a PHY transceiver of the nominated node (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT);
initiate sending a measurement pulse on the nominated node TX/RX loop and determine a nominated PHY time delay using a count of the nominated node TX/RX loops completed during a time duration (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT);
initiate sending multiple measurement pulses from the reference node to the nominated node via the shared network link (Pearce, see paragraph 0101, The delay between the transmission of the MQT the master 36 and the reception of the AAT by the slave 34 is repeatable to an uncertainty associated with the physical layer clocks. Hence by timing the delay between transmission of the MQT and reception of the AAT and then subtracting the known internal delay of the slave 34 when transmitting the MQT, the propagation delay caused by the cabling and the repeaters in any intervening nodes may be computed by automated means);
detect response pulses received via the shared network link in response to the measurement pulses (Pearce, see paragraph 0101, , this known internal delay is then used to calculate a forward path time correction factor (FPTC) for the particular node (such as node 32 in FIG. 8 and 9). After a determination of the FPTC, the master then issues a MAT (master assignment telegram, as illustrated in FIG. 10) from its P0 port. The MAT thus assigns the lowest available network address to the slave 34 and sets the FPTC for slave 34. The slave 34 responds to the MAT with a further AAT (as illustrated in FIG. 11) to confirm that the address assigned by the MAT has been accepted by the slave 32. In FIG. 11 and in all further illustrations, slave 34 will be denoted as slave 34E to indicate that it has been enumerated); and
determine a network topology of the reference node and the nominated node using the response pulses (Pearce, see paragraph 0101, The delay between the transmission of the MQT the master 36 and the reception of the AAT by the slave 34 is repeatable to an uncertainty associated with the physical layer clocks).
Regarding claim 2, Pearce teaches wherein the processing circuitry of the network node is further configured to measure the delay of the nominated node by counting the number of pulses seen during a fixed time interval while the nominated node is looping a pulse (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT).
Regarding claim 3, Pearce teaches wherein the PHY circuitry of the reference node and the nominated node includes a delay circuit to cause the PHY time delay to be longer than a pulse width of the measurement pulse (Pearce, see paragraph 0101, The delay between the transmission of the MQT the master 36 and the reception of the AAT by the slave 34 is repeatable to an uncertainty associated with the physical layer clocks. Hence by timing the delay between transmission of the MQT and reception of the AAT and then subtracting the known internal delay of the slave 34 when transmitting the MQT, the propagation delay caused by the cabling and the repeaters in any intervening nodes may be computed by automated means).
Regarding claim 4, Pearce teaches wherein the reference node TX/RX loop and the nominated node TX/RX loop include the PHY transceiver, the delay circuit, and board interface network (BIN) circuitry that connects the respective PHY transceiver to the shared network link (Pearce, see paragraph 0101, The delay between the transmission of the MQT the master 36 and the reception of the AAT by the slave 34 is repeatable to an uncertainty associated with the physical layer clocks. Hence by timing the delay between transmission of the MQT and reception of the AAT and then subtracting the known internal delay of the slave 34 when transmitting the MQT, the propagation delay caused by the cabling and the repeaters in any intervening nodes may be computed by automated means).
Regarding claim 5, Pearce teaches wherein the PHY circuitry of the reference node and the nominated node includes a delay circuit (Pearce, see paragraph 0031, A node configured to be in communication with a central controller over a data network can thus include a delay correction memory configured to store a delay correction signal related to a propagation delay between the central controller and the node over the data network), and the processing circuitry of the network node is configured to:
configure the PHY circuitry into an internal transmit/receive (TX/RX) loop that includes a PHY transceiver and the delay circuit (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT);
calculate a PHY time delay (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT); and
adjust the delay circuit to set the PHY time delay to a predetermined PHY time delay (Pearce, see paragraph 0117, In one embodiment for operation with a complete network ring topology, since the MST is a continuously running master synchronization signal, each slave node can use its own FPTC as an offset when adjusting its internal timing).
Regarding claim 6, Pearce teaches including:
a listening node separate from the reference node and the nominated node (Pearce, see paragraph 0031, A node configured to be in communication with a central controller over a data network can thus include a delay correction memory configured to store a delay correction signal related to a propagation delay between the central controller and the node over the data network); and
wherein the processing circuitry of the first network node is configured to:
detect another response pulse from the listening node (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT); and
determine relative position of the nominated node and listening node to the reference node (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT).
Regarding claim 7, Pearce teaches wherein the listening node include processing circuitry configured to:
detect the measurement pulses from the reference node (Pearce, see paragraph 0031, A node configured to be in communication with a central controller over a data network can thus include a delay correction memory configured to store a delay correction signal related to a propagation delay between the central controller and the node over the data network);
detect the response pulses from the nominated node (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT); and
calculate a time delay between the nominated node and the listening node in response to detecting the measurement pulses and the response pulses (Pearce, see paragraph 0101, The known internal delay of the slave 34 has two elements. The first arises due to the FIFO's of the slave 34. The second is the time taken for the node to automatically respond to the MQT with an AAT).
Regarding claim 8, Pearce teaches wherein the processing circuitry of the listening node is configured to determine relative position of the nominated node and listening node to the reference node (Pearce, see paragraph 0121, the rate at which position is updated in a motion control system is the servo cycle clock rate. The motion trajectory for each axis is determined by the motion planning function of the master 36, and at each tick of the servo clock the next position demand, representing the next point on the motion trajectory, is presented to the drive at a slave node).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao (US PGPub 2016/0043823) in view of Huszak (US PGPub 2023/0029130).
Regarding claim 9, Zhao teaches a computer-readable storage medium containing instructions, which when performed by processing circuitry of a reference network node of a multi-drop network (Zhao, see figure 3, an ethernet node), cause the reference node to perform actions including:
configuring PHY circuitry of a reference node of the network into a transmit/receive (TX/RX) loop internal to the reference node (Zhao, see paragraph 0054, the physical layer delay acquiring unit 11 specifically includes: a fixed delay acquiring unit 110, a dynamic precise delay acquiring unit 111, a dynamic coarse-grained delay acquiring unit 112, and a physical layer delay acquiring subunit 113);
determining a PHY time delay of the reference node by sending one or more measurement pulses over the TX/RX loop and counting the number of TX/RX loops completed during a time duration (Zhao, see paragraphs 0054 and 0063, where the fixed delay acquiring unit 110 is configured to acquire fixed delay information generated by a related module in the physical layer transceiver unit 10; the dynamic precise delay acquiring unit 111 is configured to acquire dynamic precise delay information generated by a related module in the physical layer transceiver unit 10; the dynamic coarse-grained delay acquiring unit 112 is configured to acquire dynamic coarse-grained delay information generated by a related module in the physical layer transceiver unit 10. delay information of a last data packet transmitted prior to the PTP data packet, or information about an average delay of all data packets transmitted prior to the PTP data packet).
Zhao teaches the above yet fails to teach sending, by the reference node to a nominated node of the network, a command for the nominated node to enter a discovery mode; sending multiple measurement pulses to the nominated node from the reference node; returning response pulses from the nominated node to the reference node in response to the measurement pulses; and determining, by the reference node, a network topology of the reference node and the nominated node using the response pulses.
Then Huszak teaches sending, by the reference node to a nominated node of the network, a command for the nominated node to enter a discovery mode (Huszak, see paragraph 0053, the segment coordinator sets all bus nodes 102, 104, 106 to a responsive state commanding them to reply a subsequent find request message);
sending multiple measurement pulses to the nominated node from the reference node (Huszak, see paragraph 0042, At 202 the measuring node 100 is configured to transmit at least one signal to the bus node 102 via the multi-drop communication bus 108);
returning response pulses from the nominated node to the reference node in response to the measurement pulses (Huszak, see paragraphs 0043 and 0044, At 204 the measuring node 100 is configured to receive from the bus node 102 at least one loopback response signal caused by the transmitted at least one signal. At 206 the measuring node 100 is configured to measure a roundtrip delay between the at least one signal and the loopback response signal); and
determining, by the reference node, a network topology of the reference node and the nominated node using the response pulses (Huszak, see paragraph 0050, This makes it possible to even determine a layout or a topology of the communication system by means of the inventive solution).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zhao with Determination of a sequence of bus nodes in a multi-drop communication bus of Huszak, because doing so would make Zhao more efficient in determining a sequence of bus nodes in a multi-drop communication bus (Huszak, see paragraph 0001).
Regarding claim 10, Zhao in view of Huszak teaches further including instructions that cause the reference node to perform actions including:
calculating a time delay from sending the measurement pulses to receiving the response pulses (Huszak, see paragraphs 0043 and 0044, At 204 the measuring node 100 is configured to receive from the bus node 102 at least one loopback response signal caused by the transmitted at least one signal. At 206 the measuring node 100 is configured to measure a roundtrip delay between the at least one signal and the loopback response signal);
receiving from the nominated node in response to the command, a PHY time delay of the nominated node (Huszak, see paragraph 0022, The apparatus further comprises means for solving the physical order of the bus nodes in the multi-drop communication bus based on the roundtrip delays); and
determining a transmit time delay from the reference node to the nominated node using the time delay from sending the measurement pulse to receiving the measurement pulse, the PHY time delay of the reference node, and the PHY time delay of the nominated node (Huszak, see paragraph 0046, the measuring node 100 may be configured to use the initial delay, timer and the content of the long delay line roundtrip time. Now the measuring node 100 has in its possession a vector of physical identifiers and their distances in time domain. The time domain may be mapped a spatial distance using any known solution enabling to achieve this).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHONG G KIM whose telephone number is (571)270-0619. The examiner can normally be reached Mon-Fri @ 9am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nicholas R. Taylor can be reached at 571-272-3889. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHONG G KIM/Examiner, Art Unit 2443
/NICHOLAS R TAYLOR/Supervisory Patent Examiner, Art Unit 2443
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