DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The following claimed benefit is acknowledged: The instant application, filed on 20 September 2023, claims foreign priority to DE Application No. 102021107145.3, filed on 23 March 2021.
Information Disclosure Statement
The Information Disclosure Statements (lDS) submitted on 09/20/2023 and 12/19/2023 are in compliance with the provisions of 37 CFR 1.97 and have been considered.
Claim Objections
Claims 3 and 8 are objected to because of the following informalities:
Regarding claim 3, “configured determine” should read --configured to determine--.
Regarding claim 8, “the digital generated integration value” should read --the generated integration value--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 10-12 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2 and 15 recite that the one or more characteristics of the detected signal “comprise one or more of” several listed characteristics, followed by the phrase “and/or” before the final listed characteristic. The phrase “one or more of” already indicates that the listed characteristics are alternatives or combinations of alternatives. The additional use of “and/or” renders the scope unclear because it is not clear whether the final listed characteristic is merely one alternative among the listed characteristics, is required in addition to one or more of the preceding listed characteristics, or is optionally included only in combination with one of the preceding listed characteristics. Applicant may overcome the indefiniteness by amending “and/or” to recite --or--.
Claim 10 recites “one or more additional integrator circuits, wherein each of the one or more additional integrator circuits is configured according to the integrator circuit.” The phrase “configured according to the integrator circuit” is unclear because it does not identify what aspect of “the integrator circuit” is required to be shared by each additional integrator circuit. It is unclear whether the additional integrator circuits must have identical circuit structure, identical input/output connections, identical control signal timing, identical integration functionality, or merely a generally similar configuration. Applicant may overcome the indefiniteness by amending to clarify the configuration of each integrator circuit of the plurality of integrator circuits. For example, claim 10 may be amended to recite: The detection system according to claim 1, further comprising: a plurality of integrator circuits, wherein the plurality of integrator circuits comprises the integrator circuit and one or more additional integrator circuits, wherein each integrator circuit of the plurality of integrator circuits is configured to integrate the detected signal responsive to a respective integration start signal and to generate a respective integration value.
Claim 11 recites that the processing circuit is configured to transmit respective integration start signals at different respective times “and/or” to transmit respective integration stop signals at different respective times. The use of “and/or” renders the required configuration of the processing circuit unclear because it is not clear whether the processing circuit must be configured to perform only staggered start signal transmission, only staggered stop signal transmission, or both. Further, the phrase “the time of the other integrator circuits” does not clearly identify whether “the time” refers to a start time, a stop time, or both. Applicant may overcome the indefiniteness by amending the claim to replace the “and/or” formulation with clear inclusive alternative language and to clarify the respective start and stop times. For example, claim 11 may be amended, in view of the amendment of claim 10 proposed above, to recite: The detection system according to claim 10, wherein the processing circuit is configured to perform one or both of: transmitting, to each integrator circuit of the plurality of integrator circuits, the respective integration start signal corresponding to the integrator circuit to initiate integration of the detected signal at a respective start time, wherein the respective start times are different from one another; and transmitting, to each integrator circuit of the plurality of integrator circuits, a respective integration stop signal to stop integration of the detected signal at a respective stop time, wherein the respective stop times are different from one another.
Claim 12 recites that the processing circuit is configured “to reconstruct a shape of the detected signal and/or to determine a confidence of expected properties of the detected signal.” The use of “and/or” renders the required processing circuit functionality unclear because it is not clear whether the processing circuit must reconstruct the signal shape, determine the confidence, or perform both operations. Additionally, the phrase “a confidence of expected properties” does not clearly define what “confidence” is being determined or which “expected properties” are encompassed. Applicant may overcome the indefiniteness by amending the claim to replace the “and/or” formulation with clear inclusive alternative language and to clarify the confidence determination. For example, claim 12 may be amended, in view of the amendments of claims 10-11 proposed above, to recite: The detection system according to claim 11, wherein the processing circuit is configured, using the respective integration values generated by the plurality of integrator circuits, to perform one or both of: reconstructing a shape of the detected signal; and determining a confidence value indicating a confidence that the detected signal has one or more expected properties.
Claim 3 is rejected by virtue of dependency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-7 and 13-15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Kacyra (US 20050099637 A1).
Regarding claim 1, Kacyra discloses a detection system (Fig. 5, FDV 10 including lidar transceiver 502, further detailed in Fig. 6, optical transceiver 502; ¶¶ 92-93, 110), comprising:
a detector circuit configured to detect a signal and to provide the detected signal (Fig. 6, detector 612; ¶¶ 112, 126, detector 612 receives returned optical pulse energy and converts optical pulses into electrical pulses for timing circuit 616);
an integrator circuit configured to integrate the detected signal responsive to an integration start signal and to generate an integration value representing a result of the integration of the detected signal over time (Fig. 39, switch 3930 and integrator 3940; ¶ 147, the detected signal applied through switch 3930 to integrator 3940 “over the period of time the switch is closed,” and “the value of the integrator” is sampled after the pulse, where the comparator output that closes switch 3930 corresponding to the integration start signal); and
a processing circuit (Fig. 6, timing circuit 616, further detailed by Fig. 39) configured to:
detect a change of the detected signal from below to above a predefined trigger threshold value (Fig. 39, comparator 3920; ¶¶ 146-147, timing is based on when the pulse exceeds a set threshold level) and,
in the case that the change of the detected signal from below to above the predefined trigger threshold value is detected, transmit the integration start signal to the integrator circuit (Fig. 39, comparator 3920 output to switch 3930; ¶ 147, comparator 3920 closes switch 3930 when the signal exceeds the set threshold level, thereby starting gated integration by integrator 3940);
determine a time between a provided time measurement start signal and the detection of the change of the detected signal as a time measurement associated with the detected signal (Fig. 6, timing circuit 616; ¶¶ 112, 129, 164-165, timing circuit 616 measures the interval between the start pulse sampled from the outgoing pulse and the stop pulse returned from the object); and
determine one or more characteristics of the detected signal using the generated integration value (Fig. 39, ADC 3950 of timing circuit 616; ¶¶ 126, 147, timing circuit estimates pulse energy intensity from the sampled integrator value and outputs intensity information for each pulse; ¶ 165, outputs “both the time delay between start and stop pulses, and the intensity of each pulse”).
Regarding claim 2, Kacyra discloses the detection system of claim 1, and further discloses: wherein the one or more characteristics of the detected signal comprise one or more of: an energy of the etected signal, a peak value of the detected signal, and/or a time difference between a time corresponding to the detected change of the detected signal and a time corresponding to a reference feature of the detected signal (¶ 147, “timing circuit estimates the energy in each detected pulse”).
Regarding claim 4, Kacyra discloses the detection system of claim 1, and further discloses: wherein the processing circuit comprises a trigger comparator (Fig. 39, comparator 3920; ¶ 147) configured to output a first trigger signal in the case that a value of the detected signal is greater than the predefined trigger threshold value and to output a second trigger signal in the case that a value of the detected signal is less than the predefined trigger threshold value (Fig. 39, comparator 3920 controlling switch 3930; ¶ 147, comparator responds when signal “exceeds a selected level” and when the signal falls below the same level, producing the two comparator switch-control states); and wherein the change of the detected signal corresponds to a change of the output of the trigger comparator (Fig. 39, comparator 3920 threshold transition drives the gate switch transition; ¶¶ 146-147).
Regarding claim 6, Kacyra discloses the detection system of claim 1, and further discloses: a delay circuit configured to delay the detected signal by a predefined time delay (Fig. 39, delay 3910; ¶ 147, “signal is also applied to a delay 3910” and “the delay is chosen to compensate for the time lag in the comparator and switch”); wherein the integrator circuit is configured to integrate the delayed signal responsive to the integration start signal (Fig. 39, switch 3930 and integrator 3940; ¶ 147, “the output of the delay goes through the switch 3930 when it is closed, and is applied to the integrator 3940”).
Regarding claim 7, Kacyra discloses the detection system of claim 1, further discloses: wherein the integrator circuit comprises: an input switch having a first state and a second state, wherein the input switch is configured to switch to the first state responsive to the integration start signal and to switch to the second state responsive to an integration stop signal (Fig. 39, switch 3930; ¶ 147, the gated integrator gate is open/closed at the beginning/end of the pulse, and comparator 3920 controls switch 3930 based on the selected threshold); and an integrator configured to integrate the detected signal responsive to the integration start signal in the case that the input switch is in the first state (Fig. 39, integrator 3940; ¶ 147, delayed signal passes through switch 3930 “when it is closed” and is applied to integrator 3940 during that interval).
Regarding claim 13, Kacyra discloses a LIDAR system (Fig. 5, lidar transceiver 502; ¶¶ 92-94), comprising:
a light emission system configured to emit a light signal (Fig. 6, laser 602; ¶ 111, laser 602 fires an optical pulse); and
a detection system (Fig. 6, detector 612 and timing circuit 616) comprising:
a detector circuit configured to detect a signal and to provide the detected signal (Fig. 6, detector 612; ¶¶ 112, 126, detector 612 converts received optical pulses into electrical pulses for timing processing):
an integrator circuit configured to integrate the detected signal responsive to an integration start signal and to generate an integration value representing a result of the integration of the detected signal over time (Fig. 39, switch 3930 and integrator 3940; ¶ 147, comparator controlled switch passes the delayed signal to integrator 3940 during the gate interval, and the integrator value is sampled by ADC 3950); and
a processing circuit (Fig. 39, comparator 3920) configured to:
detect a change of the detected signal from below to above a predefined trigger threshold value (Fig. 39, comparator 3920; ¶¶ 146-147, the timing circuit detects when a pulse exceeds a selected threshold) and, in the case that the change of the detected signal from below to above the predefined trigger threshold value is detected, transmit the integration start signal to the integrator circuit (Fig. 39, comparator 3920 controlling switch 3930; ¶ 147, comparator 3920 closes switch 3930 when the signal exceeds the selected level, thereby starting the gated integration);
determine a time between a provided time measurement start signal and the detection of the change of the detected signal as a time measurement associated with the detected signal (Fig. 6, timing circuit 616; ¶¶ 129, 146, 164, timing circuit measures the interval between the initial start pulse and the reflected stop pulse crossing the threshold); and
determine one or more characteristics of the detected signal using the generated integration value (Fig. 39, ADC 3950; ¶¶ 126, 147-148, pulse intensity energy is recorded),
wherein the detection system is further configured to detect a delayed and modified version of the emitted light signal as the detected signal (Fig. 39, delay 3910; ¶ 147, “signal is also applied to a delay 3910” and “the delay is chosen to compensate for the time lag in the comparator and switch”).
Regarding claim 14, Kacyra discloses a method of performing a time measurement (Fig. 6 as further detailed in Fig. 39), the method comprising:
detecting a signal (Fig. 6, detector 612; ¶ 126, detector 612 converts optical pulses to electrical pulses);
detecting a change of the detected signal from below to above a predefined trigger threshold value (Fig. 39, comparator 3920; ¶ 147, comparator responds when the signal “exceeds a selected level”; ¶ 146, timing uses the point when the return pulse exceeds the set threshold voltage);
integrating the detected signal after detecting the change of the detected signal from below to above the predefined trigger threshold value and generating an integration value representing a result of the integration of the detected signal over time (Fig. 39, switch 3930 + integrator 3940; ¶ 147, gated integrator applies the delayed signal to integrator 3940 over the closed-switch interval and samples the integrator value after the pulse);
determining a time between a provided time measurement start signal and the detection of the change of the detected signal as a time measurement associated with the detected signal (Fig. 6, timing circuit 616; ¶ 129, interval timer measures between initial start pulse and reflected pulse; ¶ 164, timing circuit provides relative time between start and stop pulses); and
determining one or more characteristics of the detected signal using the generated integration value (Fig. 39, integrator 3940; ¶ 147, timing circuit estimates pulse energy; ¶ 165, timing circuit outputs intensity of each pulse).
Regarding claim 15, Kacyra discloses the method of claim 14, and further discloses: wherein the one or more characteristics of the detected signal comprise one or more of: an energy of the detected signal, a peak value of the detected signal, a time difference between a time corresponding to the detected change of the detected signal and a time corresponding to a reference feature of the detected signal, and/or a confidence of expected properties of the detected signal (¶ 147, “timing circuit estimates the energy in each detected pulse” using the gated integrator).
Claims 1, 6-7, 10 and 14 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Riedel (US 20090224835 A1).
Regarding claim 1, Riedel discloses a detection system (Fig. 4, detector electronics overview 400 including detector 401, preamps 402/403, and ROC 405, as further detailed in Fig. 5), comprising:
a detector circuit configured to detect a signal and to provide the detected signal (Fig. 4, detector 401 with preamplifier cards 402/403; ¶¶ 48, 60);
an integrator circuit configured to integrate the detected signal responsive to an integration start signal and to generate an integration value representing a result of the integration of the detected signal over time (Fig. 5, channel electronics 505 as further detailed in Fig. 9, integration circuit 900; ¶66, delay-line output is input to an integration circuit including op amp 925, switch 920, capacitor C854, and resistors; when comparator 810 is high, FPGA “will start the integration”; ¶61, channel FPGA measures “integrated voltages on channels A and B”); and
a processing circuit configured to: detect a change of the detected signal from below to above a predefined trigger threshold value and, in the case that the change of the detected signal from below to above the predefined trigger threshold value is detected, transmit the integration start signal to the integrator circuit (Fig. 5, channel FPGA 520, with Fig. 8 comparator 810; ¶ 60, discriminator outputs logic high when summed signal “exceeds a predetermined magnitude” and channel FPGA starts integration when it triggers; ¶¶ 64-65, comparator 810 uses threshold1 and logical one output starts timing of integration circuits);
determine a time between a provided time measurement start signal and the detection of the change of the detected signal as a time measurement associated with the detected signal (Fig. 5, channel FPGA 520; ¶ 61, timestamp is “the time difference between a synchronization pulse and when the neutron is actually detected”; ¶ 65, comparator 810 causes the channel FPGA to store a timestamp counter value); and
determine one or more characteristics of the detected signal using the generated integration value (Fig. 5, control FPGA 515; ¶ 61, baseline and integrated values with timestamp are sent to control FPGA 515 “which performs the position calculation”).
Regarding claim 6, Riedel discloses the detection system of claim 1, and further discloses: a delay circuit configured to delay the detected signal by a predefined time delay (Fig. 9, delay line 915; ¶ 66, “delay line 915 delays the input signal giving the digital circuitry in the channel FPGA time to act on the switch 920”); wherein the integrator circuit is configured to integrate the delayed signal responsive to the integration start signal (Fig. 9, delay line 915 feeding integration circuit 900; ¶ 61, integration is “preferably accomplished by integrating a delayed signal”; ¶ 66, delay line output is input to the integration circuit and FPGA starts integration when comparator 810 is high).
Regarding claim 7, Riedel discloses the detection system of claim 1, further discloses: wherein the integrator circuit comprises: an input switch having a first state and a second state, wherein the input switch is configured to switch to the first state responsive to the integration start signal and to switch to the second state responsive to an integration stop signal (Fig. 9, switch 920; ¶ 66, before integration switch 920 is closed in unity gain mode; if the FPGA determines detection, “switch 920 is open forming an integrator”; after programmable integration time, “switch 920 is again closed”); and an integrator configured to integrate the detected signal responsive to the integration start signal in the case that the input switch is in the first state (Fig. 9, op amp 925 and capacitor C854; ¶ 66, opening switch 920 starts integration).
Regarding claim 10, Riedel discloses the detection system of claim 1, further discloses: a plurality of integrator circuits, wherein the plurality of integrator circuits comprises the integrator circuit and one or more additional integrator circuits, wherein each of the one or more additional integrator circuits is configured according to the integrator circuit (Fig. 9, integration circuit 900; ¶ 66, “There are separate identical integration stages for channels A and B”).
Claim 14 is a method corresponding to the system of claim 1. Accordingly, claim 14 is rejected on the same grounds and in view of the same prior art as claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kacyra in view of Oohata (US 20180259629 A1).
Regarding claim 3, Kacyra discloses the detection system of claim 3. Although Kacyra in ¶ 148 discloses using the one or more characteristics, specifically return pulse intensity, to correct for range walk error, Kacyra does not disclose: wherein the one or more characteristics of the detected signal comprise the time difference; and wherein the processing circuit is further configured determine an error-compensated time measurement associated with the detected signal by adapting the determined time measurement using the determined time difference. However, Oohata teaches: wherein the one or more characteristics of the detected signal comprise the time difference (Fig. 12; ¶ 115, “two threshold values Vth1 and Vth2 … are set,” where timing t1a/t1b corresponds to crossing Vth1, timing t2a/t2b corresponds to crossing Vth2, “a difference between the timings (t2a−t1a) is Δt1,” “a difference between the timings (t2b−t1b) is set to Δt2,” and “Δt1 or Δt2 is appropriately referred to as a detection time difference”; ¶ 116, lookup table relates the detection time difference to photon number); and wherein the processing circuit is further configured determine an error-compensated time measurement associated with the detected signal by adapting the determined time measurement using the determined time difference (Fig. 14, TDCs 43b/43c, lookup table reference circuit 43d, and timing correction circuit 43e; ¶ 130, TDC 43b acquires time difference signal t7s; ¶ 132, lookup table reference circuit 43d “obtains the detection time difference … (t43b−t43a),” acquires a shift amount M corresponding to the detection time difference, and timing correction circuit 43e “subtracts the shift amount M from the time difference signal t7s to perform correction,” thereby acquiring “the time difference signal t8s corresponding to accurate time of flight of the pulsed light”). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the processing circuit of Kacyra and correct for leading edge time walk error using detection time difference as taught by Oohata with a reasonable expectation of success in order to further improve the distance measurement accuracy (Oohata, ¶¶ 3-4, 115-116, 132).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kacyra in view of Mori (US 20080068584 A1).
Regarding claim 5, Kacyra discloses the detection system of claim 1, and further discloses: wherein the processing circuit is configured to determine at least one characteristic of the one or more characteristics of the detected signal using the generated integration value and at least one lookup-table (Fig. 39, integrator 3940 and ADC 3950; ¶ 147, “A table of corrections is maintained to improve the range estimates”; ¶ 148, “the intensity and the measured time delay values produce a map of the range walk correction required for each intensity”), […].
Kacyra does not disclose: “the at least one lookup-table comprising a respective value of the at least one characteristic for each integration value of a plurality of integration values.” However, Mori teaches generating an integration value from the reflected signal (Fig. 6, reflected light intensity detector 726 and second memory 729; ¶ 97, reflected light intensity detector 726 “calculates an integration value S7 of the reflected signal S5b … and its result is stored in the second memory 729”; ¶ 100, the integration may be determined as “the sum of products between the respective sampling values in the integration range R2 and the sampling interval,” or by adding the sampling values), and further teaches the at least one lookup-table comprising a respective value of the at least one characteristic for each integration value of a plurality of integration values (Fig. 10C; ¶ 101, system controller 71 “reads the integration values stored in the second memory 729 and compensates the calculated distance L, in accordance with the compensation table value indicating the relation between a preset integration value and a compensation distance”; ¶ 103, Fig. 10C shows “the relation between the integration value and the compensation amount for the distance”; ¶ 105, the controller may compensate delay time “in accordance with the compensation table value indicating the relation between the integration value and the delay time”). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the at least one lookup-table of Kacyra such that it was implemented as an integration value indexed compensation table as taught by Mori with a reasonable expectation of success in order to account for distance errors arising from intensity variation and compensate distance measurements according to the generated integration value, thereby yielding a system with improved measurement precision and greater distance correction stability over environments with varying reflected light intensities (Mori, ¶¶ 13, 17, 101, 103-105).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kacyra in view of Wilsher (US 5905577 A).
Regarding claim 8, Kacyra discloses the detection system of claim 1, and further discloses: wherein the integrator circuit comprises: an integrator configured to receive the integration start signal from the processing circuit and to output an analog output value representing the integration value (Fig. 39, switch 3930 and integrator 3940; ¶ 147, comparator 3920 controls switch 3930, the delayed signal passes through switch 3930 and is applied to integrator 3940 while the switch is closed, and after the pulse “the value of the integrator is sampled”); […].
Kacyra does not disclose: “a sample-and-hold circuit configured to sample the analog output value of the integrator and to hold the sampled analog output value substantially constant; and an analog-to-digital-converter configured to, responsive to an ADC readout signal, detect the hold analog output value of the sample-and-hold circuit and to output a digital representation of the digital generated integration value.” However, Wilsher teaches: “a sample-and-hold circuit configured to sample the analog output value of the integrator and to hold the sampled analog output value substantially constant” (Fig. 9, integrator 912 and sample-and-hold circuit 914; Col. 9:20-34, switch S2 passes the probe pulse to integrator 912, integrator 912 integrates the voltage pulse from photodetector 650, “the output of integrator 912 then remains constant,” and the voltage on the output of integrator 912 is transferred to sample-and-hold circuit 914 while control voltage ML3a is high; sample-and-hold circuit 914 returns to hold when ML3a goes low); “and an analog-to-digital-converter configured to, responsive to an ADC readout signal, detect the hold analog output value of the sample-and-hold circuit and to output a digital representation of the digital generated integration value” (Fig. 9, ADC 918; Col. 9:34-39, the output of sample-and-hold circuit 914 is applied through amplifier 916 to ADC 918, “Control Voltage ML4a controls the data conversion operation of ADC 918” and “output of ADC 918 represents the energy of the reflected probe light pulses”; see further Fig. 10). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the integrator circuit of Kacyra such that the integrator output was held as a stable analog voltage level before the ADC digitized the held pulse energy value, as taught by Wilsher, with the motivation to provide a stable analog value for ADC conversion and improve the digital readout stability of the integrated optical pulse energy (Wilsher, Col. 8:49-67 & 9:20-39).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Riedel in view of Nishino (“High-speed charge-to-time converter ASIC for the Super-Kamiokande detector,” published 2009)1.
Regarding claim 9, Riedel discloses the detection system of claim 1. Although Riedel further discloses that the processing circuit is configured to transmit the integration stop signal at a predefined time period after transmitting the integration start signal (Fig. 5, channel FPGA 520; Fig. 9, switch 920 and integration circuit 900; ¶ 66, “it will start the integration of the input signal at a time based on programmable settings,” and “[a]fter a programmable integration time, the switch 920 is again closed, removing the integrated charge from capacitor C854”), Riedel does not disclose: wherein the integrator circuit comprises: an input switch having a charge state and a discharge state, wherein the input switch is configured to switch to the charge state responsive to the integration start signal and to switch to the discharge state responsive to an integration stop signal; an integrator configured to charge by integrating the detected signal in the case that the input switch is in the charge state and to discharge by integrating a constant reference signal of opposite polarity to the expected polarity of the detected signal, in the case that the input switch is in the discharge state; wherein the processing circuit is configured to: transmit the integration stop signal a predefined time period after transmitting the integration start signal; determine a time duration it takes to discharge the integrator; and generate the integration value using the determined time duration it takes to discharge the integrator.
However, Nishino teaches an integrator circuit (Fig. 4, V/I converter and charging/discharging block) comprising:
an input switch having a charge state and a discharge state, wherein the input switch is configured to switch to the charge state responsive to the integration start signal and to switch to the discharge state responsive to an integration stop signal (Fig. 4, charging/discharging block; Fig. 5, charge gate and discharge gate; p. 712, “During the charge gate, the switch between the V/I converter and charging capacitor closes and input charge accumulates in the capacitor. During the discharge gate, the switch between the discharging current source and capacitor closes, and arriving input signals are ignored”);
an integrator configured to charge by integrating the detected signal in the case that the input switch is in the charge state (Fig. 5, integrated charge waveform rising during charge gate; pp. 711-712, “Charge integration starts when the amplified input signal crosses the discriminator threshold” and “input charge accumulates in the capacitor”) and
to discharge by integrating a constant reference signal of opposite polarity to the expected polarity of the detected signal, in the case that the input switch is in the discharge state (Fig. 4, discharging timer/current source in the charging/discharging block; Fig. 5, integrated charge waveform decreasing during discharge gate; pp. 711-712, “[a]fter a charging period determined by the timer block, the integrated signal starts to be discharged by a constant current source” and “the switch between the discharging current source and capacitor closes,” where the constant current source corresponds to the constant reference signal, and it is of opposite electrical polarity to the accumulated detected signal charge since discharging causes the integrated signal voltage to decrease toward the comparator threshold); wherein
the processing circuit is configured to: transmit the integration stop signal a predefined time period after transmitting the integration start signal; determine a time duration it takes to discharge the integrator (Fig. 5, discharge gate and output pulse width; p. 712, “[t]he trailing edge of the QTC output signal represents the time when the integrated signal voltage decreases to the comparator threshold level” and “the QTC output signal widens as the input signal gets larger”);
and generate the integration value using the determined time duration it takes to discharge the integrator (p. 710, “drives output timing signals whose width represents the integrated charge of the PMT signal”; p. 711, “encodes the amount of input charge to the timing signal, where leading edge and width represent timing and integrated charge of the input signal, respectively” and “[t]he discharging time is proportional to the integrated charge, which is known from the width of the output signal”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the integrator circuit of Riedel with the teachings of Nishino with a reasonable expectation of success in order to encode the integrated detector charge as a timing signal width readable by TDC circuitry, thereby yielding a detection system with improved high speed detector readout and simplified charge acquisition and downstream data handling (Nishino, Abstract; pp. 710-711; Fig. 3; Fig. 5; Table 1).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Riedel in view of Engel (“Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit,” published 2009)2.
Regarding claim 11, Riedel discloses the detection system of claim 10. Although Riedel discloses a plurality of integrator circuits (Fig. 9; ¶ 66, “separate identical integration stages for channels A and B”) where the processing circuit is configured to control integration of the detected signal in the plurality of integrator circuits (Fig. 5, channel FPGA 520; ¶¶ 60, 66), Riedel does not disclose: wherein the processing circuit is configured to: transmit a respective integration start signal to each of the plurality of integrator circuits to initiate the integration of the detected signal at a respective time that is different from the time of the other integrator circuits of the plurality of integrator circuits; and/or to transmit a respective integration stop signal to each of the plurality of integrator circuits to stop the integration of the detected signal at a respective time that is different from the time of the other integrator circuits of the plurality of integrator circuits.
However, Engel teaches an integrated circuit using “multi-region charge integration” where each channel includes three pulse height sub-channels, and each sub-channel includes “a gated integrator” with an externally programmable gate generator defining both the start and width of the integration gate relative to a discriminator signal (p. 161, Abstract). Engel further teaches that “[f]or each linear signal, three different integrations (called A, B, and C) will be performed with start times referenced to the individual discriminators” and that “delays in the integrators’ starting times (DA, DB, DC) and the widths (WA, WB, WC) of the integration windows are controlled by the user” (p. 162, Fig. 1). Engel also shows the specific sub-channel timing structure in Fig. 2, and the sub-channel gate-control circuitry in Fig. 4, further explaining that each sub-channel has “a gated integrator and a corresponding gate generator,” where one voltage-to-time converter determines the start of the integration period and another determines the duration of the integration period (p. 166, §3.5 and §3.5.1). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the integrator circuit of Riedel with the teachings of Engel with a reasonable expectation of success in order to integrate different regions of the detector pulse using separately controlled integrator start delays and integration window widths, thereby yielding a detection system with greater adaptability to variations in detected pulse shapes and improved pulse shape discrimination (Engel, p. 161, Abstract; p. 162; p. 170, Summary).
Regarding claim 12, Riedel in view of Engel teaches the detection system of claim 11, and further teaches: Although Riedel discloses that each integrator circuit of the plurality of integrator circuits is configured to generate a respective integration value (Fig. 9, separate A/B integration stages; ¶ 61), Riedel does not disclose: wherein each integrator circuit of the plurality of integrator circuits is configured to generate a respective integration value; and wherein the processing circuit is configured to reconstruct a shape of the detected signal and/or to determine a confidence of expected properties of the detected signal using the integration values generated by the plurality of integrator circuits.
However, Engel teaches using integration values from a plurality of integrator circuits to determine expected signal properties. Specifically, Engel teaches circuitry that performs “multi-region charge integration” (p. 161, Abstract), where three sub-channels produce respective integrations A, B, and C, and that the outputs A, B, C, and T are sent for ADC digitization (p. 162, Fig. 1; p. 163, Fig. 2), further teaching that different integration values are used to determine expected properties of the detected signal (p. 169, Fig. 11 and accompanying discussion). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the integrator circuit of Riedel in view of Engel with the additional teachings of Engel with a reasonable expectation of success in order to employ integration values from different detector pulse regions for pulse shape discrimination, thereby yielding a detection system with improved confidence and reliability in event discrimination while reducing readout cost, size and power (Engel, p. 161, Abstract; p. 169, Fig. 11; p. 170, Summary).
Conclusion
Prior art made of record though not relied upon in the present basis of rejection are noted in the attached PTO 892 and include:
Solf (US 20110001053 A1) which discloses a detector array signal processing architecture in which threshold leading-edge detection triggers integration and ADC/TDC readout to generate event energy values and time stamps.
Slobodyanyuk (US 20170090019 A1) which discloses a LIDAR receiver that detects reflected pulses, measures threshold crossing timing with a TDC, integrates the detected analog signal, digitizes the integrator output, and processes the timing integration data to estimate reflected energy.
Dimsdale (US 20070252974 A1) which discloses a pulsed LIDAR 3D imaging system using detector timing circuits, discriminator triggered pulse timing, and gated integrators or peak detectors to measure reflected pulse intensity for range error compensation.
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/ZHENGQING QI/Examiner, Art Unit 3645
1 Nishino, H., et al. "High-speed charge-to-time converter ASIC for the Super-Kamiokande detector." Nuclear instruments and methods in physics research section a: accelerators, spectrometers, detectors and associated equipment 610.3 (2009): 710-717.
2 Engel, G. L., et al. "Design and performance of a multi-channel, multi-sampling, PSD-enabling integrated circuit." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 612.1 (2009): 161-170.
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