Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 21-23 and 25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sizov et al (WO 2019/147589).
Regarding claim 21, Sizov teaches a display system comprising: an array of light-emitting diodes (175, figs. 1-8) configured to emit illumination light; a substrate (400) with driver circuitry (paragraph [0063]) that controls the array of light-emitting diodes, wherein the array of light-emitting diodes are mounted on the substrate, wherein each light-emitting diode comprises an n-type semiconductor layer (104, figs. 7 and 8, paragraphs [0055][0070]) and a p-type semiconductor layer (108,paragraph [0055]), wherein each light-emitting diode comprises a respective p contact pad (180, paragraph [0065]) that electrically connects the p-type semiconductor layer for that light-emitting diode to the driver circuitry, wherein the array of light-emitting diodes shares a common n contact pad (190, paragraph [0064]) that electrically connects the n- type semiconductor layer for the light-emitting diodes to the driver circuitry, and wherein the p contact pads are interposed between the substrate and the n contact pad; a first dielectric layer (134, figs. 7 and 8, paragraph [0058]) that has portions that are interposed between the light-emitting diodes in the array of light-emitting diodes, wherein the n-type semiconductor layer overlaps the portions of the first dielectric layer; and a second dielectric layer (170, paragraph [0061]) that is formed around the first dielectric layer.
Regarding claim 22, Sizov teaches the display system defined in claim 21, wherein the first dielectric layer (134, figs. 7 and 8) has additional portions that laterally surround the array of light-emitting diodes and wherein the additional portions are interposed between the array of light-emitting diodes and the second dielectric layer.
Regarding claim 23, Sizov teaches the display system defined in claim 21, wherein the second dielectric layer has additional portions that are interposed between the light-emitting diodes in the array of light-emitting diodes (figs. 7 and 8).
Regarding claim 25, Sizov teaches the display system defined in claim 21, wherein the p-type semiconductor layer is a respective p-type semiconductor layer for each light-emitting diode in the array of light-emitting diodes (paragraph [0055], figs. 1-8).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (PG Pub 2021/0183301 A1) and Sizov et al (WO 2019/147589).
Regarding claim 19, Choi teaches a display system comprising: an array of light-emitting diodes (242/243/245, fig. 4) configured to emit illumination light; and a substrate with driver circuitry (in 235) that controls the array of light-emitting diodes, wherein the array of light- emitting diodes are mounted on the substrate, wherein each light-emitting diode comprises a p-type semiconductor layer (242, paragraph [0087]) and a common n-type semiconductor layer (245, paragraph [0087]), wherein each light-emitting diode comprises a respective p contact pad (241) that electrically connects the p-type semiconductor layer for that light-emitting diode to the driver circuitry, wherein the array of light-emitting diodes shares a common n contact pad (260), and wherein the p contact pads are interposed between the substrate and the n contact pad (fig. 4).
Choi does not each the common n contact pad electrically connects the common n- type semiconductor layer for the light-emitting diodes to the driver circuitry.
In the same field of endeavor, Sizov teaches a common n contact pad (190, fig. 8) electrically connects the n- type semiconductor layer for the light-emitting diodes to the driver circuitry (in 400), for the benefit of providing electrical bias to the n-type semiconductor layer (paragraph [0064]).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the common n contact pad electrically connect the common n- type semiconductor layer for the light-emitting diodes to the driver circuitry for the benefit of providing electrical bias to the n-type semiconductor layer.
Regarding claim 20, Choi teaches the display system defined in claim 19, wherein each light-emitting diode additionally includes a multi-quantum wells layer (MQW, paragraphs [0084][0071]) that is interposed between the common n-type semiconductor layer and the p-type semiconductor layer for that light-emitting diode.
Response to Arguments
Applicant’s arguments with respect to claim(s) 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 1,3,10-13,26 are allowed.
Claim 24 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach
“a dielectric layer overlapping the driver die in the first direction; conductive routing lines on an upper surface of the dielectric layer; and conductive vias in the dielectric layer, wherein the conductive routing lines and the conductive vias electrically connect the common contact pad to a driver contact pad on the driver die” (claim 1);
“the n-type semiconductor layer is a common n-type semiconductor layer shared between each light-emitting diode in the array of light-emitting diodes” (claim 24) and “a second dielectric layer that is formed around the first dielectric layer” (claim 21).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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