DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The response filed 04/07/2026 is accepted, in which, claims 6, 10, and 11 are amended, claim 4 is canceled, and claim 21 is newly added. Claims 1-3 and 5-21 await an action on the merits as follows.
The objection to the specification is withdrawn in view of the amended title.
The rejection of claims 6 and 11 under USC 112b is withdrawn in view of the amended claims.
Response to Arguments
On page 8 of the response, Applicant argues,
"Element 218 in Yoshida is not a "second portion" of a unitary gate electrode structure. It is explicitly and unambiguously described as a "contact plug" that is electrically connected to the gate electrode structure. The gate electrode structure in Yoshida is formed earlier and consists of parts 207a and 207b (see, e.g., Fig. 3P and the description at [0043]-[0046] of Yoshida). The contact plug 218 is a separate, distinct conductive interconnect formed in a subsequent back-end- of-line (BEOL) process to provide electrical connection to the pre-existing gate electrode 207a and the body contact region.
…
In contrast, the present invention defines a unitary extended gate structure that is part of the gate electrode layer, fabricated in a front-end process. This structure has a first portion connected to the main gate and a second portion with a specifically defined, smaller length. The purpose of this specific stepped morphology, as described in Applicants' specification, is to provide alignment tolerance for the source/drain and body contact ion implants (which are of opposite types) while minimizing the gate area over the semiconductor to reduce parasitic capacitance.
Therefore, Yoshida fails to teach or suggest the claimed "extended gate comprising a first portion and a second portion." The Examiner's combination of Chan with an element of Yoshida (the contact plug 218) misinterpreted as a gate portion does not render the claimed invention obvious."
Examiner respectfully disagrees.
Utility patent applications are examined based on structure, not function and/or process of making as argued in the above underlined portion. There is no limitation in claim 1 that prevents the gate structure from being comprised of subparts being formed at different times. Claim 9's method goes on to limit, " the extended gate comprising a first portion joined to the main gate and a second portion located on a side of the first portion away from the main gate, the first portion joined to the second portion," which also does not prevent the gate structure from being comprised of subparts being formed at different times as long as the first and second portions exist in the final product.
While Yoshida discloses element 218 as a contact plug, Examiner interprets 218 as a subpart of the gate structure since a gate structure is known in the art to be comprised of a conductive structure connected to the channel of the transistor through an insulative layer.
As discussed in the previous rejection, the combination of Chan and Yoshida discloses the structure of the instant application. Therefore, the traversal is overcome and the previous rejection stands.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-11, and 13-21 are rejected under 35 U.S.C. 103 as being unpatentable over Chan (US 20050023608 A), and further in view of Yoshida (US 20120119267 A1).
Regarding claims 1 and 9, Chan teaches a semiconductor device, and a method of fabricating said semiconductor device, (MOSFET device, [Abs.], Fig 3A), comprising: a semiconductor-on-insulator (SOI) substrate (SOI, [0013]) comprising,
stacked from the bottom upward (shown stacked from bottom up, Fig 2B), a lower substrate (1), a buried insulating layer (2) and a semiconductor layer (3);
a gate electrode layer (5) formed on (shown on) the semiconductor layer (3),
the gate electrode layer (5) comprising a main gate (5A: horizontal portion of 5 parallel to line 2B in Fig 2A) and an extended gate (5B: vertical portion of 5 parallel to line 2C in Fig 2A),
a source region (7A: portion of 7 above 5A and to the left of 5B in Fig 4A) and a drain region (7B: portion of 7 below 5A and left of 5B in Fig 4A), which are formed in (shown in) the semiconductor layer (3) respectively on opposing sides (shown on opposing sides) of the main gate (5A),
Chan fails to explicitly teach the extended gate comprising a first portion joined to the main gate and a second portion located on a side of the first portion away from the main gate, the first portion joined to the second portion; the second portion having a length smaller than a length of the first portion on the semiconductor layer.
However, Yoshida teaches the extended gate comprising a first portion (207a, Fig 15P) joined (shown joined) to the main gate and a second portion (218) located on a side (207aT: top of 207a) of the first portion (207a) away (shown away) from the main gate,
the first portion (207a) joined (shown joined; contact plug electrically connected to gate electrode, [0084]) to the second portion (218);
the second portion (218) having a length (218L: length of 218 in horizontal direction in Fig 15P) smaller (shown smaller) than a length (207aL: length of 207a in horizontal direction of Fig 15P) of the first portion (207a) on (shown on) the semiconductor layer;
Chan then goes on to teach a body contact region (6, Fig 3A) formed in (shown in) the semiconductor layer (3) on (shown on) the side of the first portion away (shown away) from the main gate (5A),
the body contact region (6) at least in contact (shown in contact) with the second portion.
Chan and Yoshida are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor SOI devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Chan with the features of Yoshida to create a device wherein the extended gate comprising a first portion joined to the main gate and a second portion located on a side of the first portion away from the main gate, the first portion joined to the second portion; the second portion having a length smaller than a length of the first portion on the semiconductor layer which can operate at a high speed at a low voltage due to a decrease in threshold voltage (Yoshida, [0003]) and reduces the size of the capacitor electrode region which generates a parasitic capacitance which serves to reduce the parasitic capacitance (Yoshida, [0022]).
Regarding claim 2, the combination of Chan and Yoshida discloses the device of claim 1. Chan goes on to teach wherein a shallow trench isolation structure (4, Fig 3A) is formed on (shown on , Fig 1B) the buried insulating layer (2), the shallow trench isolation structure (4, Fig 3A) surrounding (shown surrounding) the source region (7A), the drain region (7B) and the body contact region (6).
Regarding claim 3, the combination of Chan and Yoshida discloses the device of claim 2. Yoshida teaches the first portion (207a, Fig 15P).
Chan goes on to teach wherein the main gate (5A, Fig 3A) extends (shown extending) on a side (5B-B: left side of 5B in Fig 3A, which would be the bottom of first portion 207a in Fig 15P of Yoshida) away (shown away) from the first portion from over (shown over) the semiconductor layer (3) to over (shown over) the shallow trench isolation structure (4).
Regarding claim 5, the combination of Chan and Yoshida discloses the device of claim 1. Chan teaches the main gate (5A, Fig 3A).
Yoshida goes on to teach wherein the second portion (218, Fig 15P) is aligned (shown aligned) with the main gate on the side (207aT) of the first portion (207a) away (shown away) from the main gate.
Regarding claims 6, 10, and 21, the combination of Chan and Yoshida discloses the device of claim 1 and the method of claim 9. Yoshida teaches a side (218T: top of 218 in Fig 15P) of the second portion (218, Fig 15P), the first portion (207a), and a side away (207aT).
Chan goes on to teach wherein the body contact region (6, Fig 3A) has a Π-like shape (shown with Π-shape), a horizontal arm (6A: vertical portion of 6 to the right of topographical projection of right edge of 4; please see annotated figure below) of the Π-like shape located in (shown in) the semiconductor layer (3) on (shown on) a side of the second portion away (shown away) from the first portion, and vertical arms (6B; please see annotated figure below) of the Π-like shape coming into contact (shown in contact) with the first portion on a side away from the horizontal arm (6A).
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Regarding claim 7, the combination of Chan and Yoshida discloses the device of claim 1. Chan teaches the main gate (5A, Fig 3A), the source region (7A, Fig 4A), the drain region (7B), and the body contact region (6, Fig 3A).
Yoshida goes on to teach wherein a first ion-doped region (Iwn, Fig 13) is formed in (shown in) the main gate (5A, Fig 3A) and the first portion (207a, Fig 15P) and a second ion-doped region (Iwp) in (shown in) the second portion (218), wherein the source region (7A, Fig 4A), the drain region (7B) and the first ion-doped region (Iwn) are of the same conductivity type (n-type); the body contact region (6, Fig 3A) and the second ion-doped region (Iwp) are of the same conductivity type (p-type).
Regarding claim 8, the combination of Chan and Yoshida discloses the device of claim 1. Chan goes on to teach wherein a gate dielectric layer (10, Fig 2B) is formed between (shown between) the gate electrode layer (5) and the semiconductor layer (3).
Regarding claim 11, the combination of Chan and Yoshida discloses the method of claim 9. Chan teaches forming the main gate (5A, Fig 3A), the source region (7A, Fig 4A), the drain region (7B), the semiconductor layer (3, Fig 3A), and the body contact region (6).
Yoshida goes on to teach wherein a first ion-doped region (Iwn, Fig 14) is formed in (shown formed in) the main gate and the first portion (207a) at the same time (shown formed at the same time) as the formation of the source region and the drain region in (shown in) the semiconductor layer on opposing sides (shown on opposing sides) of the main gate and a second ion-doped region (Iwp) is formed in (shown formed in) the second portion (218) at the same time (shown formed at the same time) as the formation of the body contact region in (shown in) the semiconductor layer on (shown on) the side (207aT) of the first portion (207a) away (shown away) from the main gate, wherein the source region, the drain region and the first ion- doped region (Iwn) are of the same conductivity type (n-type); the body contact region and the second ion-doped region (Iwp) are of the same conductivity type (p-type).
Regarding claims 13 and 15, the combination of Chan and Yoshida discloses the device of claim 7 and the method of claim 11. Chan teaches the body contact region (6, Fig 3A) and the source region (7A, Fig 4A).
Yoshida goes on to teach wherein the conductivity type (p-type) of the body contact region (6, Fig 3A) is different (different) from that (n-type) of the source region (7A, Fig 4A).
Regarding claim 14, the combination of Chan and Yoshida discloses the device of claim 1. Yoshida teaches the first portion (207a, Fig 15P).
Chan goes on to teach wherein the main gate (5A, Fig 3A) and the first portion make up a T-shaped structure (shown making a T-shape), the main gate (5A) forming a vertical arm (shown forming a vertical arm; figures of Chan would be rotated counter clockwise 90 degrees to agree with figures of Yoshida) of the T-shaped structure, and the first portion forming a horizontal arm (shown forming a horizontal arm) of the T-shaped structure.
Regarding claim 16, Chan teaches a semiconductor device (MOSFET device, [Abs.], Fig 3A), comprising: a semiconductor layer (3) of a substrate (SOI, [0013]);
a gate electrode layer (5) formed on (shown on) the semiconductor layer (3), the gate electrode layer (5) comprising a main gate (5A: horizontal portion of 5 parallel to line 2B in Fig 2A) and an extended gate (5B: vertical portion of 5 parallel to line 2C in Fig 2A),
Chan fails to explicitly teach the extended gate comprising a first portion joined to the main gate and a second portion located on a side of the first portion away from the main gate, the first portion joined to the second portion; the second portion has a length smaller than a length of the first portion on the semiconductor layer.
However, Yoshida teaches the extended gate comprising a first portion (207a, Fig 15P) joined (shown joined) to the main gate and a second portion (218) located on a side (207aT: top of 207a) of the first portion (207a) away (shown away) from the main gate,
the first portion (207a) joined (shown joined; contact plug electrically connected to gate electrode, [0084]) to the second portion (218);
the second portion (218) has a length (218L: length of 218 in horizontal direction in Fig 15P) smaller (shown smaller) than a length (207aL: length of 207a in horizontal direction of Fig 15P) of the first portion (207a) on (shown on) the semiconductor layer;
Chan goes on to teach a body contact region (6, Fig 3A) formed in (shown in) the semiconductor layer (3) on (shown on) the side of the first portion away (shown away) from the main gate (5A),
the body contact region (6) at least in contact (shown in contact) with the second portion.
Chan and Yoshida are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor SOI devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Chan with the features of Yoshida to create a device wherein the extended gate comprising a first portion joined to the main gate and a second portion located on a side of the first portion away from the main gate, the first portion joined to the second portion; the second portion has a length smaller than a length of the first portion on the semiconductor layer which can operate at a high speed at a low voltage due to a decrease in threshold voltage (Yoshida, [0003]) and reduces the size of the capacitor electrode region which generates a parasitic capacitance which serves to reduce the parasitic capacitance (Yoshida, [0022]).
Regarding claim 17, the combination of Chan and Yoshida discloses the device of claim 16. Chan goes on to teach wherein the substrate (SOI, Fig 2B) is a semiconductor- on-insulator (SOI) substrate (SOI, [0013]), the SOI substrate (SOI) comprising, stacked from the bottom upward (shown stacked from bottom up), a lower substrate (1), a buried insulating layer (2) and the semiconductor layer (3).
Regarding claim 18, the combination of Chan and Yoshida discloses the device of claim 16. Yoshida teaches the first portion (207a, Fig 15P) and the second portion (218).
Chan goes on to teach wherein the body contact region (6, Fig 3A) contacts (shown contacting) both the first portion and the second portion, the body contact region (6) surrounding (shown surrounding) the second portion together with the first portion.
Regarding claim 19, the combination of Chan and Yoshida discloses the device of claim 16. Chan teaches the main gate (5A, Fig 3A).
Yoshida goes on to teach wherein the second portion (218, Fig 15P) is aligned (shown aligned) with the main gate (5A, Fig 3A) on the side (207aT) of the first portion (207a) away (shown away) from the main gate.
Regarding claim 20, the combination of Chan and Yoshida discloses the device of claim 16. Yoshida teaches the first portion (207a, Fig 15P).
Chan goes on to teach wherein the main gate (5A, Fig 3A) and the first portion (207a, Fig 15P) make up a T-shaped structure (shown making a T-shape), the main gate (5A) forming a vertical arm (shown forming a vertical arm; figures of Chan would be rotated counter clockwise 90 degrees to agree with figures of Yoshida) of the T-shaped structure, and the first portion forming a horizontal arm (shown forming a horizontal arm) of the T-shaped structure.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Chan (US 20050023608 A), in view of Yoshida (US 20120119267 A1), and further in view of Athanasiou (US 20170288059 A1).
Regarding claim 12, the combination of Chan and Yoshida discloses the device of claim 1. Chan teaches the body contact region (6, Fig 3A). Yoshida teaches the second portion (218, Fig 15P).
The combination fails to explicitly teach the body contact region has a T-like shape with a vertical arm extending toward and coming into contact with the second portion.
However, Athanasiou teaches the body contact region has a T-like shape (body contact 1 shown with T-shape, Fig 1) with a vertical arm (1A: vertical arm under 5; figure 1 of Athanasiou would be rotated counter clockwise 90 degrees to agree with figure of Yoshida and Chan) extending (shown extending) toward and coming into contact (shown in contact) with the second portion.
Chan, Yoshida, and Athanasiou are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor SOI devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Chan and Yoshida with the features of Athanasiou to create a device wherein the body contact region has a T-like shape with a vertical arm extending toward and coming into contact with the second portion so the contact is close to the substrate of the transistor which makes it possible to reduce the spurious capacitive effects and the substrate access resistance (Athanasiou, [0044]), wherein such a device notably makes it possible to obtain a very significant current gain (Athanasiou, [0049]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tseng (US 20220320343 A1) - Body tie example with air gap between body tie and S/D.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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