DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election with traverse of Group I (claims 1-6) in the reply filed on is acknowledged. The traversal is on the ground(s) that applicant has amended the method claims such that they depend upon claim 1 and since the prior art Moon does not read on claim 1, the common technical features of the product and method claims as recited in claim 1 are special technical f eatures therefore unit is present . This is not found persuasive because as can be seen below claim 1 is not novel over Moon . Therefore the elected claims 2-6 will examined along with claim 1 which has been made generic by applicant’s amendment after the restriction requirement. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Moon (US 2013/0234240) . [claim 1 ] A semiconductor structure (fig. 1 , specifically the embodiment of fig. 11 which slightly modifies the device of fig. 1 as explained in [0087]) comprising: a first substrate (120 b, 120c , fig. 1 where 120c supports and contacts a contact plug of a lower electrode of a capacitor [0113] , see also fig. 33 ) , which has a first surface (top surface of 120c, fig. 1) and a second surface (bottom surface of 120b, fig. 1) opposite to the first surface, and comprises several discrete active areas (120b, 120c, fig. 1) arranged in a first direction (e.g. to the upper left in fig. 1) and parallel to a second direction (e.g. to the upper right in fig. 1) , wherein the first direction is perpendicular to the second direction (fig. 1) , an isolation layer (140, fig. 1, note that the embodiment of fig. 11 has 140 extend all the way to 110) is disposed between adjacent active areas, and the first surface and the second surface expose the isolation layer (fig. 1) ; a plurality of first grooves (filled in by 150 , 160, and 170, fig. 1) which are disposed in the first substrate, extend from the first surface to the second surface, are arranged in the second direction (fig. 1) , and run through the active areas along the first direction (fig. 1) , as well as have a bottom with a distance less than the thickness of the isolation layer from the first surface (note that in fig. 11, the isolation layer 140 extends all the way to bottom of 120a, while the first groove only ext4ends to the bottom of 120b in fig. 1) ; a word line gate structure (160, fig. 1) , which is disposed in the first grooves; a plurality of bit lines (130, fig. 11, [0087]) , which are disposed on the second surface (bottom surface of 120b, fig. 11) , arranged in the first direction (fig. 11) , and parallel to the second direction (fig. 1) , wherein one of the active areas is electrically coupled with one of the bit lines (fig. 11) . [claim 2 ] The semiconductor structure according to claim 1, wherein the isolation layers have a surface protruding from the second surface (140, fig. 11 protrudes above the bottom of 120b which is the bottom surface) and have a second groove (filled in by 120 and 130 in fig. 11) between each other (isolation layers 140, fig. 11) , wherein the second groove exposes the second surface (fig. 11) , is parallel to the second direction, and is arranged in the first direction (fig. 1) n; and the bit lines (130, fig. 11) are disposed in the second groove. [claim 3 ] The semiconductor structure according to claim 1, further comprising a dielectric layer (172, fig. 11, [0087]) , which is disposed on the second surface (on the bottom of 120b, fig. 11) and has a second groove (filled in by 120 and 130/172 in fig. 11) exposing a surface of the active areas therein (top of 120c is exposed by second grooves, fig. 11) , wherein the second groove is parallel to the second direction and arranged in the first direction (fig. 1) ; and the bit lines (130, fig. 11) are disposed in the second groove. [claim 4 ] The semiconductor structure according to claim 1, further comprising a plurality of second source/drain regions (120c,120a, fig. 11) , which are disposed in each of the active areas, and extend from the first surface to the second surface (fig. 11) . [claim 5 ] The semiconductor structure according to claim 4, further comprising a plurality of capacitors [0113] , which are disposed on the first surface, and each of which is electrically coupled with one of the second source/drain regions (120c, fig. 11) . [claim 6 ] The semiconductor structure according to claim 2, further comprising a first source/drain region (120c,120a, fig. 11) , which is disposed in the active areas, and extends from a bottom of the second groove to the first surface (fig. 11) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT AMAR MOVVA whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-9009 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 9AM-5PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Julio Maldonado can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-1864 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMAR MOVVA/ Primary Examiner, Art Unit 2898