DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moon (US 2013/0234240).
[claim 1] A semiconductor structure (fig. 1, specifically the embodiment of fig. 11 which slightly modifies the device of fig. 1 as explained in [0087]) comprising: a first substrate (120b, 120c, fig. 1 where 120c supports and contacts a contact plug of a lower electrode of a capacitor [0113], see also fig. 33), which has a first surface (top surface of 120c, fig. 1) and a second surface (bottom surface of 120b, fig. 1) opposite to the first surface, and comprises several discrete active areas (120b, 120c, fig. 1) arranged in a first direction (e.g. to the upper left in fig. 1) and parallel to a second direction (e.g. to the upper right in fig. 1), wherein the first direction is perpendicular to the second direction (fig. 1), an isolation layer (140, fig. 1, note that the embodiment of fig. 11 has 140 extend all the way to 110) is disposed between adjacent active areas, and the first surface and the second surface expose the isolation layer (fig. 1); a plurality of first grooves (filled in by 150, 160, and 170, fig. 1) which are disposed in the first substrate, extend from the first surface to the second surface, are arranged in the second direction (fig. 1), and run through the active areas along the first direction (fig. 1), as well as have a bottom with a distance less than the thickness of the isolation layer from the first surface (note that in fig. 11, the isolation layer 140 extends all the way to bottom of 120a, while the first groove only ext4ends to the bottom of 120b in fig. 1); a word line gate structure (160, fig. 1), which is disposed in the first grooves; a plurality of bit lines (130, fig. 11, [0087]), which are disposed on the second surface (bottom surface of 120b, fig. 11), arranged in the first direction (fig. 11), and parallel to the second direction (fig. 1), wherein one of the active areas is electrically coupled with one of the bit lines (fig. 11), wherein the isolation layers have a surface protruding from or flush with the second surface (bottom surface of isolation 140, fig. 1 directly above 130/125 is flush/at the same level as the bottom surface of 120b).
[claim 2] The semiconductor structure according to claim 1, wherein the isolation layers have a second groove (filled in by 120 and 130 in fig. 11) between each other (isolation layers 140, fig. 11), wherein the second groove exposes the second surface (fig. 11), is parallel to the second direction, and is arranged in the first direction (fig. 1)n; and the bit lines (130, fig. 11) are disposed in the second groove.
[claim 3] The semiconductor structure according to claim 1, further comprising a dielectric layer (172, fig. 11, [0087]), which is disposed on the second surface (on the bottom of 120b, fig. 11) and has a second groove (filled in by 120 and 130/172 in fig. 11) exposing a surface of the active areas therein (top of 120c is exposed by second grooves, fig. 11), wherein the second groove is parallel to the second direction and arranged in the first direction (fig. 1); and the bit lines (130, fig. 11) are disposed in the second groove.
[claim 4] The semiconductor structure according to claim 1, further comprising a plurality of second source/drain regions (120c,120a, fig. 11), which are disposed in each of the active areas, and extend from the first surface to the second surface (fig. 11).
[claim 5] The semiconductor structure according to claim 4, further comprising a plurality of capacitors [0113], which are disposed on the first surface, and each of which is electrically coupled with one of the second source/drain regions (120c, fig. 11).
[claim 6] The semiconductor structure according to claim 2, further comprising a first source/drain region (120c,120a, fig. 11), which is disposed in the active areas, and extends from a bottom of the second groove to the first surface (fig. 11).
Response to Arguments
Applicant's arguments filed 7-6-2026 have been fully considered but they are not persuasive.
Applicant argues that the elements 110/120a/120b/120c of Moon conform to the claimed substrate rather than 120b and 120c as noted in the rejection. However, a substrate is defined as underlying substance or layer (see e.g. https://en.thefreedictionary.com/substrate). In Moon 120b/120c supports and contacts a contact plug of a lower electrode of a capacitor [0113], see figs. 1 and 33. Therefore under the broadest reasonable interpretation, 120b/120c can be interpreted as the substrate.
Applicant further argues that amended claim 1 requires thinning the substrate and non-buried bit lines. However claim 1 says nothing about thinning the substate or non-buried bit lines.
Applicants arguments regarding the amendment are not persuasive since as noted in the rejection isolation 140, fig. 1 directly above 130/125 is flush/at the same level as the bottom surface of 120b.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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