DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7 and 9 are rejected under 35 U.S.C. 102a1 as being anticipated by Yamato et al. (US 4,808,951 cited by applicant).
Yamato (e.g. Fig. 1) teaches a filter including:
Regarding Claim 7, a dielectric substrate (e.g. 150); a plurality of resonators (e.g. 131-136) that are formed within the dielectric substrate and surrounded by shield conductors (e.g. 148 on the surrounding side walls and bottom 147): and a first input/output terminal and a second input/output terminal (e.g. see input/outputs 145 and 146) formed in a portion where the shield conductors are not formed. wherein: a first resonator (e.g. 131), which is a resonator nearest the first input/output terminal (e.g. 145) among the plurality of resonators, and a second resonator (e.g. 136), which is a resonator nearest the second input/output terminal (e.g. 146) among the plurality of resonators, are arranged in a positional relationship with point symmetry, with a center of the dielectric substrate in a planar view being a center of the point symmetry (e.g. the center point of the block between resonators 133 and 134 is the point of symmetry at the top of the block): a third resonator (e.g. 132) among the plurality of resonators and a fourth resonator (e.g. 135) among the plurality of resonators are arranged in a positional relationship with point symmetry, with the center of the dielectric substrate in the planar view being a center of the point symmetry; a position of the third resonator in a first direction, which is a longitudinal direction of the dielectric substrate, is between a position of the first resonator in the first direction and a position of the center of the dielectric substrate in the first direction (e.g. 132 is linearly aligned between 131 and the center point); and a position of the fourth resonator in the first direction is between a position of the second resonator in the first direction and the position of the center of the dielectric substrate in the first direction (e.g. 135 is linearly aligned between 136 and the center point), wherein: a plurality of capacitive coupling structures (e.g. 139-144) are included respectively between the resonators; each of the capacitive coupling structures includes a capacitive electrode extending from one resonator of the resonators and a capacitive electrode extending from another resonator of the resonators (e.g. 139-144 extend towards each other to capacitively couple, see Col. 2, lines 35-48); and a portion of the capacitive electrode extending from the one resonator and a portion of the capacitive electrode extending from the another resonator are near each other (see Fig. 1, the portions 139-144 are spaced to be near each adjacent coupling conductor).
Regarding claim 9, a dielectric substrate (e.g. 150); a plurality of resonators (e.g. 131-136) that are formed within the dielectric substrate and surrounded by shield conductors (e.g. 148 on the surrounding side walls and bottom 147): and a first input/output terminal and a second input/output terminal (e.g. see input/outputs 145 and 146) formed in a portion where the shield conductors are not formed, wherein: a first resonator (e.g. 131), which is a resonator nearest the first input/output terminal (e.g. 145) among the plurality of resonators, and a second resonator (e.g. 136), which is a resonator nearest the second input/output terminal (e.g. 146) among the plurality of resonators, are arranged in a positional relationship with point symmetry, with a center of the dielectric substrate in a planar view being a center of the point symmetry (e.g. the center point of the block between resonators 133 and 134 is the point of symmetry at the top of the block): a third resonator (e.g. 132) among the plurality of resonators and a fourth resonator (e.g. 135) among the plurality of resonators are arranged in a positional relationship with point symmetry, with the center of the dielectric substrate in the planar view being a center of the point symmetry; a position of the third resonator in a first direction, which is a longitudinal direction of the dielectric substrate, is between a position of the first resonator in the first direction and a position of the center of the dielectric substrate in the first direction (e.g. 132 is linearly aligned between 131 and the center point); and a position of the fourth resonator in the first direction is between a position of the second resonator in the first direction and the position of the center of the dielectric substrate in the first direction (e.g. 135 is linearly aligned between 136 and the center point), wherein: the dielectric substrate includes two principal surfaces (e.g. the top and bottom) and four side surfaces (e.g. the sides covered with shielding 148); a distance between a first side surface among the four side surfaces and the first resonator is less than a distance between the first side surface and the third resonator (e.g. resonator 131 is closer to the left side wall of the block in Fig. 1 than the distance between resonator 132 and the left side wall); and the filter further comprises a first capacitive coupling (e.g. 139) structure that includes a first electrode pattern, which is connected to the first resonator and protrudes toward the first side surface (e.g. 139 extends away from the resonator 131 to have an extension amount, i.e. width extension and length extension directions of the conductor 139, towards all of the respective side walls and the width direction is an extension towards the left side wall), and a second electrode pattern (e.g. 143), which is connected to the fourth resonator and protrudes toward the first side surface (e.g. 143 extends away from the resonator 135 to have an extension amount, i.e. width extension and length extension directions of the conductor 139, towards all of the respective side walls and the width direction is an extension towards the left side wall).
Allowable Subject Matter
Claims 1, 3-6, and 11-13 are allowed.
Claims 8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 7 and 9 have been considered but are moot because the new ground of rejection in view of Yamato newly cited by applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN E JONES whose telephone number is (571)272-1762. The examiner can normally be reached 9AM to 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Stephen E. Jones/ Primary Examiner, Art Unit 2843
Prosecution Insights