Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 9 June 2026 has been entered.
Claims 1, 3-29 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9 June 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3-29 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-24 of U.S. Patent No. 12,417,301 provided by the applicant in the IDS filed 9 June 2026, in view of Kupwade-Patilh et al (US 20160105402 A1) of record, in view of US 2015/0317563 A1 to INTERNATIONAL BUSINESS MACHINES CORPORATION (hereinafter "IBM") of record, further in view of Li et al (US 20170331763 A1) of record.
Claims of instant application
Claims of U.S. Patent 12,417,301
c1. A method, comprising:
receiving, at a central processing unit (CPU), a data request from a data requester to search or filter data stored in a repository, wherein at least a first portion of the stored data is homomorphically encrypted;
analyzing the stored data
without decrypting the homomorphically encrypted data to determine
an aggregated subset of data relevant to the data request, the aggregated subset of data comprising at least some of the homomorphically encrypted data, the analyzing including: identifying, during execution of the analysis, an operation to perform on the homomorphically encrypted data based on the received data request;
determining, during execution of the analysis, that the operation is performable using fewer processor cycles using a hardware accelerator selected from a plurality of hardware accelerators, than using the CPU; dispatching, from the CPU, during execution of the analysis, a command to the hardware accelerator to execute the operation; executing, at the hardware accelerator, during execution of the analysis, the operation on the homomorphically encrypted data; and receiving, at the CPU, during execution of the analysis, an output of the execution of the operation by the hardware accelerator, wherein the aggregated subset of data is based on the output; and
providing data request results that include or are derived from the aggregated subset of data to the data requester.
c1. A method, comprising: receiving data from a plurality of independent data sources; storing the data in a central repository;
homomorphically encrypting, prior to receiving a data request from a data requester, at least a first portion of the stored data in the central repository,
wherein the first portion of the stored data includes data from at least two of the plurality of independent data sources; receiving the data request from the data requester;
analyzing the stored data without decrypting the homomorphically encrypted data to determine an aggregated subset of data relevant to the data request, the aggregated subset of data comprising at least some of the homomorphically encrypted data; and
providing data request results that include or are derived from the aggregated subset of data to the data requester.
c27. A method, comprising:
receiving, at a central processing unit (CPU), a request from a requester to process data in a repository, wherein at least a first portion of the data is homomorphically encrypted;
processing the data without decrypting the homomorphically encrypted data to calculate a result of a computational operation, the processing including:
identifying, during execution of the analysis, an operation to perform on the homomorphically encrypted data based on the request;
determining, during execution of the analysis, that the operation is performable using fewer processor cycles using a hardware accelerator selected from the plurality of hardware accelerators, than using the CPU;
dispatching, from the CPU, during execution of the analysis, a command to the hardware accelerator to execute the operation on the homomorphically encrypted data to complete the processing;
executing, at the hardware accelerator, during execution of the analysis, the operation on the homomorphically encrypted data; and
receiving, at the CPU, during execution of the analysis, an output of the execution of the operation; and
returning the result of the computational operation, wherein the result of the computational operation includes or is based on the output of the operation executed by the hardware accelerator.
c1. A method, comprising: receiving data from a plurality of independent data sources; storing the data in a central repository;
homomorphically encrypting, prior to receiving a data request from a data requester, at least a first portion of the stored data in the central repository, wherein the first portion of the stored data includes data from at least two of the plurality of independent data sources; receiving the data request from the data requester; analyzing the stored data without decrypting the homomorphically encrypted data to determine an aggregated subset of data relevant to the data request, the aggregated subset of data comprising at least some of the homomorphically encrypted data; and providing data request results that include or are derived from the aggregated subset of data to the data requester.
As shown in the claims mapping above, claim 1 of the instant application essentially recites the limitations of claim 1 of the U.S. Patent with further details for the analyzing operation. Claim 27 essentially recites the limitations of claim 1 of the U.S. Patent with further details for the calculation operation.
However the details recited in the instant application although not claimed by the U.S. Patent, are obvious in view of the references of record Kupwade-Patilh et al (US 20160105402 A1), IBM Corp (US 20150317563 A1), Li et al (US 20170331763 A1) discussed in the Office Action mailed 24 September 2025.
Claims 22, 26 of the instant application respectively correspond to system and computer program product for method claim 1 thus are similarly rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Morshed, Toufique, Md Momin Al Aziz, and Noman Mohammed. "CPU and GPU accelerated fully homomorphic encryption." 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2020.
Abstract—Fully Homomorphic Encryption (FHE) is one of the most promising technologies for privacy protection as it allows an arbitrary number of function computations over encrypted data. However, the computational cost of these FHE systems limits their widespread applications. In this paper, our objective is to improve the performance of FHE schemes by designing efficient parallel frameworks. In particular, we choose Torus Fully Homomorphic Encryption (TFHE) as it offers exact results for an infinite number of boolean gate (e.g., AND, XOR) evaluations. We first extend the gate operations to algebraic circuits such as addition, multiplication, and their vector and matrix equivalents. Secondly, we consider the multi-core CPUs to improve the efficiency of both the gate and the arithmetic operations. Finally, we port the TFHE to the Graphics Processing Units (GPU) and device novel optimizations for boolean and arithmetic circuits employing the multitude of cores. We also experimentally analyze both the CPU and GPU parallel frameworks for different numeric representations (16 to 32-bit). Our GPU implementation outperforms the existing technique, and it achieves a speedup of 20× for any 32-bit boolean operation and 14.5× for multiplications.
Reis, Dayane, et al. "Computing-in-memory for performance and energy-efficient homomorphic encryption." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28.11 (2020): 2300-2313.
Abstract—Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory Processing (NMP) and Computing-in-memory (CiM) — paradigms where computation is done within the memory boundaries — represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications such as HE. This paper introduces CiM-HE, a Computing-in-memory (CiM) architecture that can support operations for the B/FV scheme, a somewhat homomorphic encryption scheme for general computation. CiM-HE hardware consists of customized peripherals such as sense amplifiers, adders, bit-shifters, and sequencing circuits. The peripherals are based on CMOS technology, and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against (i) two optimized CPU HE implementations, and (ii) an FPGA-based HE accelerator implementation. When compared to a CPU solution, CiM-HE obtains speedups between 4.6x and 9.1x, and energy savings between 266.4x and 532.8x for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-to-end tasks, i.e., mean, variance, linear regression, and inference are up to 1.1x, 7.7x, 7.1x, and 7.5x faster (and 301.1x, 404.6x, 532.3x, and 532.8x more energy efficient). Compared to CPU-based HE in a previous work, CiM-HE obtain 14.3x speed-up and >2600x energy savings. Finally, our design offers 2.2x speed-up with 88.1x energy savings compared to a state-of-the-art FPGA-based accelerator.
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 9 June 2026 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to UYEN T LE whose telephone number is (571)272-4021. The examiner can normally be reached M-F 9-5.
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/UYEN T LE/Primary Examiner, Art Unit 2156 25 June 2026
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