Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6, 8-9, 13, 15-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over “A Learning-Based Methodology for Accelerating Cell-Aware Model Generation” (2021-dHondt) in view of “An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults” (2019-Wang)
With respect to claim 1, dHondt teaches A method, executed by at least one processor of a computer (see FIG. 7, [page 1585]; note the purpose of method is to overcome limitations “in terms of run time, SPICE simulator licenses, CPU requirements and disk usage”, [page 1580 col 1 paragraph 1 lines 24-27], where the run time and CPU refers to an algorithm being executed by a processor on a computer), comprising (see FIG. 7, [page 1585], which is a combination of FIG. 1, [page 1580], and FIG. 2, [page 1581]): receiving a first set of test patterns generated for a first circuit design (in FIG. 2, see “CA models” as input to “CA-Matrix creation” resulting in “model training”, where the CA models are transformed into CA-matrices to perform model training, [page 1581]; this is the "training data" described in section B, [page 1581 col 1 paragraph 4 lines 1-4]; the training data set includes "Cell Patterns and responses", [page 1581 col 2 paragraph 2 bullet 1]; see also Table I, [page 1581]; note, this step connects to FIG. 7 through the ML models DB, [page 1585]), a second circuit design (In FIG. 7, this is the “new cell”, [page 1585]; in corresponding part of FIG. 2 see inputs to “New Data Creation”, where the box labeled library cells refers to a set of new cells that teach the second circuit design, [page 1581]), and a set of faults to be used for test pattern generation for the second circuit design (see bottom input line of FIG. 2, where the box labeled defect list refers to the set of faults to be used for test pattern generation for the second circuit design, [page 1581]); analyzing the first circuit design and the second circuit design to determine part of the second circuit design structurally similar to part of the first circuit design (in FIG. 7, see box labeled “structural analysis”, [page 1585]; “we first check if the ML-based generation will lead to high-quality CA models. This is done by analyzing the structure of the new cell and check whether the training dataset contains a cell with identical or similar structure (as presented in V.B), [page 1584 col 2 paragraph 5 lines 3-7]; and the reference back to V.B is “The analysis showed that all these cells had at least one cell in the training dataset with the same transistor structure or a very similar one, [page 1584 col 2 paragraph 2 lines 3-5]); modifying the first set of test patterns to generate a second set of test patterns for the second circuit design, the modifying comprising reusing values of bits in the first set of test patterns associated with the part of the first circuit design as values of bits in the second set of test patterns associated with the part of the second circuit design (In FIG. 7, the step ML-based CA model generation is referencing FIG. 2, [page 1585]; in FIG. 2, this is the inference step that results in the New CA models, [page 1581], where the stimulus/bits are being reused to detect faults in the second circuit “The second main step consists in using the Random Forest Classifier to make prediction (or inference) when a new data instance has to be evaluated. Prediction for a new data instance amounts to answer to the question: "Does this stimulus detects this defect affecting this cell?”, [page 1582 col 1 paragraph 2 lines 16-22]); ... performing test pattern generation for the subset of faults to generate a third set of test patterns for the second circuit design (In FIG. 7, this is each "new cell" that is not a known structure, where the flow results in "simulation-based CA model generation", [page 1585]; note this references FIG. 1, where the box labeled "cell-aware model generation" is the sub-operation for this step, [page 1580]); and storing the second set of test patterns and the third set of test patterns in a non-transitory computer-readable media (the resulting test patterns are stored in the storage labeled “CA Model” in FIG. 7, where you can see the second set coming from ML-based CA model generation, and the third set coming from Simulation-based CA model generation, [page 1585]; note the purpose of method is to overcome limitations “in terms of run time, SPICE simulator licenses, CPU requirements and disk usage”, [page 1580 col 1 paragraph 1 lines 24-27], where the disk usage refers to how much data is stored on a disk on a computer as a result of the algorithm).
Dhondt does not teach performing fault simulation on the second circuit design using the second set of test patterns and the set of faults to determine a subset of faults in the set of faults that cannot be detected by the second set of test patterns.
However, Wang teaches performing fault simulation on the second circuit design using the second set of test patterns and the set of faults to determine a subset of faults in the set of faults that cannot be detected by the second set of test patterns (see title “Incremental ATPG...”, [Title]; using single stuck on faults (SSAFs) as a starting point to simulate and get test patterns of double stuck on faults (DASF): “Therefore, starting from a compact test set for SSAF, the proposed method can be inductively employed to generate the test patterns for all the MSAF”, [page 1 col 2 paragraph 1 lines 12-14]; “A fault filtering is proposed to accelerate the fault selection process. It picks up the undetected DSAF by selecting two SSAF blocking the propagation path with each other, which means that they can no more be detected by their related test patterns, [page 1 col 2 paragraph 4 lines 2-6]; Therefore, the fault simulation needs to be performed to pick up the real undetected DSAF. By employing the fault filtering, the time to pick up the undetected DSAF can be greatly reduced, as shown in [7], [page 2 col 1 paragraph 1 lines 13-16]; see also FIG. 3, showing the step of “pick up all undetected n multiple faults, [page 4]).
It would have been obvious to one skilled in the art before the effective filing date to combine Dhondt with Wang because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Dhondt discloses a system that teaches all of the claimed features except for incrementally applying the testing techniques to find undetected faults. Wang teaches:
Instead of inspecting all the MSAF, the proposed method only selects the undetected faults by the test patterns for SSAF and then generates the additional test patterns, which can significantly reduce the runtime and compress the size of test patterns.
(Wang [page 1 col 2 paragraph 1 lines 3-7]).
A person having skill in the art would have a reasonable expectation of successfully reducing the runtime and compressing the size of test patterns in the system and method of dHondt by modifying dHondt with the incremental testing and simulation of Wang. Therefore, it would have been obvious to combine dHondt with Wang to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 2, Dhondt in view of Wang teaches all of the limitations of claim 1, as noted above. Dhondt further teaches wherein the analyzing comprises: comparing first output signatures and first input signatures for the first circuit design with second output signatures and second input signatures for the second circuit design (The logic function of these configurations is the same, [page 1584 col 2 paragraph 2 lines 11-12]).
With respect to claim 6, Dhondt in view of Wang teaches all of the limitations of claim 1, as noted above. Dhondt further teaches wherein the first output signatures and the first input signatures are stored with each of the first output signatures being associated with corresponding first input signatures in the first input signatures (see the CA-Matrix in Table I that shows how Cell inputs and responses are stored with one another, [page 1581], and see the repository labeled CA-matrices in FIG.2, showing how they are all stored together, [page 1581]), and wherein the second output signatures and the second input signatures are stored with each of the second output signatures being associated with corresponding second input signatures in the second input signatures (see the CA-Matrix in Table I that shows how Cell inputs and responses are stored with one another, [page 1581], and see the repository CA new data in FIG.2, showing how they are all stored together, [page 1581]).
With respect to claim 8, dHondt teaches One or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising (note the purpose of method is to overcome limitations “in terms of run time, SPICE simulator licenses, CPU requirements and disk usage”, [page 1580 col 1 paragraph 1 lines 24-27], where the disk usage refers to a non-transitory disk that stores the program and the results of the program as depicted in FIG. 7, [page 1585]; and also note the purpose of method is to overcome limitations “in terms of run time, SPICE simulator licenses, CPU requirements and disk usage”, [page 1580 col 1 paragraph 1 lines 24-27], where the run time and CPU refers to an algorithm being executed by a processor on a computer).
Regarding the rest of claim 8, incorporating the rejection of claim 1, claim 8 is rejected for a substantially similar rationale.
With respect to claim 9, incorporating the rejection of claim 2 and claim 8, claim 9 is rejected for a substantially similar rationale.
With respect to claim 13, incorporating the rejection of claim 6 and claim 9, claim 13 is rejected for a substantially similar rationale.
With respect to claim 15, dHondt teaches A system, comprising: one or more processors, the one or more processors programmed to perform a method, the method comprising (see FIG. 7, [page 1585]; note the purpose of method is to overcome limitations “in terms of run time, SPICE simulator licenses, CPU requirements and disk usage”, [page 1580 col 1 paragraph 1 lines 24-27], where the run time and CPU refers to an algorithm being executed by a processor on a computer).
Regarding the rest of claim 15, incorporating the rejection of claim 1, claim 15 is rejected for a substantially similar rationale.
With respect to claim 16, incorporating the rejection of claim 15 and claim 2, claim 16 is rejected for a substantially similar rationale.
With respect to claim 20, incorporating the rejection of claim 16 and claim 6, claim 20 is rejected for a substantially similar rationale.
Claim(s) 3, 5, 7, 10, 12, 14, 17, 19, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over “A Learning-Based Methodology for Accelerating Cell-Aware Model Generation” (2021-dHondt) in view of “An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults” (2019-Wang) in further view of “Diagnosis of Automata Failures: A Calculus and a Method” (1966-Roth)
With respect to claim 3, Dhondt in view of Wang teaches all of the limitations of claim 2, as noted above. Dhondt and Wang do not teach wherein the analyzing further comprises: generating the second output signatures using a forward propagation process traversing the second circuit design from inputs (primary inputs, scan cells, or both) to outputs (primary outputs, scan cells, or both); and generating the second input signatures using a backward propagation process traversing the second circuit design from the outputs to the inputs.
However, Roth teaches wherein the analyzing further comprises: generating the second output signatures using a forward propagation process traversing the second circuit design from inputs (primary inputs, scan cells, or both) to outputs (primary outputs, scan cells, or both); and generating the second input signatures using a backward propagation process traversing the second circuit design from the outputs to the inputs (There are two parts to the algorithm. In the first, a primitive D-cube tc of the failure is recursively intersected with primitive D-cubes of logic blocks seeking to form a D-CUbe tc which provides a "connected chain" of D-Coordinates to some primary output po (Steps 1 through 38). The second part, the CONSISTENCY operation (Steps 39 to 58), consists of intersecting this n-cube te with the singular cover S. This amounts to "driving backward", [page 287 col 1 paragraph 8]-[page 287 col 2 paragraph 1];... where the program is complete when the test vector g is “driven backwards” all the way to the primary inputs: “Finally control is shifted to Step 40 where the test for completion is made: is g contained in the set pi of primary inputs? With this, then, the description of the program is complete”, [page 289 col 1 paragraph 1 lines 25-28]).
It would have been obvious to one skilled in the art before the effective filing date to combine dHondt in view of Wang with Roth because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. DHondt discloses a system and method that teaches:
For this category, a cell-internal-fault dictionary or CA model (also referred to as CA fault model or CA test model in the literature), describing the detection conditions of each potential defect affecting a cell, is used [5-6]. These techniques are more efficient and can be used to guide the test pattern generation and CA diagnosis phases.
(dHondt [page 1580 col 1 paragraph 1 lines 18-23]).
Essentially, the “cell-aware” refers to knowledge of the “intra-cell” defects, and once these are characterized they can be used in the “test pattern generation” phase. The cell-aware model generation is taught by dHondt (see Fig. 7 of dHondt, [page 1585]), and once the faults at the gate level are determined, they can be used in the larger automatic test generation process as disclosed by Roth. Therefore, it would have been obvious to combine dHondt in view of Wang with Roth to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 5, dHondt in view of Wang teaches all of the limitations of claim 2, as noted above. DHondt teaches the first input signatures are derived ... wherein the second input signatures are derived... (see FIG. 7, note the method is repeated by the pink arrow on the right side labeled “reinforcement training”, the first time a new structure of circuit is encountered the new structure has to go through simulation-based CA model generation, then in future runs the signature in the CA model can be used in the ML-based CA model generation, [page 1585]).
DHondt and Wang do not teach ... based on propagating the first output signatures from outputs (primary outputs, scan cells, or both) of the first circuit design to inputs (primary inputs, scan cells, or both) of the first circuit design according to circuit structure of the first circuit design, and ... based on propagating the second output signatures from outputs (primary outputs, scan cells, or both).
However, Roth teaches wherein the first input signatures are derived based on propagating the first output signatures from outputs (primary outputs, scan cells, or both) of the first circuit design to inputs (primary inputs, scan cells, or both) of the first circuit design according to circuit structure of the first circuit design, and wherein the second input signatures are derived based on propagating the second output signatures from outputs (primary outputs, scan cells, or both) of the second circuit design to inputs (primary inputs, scan cells, or both) of the second circuit design according to circuit structure of the second circuit design (The second part, the CONSISTENCY operation (Steps 39 to 58), consists of intersecting this n-cube te with the singular cover S. This amounts to "driving backward", [page 287 col 1 paragraph 8]-[page 287 col 2 paragraph 1];... where the program is complete when the test vector g is “driven backwards” all the way to the primary inputs: “Finally control is shifted to Step 40 where the test for completion is made: is g contained in the set pi of primary inputs? With this, then, the description of the program is complete”, [page 289 col 1 paragraph 1 lines 25-28]; the process is repeated for the first circuit and the second circuit because the process of dHondt is repeated, as noted above).
It would have been obvious to one skilled in the art before the effective filing date to combine dHondt in view of Wang with Roth because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. DHondt discloses a system and method that teaches:
For this category, a cell-internal-fault dictionary or CA model (also referred to as CA fault model or CA test model in the literature), describing the detection conditions of each potential defect affecting a cell, is used [5-6]. These techniques are more efficient and can be used to guide the test pattern generation and CA diagnosis phases.
(DHondt [page 1580 col 1 paragraph 1 lines 18-23]).
Essentially, the “cell-aware” refers to knowledge of the “intra-cell” defects, and once these are characterized they can be used in the “test pattern generation” phase. The cell-aware model generation is taught by dHondt (see Fig. 7 of dHondt, [page 1585]), and once the faults at the gate level are determined, they can be used in the larger automatic test generation process as disclosed by Roth. Therefore, it would have been obvious to combine dHondt in view of Wang with Roth to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 7, Dhond in view of Wang teaches all of the limitations of claim 1, as noted above. DHondt and Wang do not teach wherein the modifying further comprises assigning random values to rest of bits of the second set of test patterns.
However, Roth teaches wherein the modifying further comprises assigning random values to rest of bits of the second set of test patterns (In the section “Calculus of D-Cubes” both a blank (also represented by an x) and a defect D are defined, see [page 280 col 1 paragraph 3]-[page 280 col 2 paragraph 3]; this limitation is about blanks/X, so note that the cube <0 x 0> stands for the two vertices: <0 0 0> and <0 1 0>, meaning X can be either 0 or 1, [page 280 col 1 paragraph 2 lines 12-19]; the section “Intersection of Cubes”, [page 282 col 1 paragraph 3], describes the Boolean operations for blanks, when an X intersects with 1, the result is 1; when X intersects with 0, the result is 0; but when X intersects with another X, then the result is X; eventually, when a test is generated, ALL of the D’s must be assigned the same value, but if there are any blanks left open, those can be assigned any arbitrary value: see the example “The fourth coordinate is blank (or x); this means that it may be given an arbitrary value”, [page 286 col 1 paragraph 4]; in the actual program, this is making sure that the vector g has values of 1 or 0, see “The last part of the algorithm, the CONSISTENCY operation, begins with step
39. This step defines a vector g consisting of all lines whose coordinates tc have values 1 or 0, [page 288 col 2 paragraph 6 lines 1-4]; and finally, see the end of the algorithm: “In any event in step 53,
g_n is deleted from g and those coordinates of g·S, whose value is 0 or 1 and for which tc = x, are added to g.”, [page 289 col 1 paragraph 1 lines 22-24]).
It would have been obvious to one skilled in the art before the effective filing date to combine dHondt in view of Wang with Roth because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. DHondt discloses a system and method that teaches:
For this category, a cell-internal-fault dictionary or CA model (also referred to as CA fault model or CA test model in the literature), describing the detection conditions of each potential defect affecting a cell, is used [5-6]. These techniques are more efficient and can be used to guide the test pattern generation and CA diagnosis phases.
(DHondt [page 1580 col 1 paragraph 1 lines 18-23]).
Essentially, the “cell-aware” refers to knowledge of the “intra-cell” defects, and once these are characterized they can be used in the “test pattern generation” phase. The cell-aware model generation is taught by dHondt (see Fig. 7 of dHondt, [page 1585]), and once the faults at the gate level are determined, they can be used in the larger automatic test generation process as disclosed by Roth. Therefore, it would have been obvious to combine dHondt in view of Wang with Roth to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 10, incorporating the rejection of claim 3 and claim 9, claim 10 is rejected for a substantially similar rationale.
With respect to claim 12, incorporating the rejection of claim 5 and claim 9, claim 12 is rejected for a substantially similar rationale.
With respect to claim 14, incorporating the rejection of claim 7 and claim 8, claim 14 is rejected for a substantially similar rationale.
With respect to claim 17, incorporating the rejection of claim 16 and claim 3, claim 17 is rejected for a substantially similar rationale.
With respect to claim 19, incorporating the rejection of claim 16 and claim 5, claim 19 is rejected for a substantially similar rationale.
With respect to claim 21, incorporating the rejection of claim 15 and claim 7, claim 21 is rejected for a substantially similar rationale.
Claim(s) 4, 11, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over “A Learning-Based Methodology for Accelerating Cell-Aware Model Generation” (2021-dHondt) in view of “An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults” (2019-Wang) in further view of “Diagnosis of Automata Failures: A Calculus and a Method” (1966-Roth) in further view of “The Power of Higher-Order Composition Languages in System Design” (2006-Cataldo)
With respect to claim 4, Dhondt in view of Wang and Roth teaches all of the limitations of claim 3, as noted above. Dhondt, Wang, and Roth do not teach wherein the generating the second output signatures comprises: assigning one or more prime numbers to the inputs; and assigning prime numbers, predefined output signature computation equations, and predefined input signature computation equations to devices in the second circuit design
However, Cataldo teaches wherein the generating the second output signatures comprises: assigning one or more prime numbers to the inputs (see chapter 3, [pages 67-93]; which first assigns each Boolean expression to a prime number (known as Gödel numbering), [page 78]; prime inputs are true or false, which are given numbers 1 and 2 in the example, [page 78 lines 2-3]); and assigning prime numbers, predefined output signature computation equations, and predefined input signature computation equations to devices in the second circuit design (see chapter 3, [pages 67-93]; which first assigns each Boolean expression to a prime number (known as Gödel numbering), [page 78], see the rest of the defined gates, [page 78 lines 4-11]; and then performs structural equivalence of circuits: “now show how the semantics function and the structural equivalence =_h can be used to prove that two components in the circuit language are the same”, [page 80 paragraph 1]).
It would have been obvious to one skilled in the art before the effective filing date to combine dHondt in view of Wang and Roth with Cataldo because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Under the section labeled “A. Motivation”, DHondt discloses:
The motivation behind the use of ML for defective cell characterization is the result of several observations made while performing comparisons between several CA models coming from different standard cell libraries and technologies:
(dHondt [page 1580 col 2 paragraph 4]), where one of the observations is:
For the same function, two cell structures are quite similar for two different technologies.
(dHondt [page 1581 col 1 paragraph 1 bullet 1]).
Cataldo teaches:
Scalability is a big problem in system design. Kuetzer et al. [34] suggest an “orthogonalization of concerns” to help manage this problem. The idea is to separate various aspects of system design to allow more effective exploration of possible solutions in the design space. As an example, function, or what the system should do, can be separated from architecture, or how the system should do it. Similarly, communication, or how components transfer data, can be separated from computation, or how components transform data.
(Cataldo [page 1]).
DHondt and Cataldo point out the same principle, that functions and structure can be separated and analyzed separately. Goedel’s numbering allows for the architecture to be described separate from the Boolean logic, (Cataldo [page 78]), which allows structural equivalence of circuits to be analyzed, (Cataldo [page 80 paragraph 1]). A person having skill in the art would have a reasonable expectation of successfully analyzing structural equivalence using Goedel numbering by modifying dHondt in view of Wang and Roth with the Goedel numbering and structural equivalence analysis of Cataldo. Therefore, it would have been obvious to combine dHondt in view of Wang and Roth with Cataldo to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 11, incorporating the rejection of claim 4 and claim 10, claim 11 is rejected for a substantially similar rationale.
With respect to claim 18, incorporating the rejection of claim 17 and claim 4, claim 18 is rejected for a substantially similar rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20060053357 A1 (Rajski) - Furthermore the fault simulation test pattern generating component (4712) can generate incremental test patterns, [0076] lines 9-10.
“An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits” (1981-Goel) – describing PODEM for the first time.
“Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs” (2009-Hapke) - describing CA-ATPG for the first time.
“Reducing the cost of test pattern generation by information reusing” (1993-Li) - In this paper, a new source of computational saving for test pattern generation, i.e., information reusing, is presented. The proposed technique can make full use of the pattern generation information from last pattern to derive a set of new tests by means of critical path transitions. By so doing, fault propagation procedure is no longer required in the next pattern generation process and the line justification procedure is simplified. Experiments using the ISCAS-85 benchmark circuits show that, when the technique is used with a deterministic test pattern generation algorithm (DTPG), computational cost is greatly reduced without a substantial increase in test length, [Abstract].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL MILLER whose telephone number is (408) 918-7548. The examiner can normally be reached on Monday-Friday from 11am to 5pm (PT). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang, can be reached at telephone number 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.M./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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