DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/12/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 5-14, 16 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the light emission control transistor" in lines 43-44 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the second reset transistor" in line 45 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites the limitation "the third reset transistor" in lines 46 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the compensation transistor" in lines 1-2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 recites the limitation "the first reset transistor" in line 2 of the claim. There is insufficient antecedent basis for this limitation in the claim.
Claim 6 is rejected based on dependence on claim 5.
Claims 2, 7-14, 16 and 21 are rejected based on dependence on claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 13-14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeong (US 2023/0027673 A1) in view of Luo et al. (US 2025/0166573 A1).
As to claim 1, Jeong teaches a display device, comprising: a display panel ([0030]:
display), comprising a plurality of subpixels ([0104]: pixels) each comprising a light-emitting
element (LD in Fig. 2) and a pixel driving circuit electrically connected to the light-emitting
element and comprising a plurality of transistors ([0067]: transistors T1, T2, T3, T4, T5, T6, and T7
connected to light emitting element LD)) and a plurality of gate driving units, at least comprising a
first gate driving unit (EMS1, EMS2, in Fig. 7) and a second gate driving unit (G1S1, G1S2, in Fig.
7) electrically connected to the plurality of subpixels (PX in Fig. 7; [0104]) and sharing a clock
signal (CK2 in Fig. 7) and a power supply signal (VHNL in Fig. 8; [0112]: configurations of
EMS1 to EMS4, GIS1 to GIS4 substantially the same),
wherein the first gate driving unit comprises a plurality of cascaded first gate driving
circuits (EMS1, EMS2 in Fig. 7) and is configured to output a plurality of first scanning signals to
the plurality of subpixels (pixels PX in Fig. 7; [0101]: output terminal 204 connected to pixel
rows) in response to a first startup signal (FLM1 in Fig. 7; [0115]), the clock signal (CK2 in Fig. 7),
and the power supply signal (VHNL in Fig. 8; [0112]: configurations of EMS1 to EMS4, GIS1 to GIS4
substantially the same; [0122-0123]);
the second gate driving unit comprises a plurality of cascaded second gate driving
circuits (GIS1, GIS2 in Fig. 7) and is configured to output a plurality of second scanning signals
to the plurality of subpixels (pixels PX in Fig. 7;[0103-0104]: output terminals connected to pixel
rows) in response to a second startup signal (FLM2 in Fig. 7; [0104]), the clock signal (CK2 in Fig. 7),
and the power supply signal (VHNL in Fig. 8; [0112]: configurations of EMS1 to EMS4, GIS1 to GIS4
substantially the same; [0122-0123]);
each of the subpixels comprises one of the transistors which is turned on in response
to a corresponding one of the first scanning signals ([0072]: gate electrode of transistor T5
connected to emission line; [0091]: transistor T5 turned on; [0101]: output terminal of EMS1
connected to emission line) and another one of transistors (T4 in Fig. 2) which is turned on in
response to a corresponding one of the second scanning signals ([0071];[0087]: turn-on level
(for example, a logic high level) may be applied to scan line GIq, fourth transistor T4 turned
on); and
the plurality of first gate driving circuits (EMS1, EMS2 in Fig. 7) and the plurality of
second gate driving circuits (GIS1, GIS2 in Fig. 7) are alternately arranged in a first direction
(vertical direction in Fig. 7),
wherein each of the first gate driving circuits (EMS1, EMS2 in Fig. 7;[0112]) comprises:
a first transistor (P4 in Fig. 8), comprising a control end electrically connected to one of a first clock signal line (CK1 line in Fig. 8) and a second clock signal line (CK2 in Fig. 8), and an input end electrically connected to a second power supply line (VLNL line in Fig. 8);
a second transistor (P12 in Fig. 8), comprising a control end electrically connected to an output end of the first transistor (P4 in Fig. 8), and an input end electrically connected to the other one of the first clock signal line (CK1 line in Fig. 8) and the second clock signal line (CK2 in Fig. 8);
a third transistor (P1 in Fig. 8), comprising a control end electrically connected to the output end of the first transistor (P4 in Fig. 8), and an input end electrically connected to a first power supply line
(VHNL in Fig. 8);
a fourth transistor (P6 in Fig. 8), comprising an output end electrically connected to the output end of the first transistor (P4 in Fig. 8), and an input end electrically connected to one of the first clock signal line (CK1 line in Fig. 8) and the second clock signal line (CK2 in Fig. 8);
a fifth transistor (P8 in Fig. 8), comprising a control end electrically connected to the other one of the first clock signal line (CK1 line in Fig. 8) and the second clock signal line (CK2 in Fig. 8), and an input end electrically connected to an output end of the second transistor (P12 in Fig. 8);
a sixth transistor (P5 in Fig. 8), comprising an input end electrically connected to one of the first clock signal line (CK1 line in Fig. 8) and the second clock signal line (CK2 in Fig. 8), and an output end electrically connected to an output end of the third transistor (P1 in Fig. 8);
a seventh transistor (P2 in Fig. 8), comprising an input end receiving a startup signal (FLM1 in Fig. 8), and an output end electrically connected to a control end of the fourth transistor (P6 in Fig. 8) and a control end of the sixth transistor (P5 in Fig. 8);
wherein the first gate driving unit (EMS1, EMS2 in Fig. 7;[0036] ;[0101]: output terminal 204
connected to pixel rows)) is electrically connected to a control end of the light emission control
transistor (T6 in Fig. 2;[0031]) of each of the plurality of subpixels ([0104]: pixels), the second gate
driving unit (GIS1, GIS2 in Fig. 7; [0103-0104]: output terminals connected to pixel rows) is electrically
connected to a control end of the second reset transistor (T7 in Fig. 2) of each of the plurality of
subpixels ([0104]: pixels), and a control end of the third reset transistor (T4 in Fig. 2) is electrically
connected to the control end of the second reset transistor (T7 in Fig. 2), but does not explicitly disclose
a thirteenth transistor, comprising a control end electrically connected to a reset signal line, an
input end electrically connected to the first power supply line, and an output end electrically connected
to the output end of the seventh transistor.
However, Luo et al. teaches a first transistor (T16 in Fig. 8a), comprising a control end electrically connected to one of a first clock signal line (CKA line in Fig. 8a) and a second clock signal line (CKB line in Fig. 8a), and an input end electrically connected to a second power supply line (VGL1 line in Fig. 8a);
a second transistor (T9 in Fig. 8a), comprising a control end electrically connected to an output end of the first transistor (T16 in Fig. 8a) (note that the claim does not recite “directly” connected. All the elements in Fig. 8a are connected to each other), and an input end electrically connected to the other one of the first clock signal line (CKA line in Fig. 8a) and the second clock signal line (CKB line in Fig. 8a);
a third transistor (T8 in Fig. 8a), comprising a control end electrically connected to the output end of the first transistor (T16 in Fig. 8a), and an input end electrically connected to a first power supply line (VGH in Fig. 8a);
a fourth transistor (T18 in Fig. 8a), comprising an output end electrically connected to the output end of the first transistor (T16 in Fig. 8a), and an input end electrically connected to one of the first clock signal line (CKA line in Fig. 8a) and the second clock signal line (CKB line in Fig. 8a);
a fifth transistor (T10 in Fig. 8a), comprising a control end electrically connected to the other one of the first clock signal line (CKA line in Fig. 8a) and the second clock signal line (CKB line in Fig. 8a), and an input end electrically connected to an output end of the second transistor (T9 in Fig. 8a);
a sixth transistor (T11 in Fig. 8a), comprising an input end electrically connected to one of the first clock signal line (CKA line in Fig. 8a) and the second clock signal line (CKB in Fig. 8a), and an output end electrically connected to an output end of the third transistor (T8 in Fig. 8a);
a seventh transistor (T2 in Fig. 8a), comprising an input end receiving a startup signal (STU signal
in Fig. 8a), and an output end electrically connected to a control end of the fourth transistor (T18 in Fig.
8a) and a control end of the sixth transistor (T11 in Fig. 8a),
a thirteenth transistor (T1 in Fig. 8a), comprising a control end electrically connected to a reset
signal line (RST line in Fig. 8a), an input end electrically connected to the first power supply line (VGH
line in Fig. 8a), and an output end electrically connected to the output end of the seventh transistor (T2
in Fig. 8a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify the device of Jeong with first gate driving circuit comprising a thirteenth
transistor with a control end electrically connected to a reset signal line, an input end electrically
connected to the first power supply line, and an output end electrically connected to the output end of
the seventh transistor as taught by Luo et al. in order to reduce generation of noise.
As to claim 2, Jeong in view of Luo et al. teaches the display device according to claim 1,
wherein the first gate driving circuits and the second gate driving circuits have a same circuit
topological structure (Jeong, [0112]: configurations of EMS1 to EMS4, GIS1 to GIS4 substantially the
same).
As to claim 13, Jeong in view of Luo et al. teaches wherein each of the first gate driving circuits (Jeong, EMS1, EMS2 in Fig. 7;[0112]) comprises:
an eighth transistor (Jeong, P3 in Fig. 8), comprising a control end electrically connected to the output end of the seventh transistor (Jeong, P2 in Fig. 8), an input end electrically connected to the first power supply line (Jeong, VHNL in Fig. 8), and an output end electrically connected to an output end of the fifth transistor (Jeong, P8 in Fig. 8);
a ninth transistor (Jeong, P11 in Fig. 8), comprising a control end electrically connected to the output end of the seventh transistor (Jeong, P2 in Fig. 8) and an input end electrically connected to the second power supply line (Jeong, VLNL line in Fig. 8);
a tenth transistor (Jeong, P10 in Fig. 8), comprising a control end electrically connected to the output end of the fifth transistor (Jeong, P8 in Fig. 8) and an input end electrically connected to the first power supply line (Jeong, VHNL in Fig. 8), wherein an output end of the ninth transistor (Jeong, P11 in Fig. 8) and an output end of the tenth transistor (Jeong, P10 in Fig. 8) are both electrically connected to a signal output end (Jeong, output terminal 204, emission line EM1 in Fig. 8) of a corresponding one of the first gate driving circuits (Jeong, EMS1, EMS2 in Fig. 7), and the signal output end is configured to output a scanning signal (Jeong, [0062]:emission signals, which are supplied to emission lines EM1; [0101]);
a first capacitor (Jeong, CN2 in Fig. 8), connected between the output end of the sixth transistor (Jeong, P5 in Fig. 8) and a control end of the sixth transistor (Jeong, P5 in Fig. 8);
a second capacitor (Jeong, CN1 in Fig. 8), connected between an output end of the second transistor (Jeong, P12 in Fig. 8) and the control end of the second transistor (Jeong, P12 in Fig. 8); and
a third capacitor (Jeong, CN3 in Fig. 8), connected between the input end of the tenth transistor (Jeong, P10 in Fig. 8) and the control end of the tenth transistor (Jeong, P10 in Fig. 8).
As to claim 14, Jeong in view of Luo et al. teaches the display device according to claim 17, wherein each of the first gate driving circuits (Jeong, EMS1, EMS2 in Fig. 7; [0112]) further comprises:
an eleventh transistor (Jeong, P9 in Fig. 8), comprising a control end electrically connected to the second power supply line (Jeong, VLNL line in Fig. 8), an input end, and an output end (Jeong, input end and output end of transistor P9 in Fig. 8), wherein the input end of the eleventh transistor (Jeong, the input end of transistor P9 in Fig. 8) is electrically connected to the output end of the first transistor (Jeong, P4 in Fig. 8), the output end of the eleventh transistor (Jeong, P9 in Fig. 8) electrically connected to the control end of the second transistor (Jeong, P12 in Fig. 8); and
a twelfth transistor (Jeong, P7 in Fig. 8), comprising a control end electrically connected to the second power supply line (Jeong, VLNL line in Fig. 8), an input end (Jeong, input end of transistor P7 in Fig. 8) electrically connected to the control end of the fourth transistor (Jeong, P6 in Fig. 8), the output end of the seventh transistor (Jeong, P2 in Fig. 8), and the control end of the eighth transistor (Jeong, P3 in Fig. 8), and an output end (Jeong, output end of transistor P7 in Fig. 8) electrically connected to the control end of the sixth transistor (Jeong, P5 in Fig. 8) and the control end of the ninth transistor (Jeong, P11 in Fig. 8).
As to claim 16, Jeong teaches the display device as discussed above, but does not explicitly disclose wherein each of the first gate driving circuits further comprises: a fourteenth transistor, comprising an input end electrically connected to the input end of the seventh transistor, and a control end electrically connected to the first clock signal line or the second clock signal line; a fifteenth transistor, comprising an input end electrically connected to an output end of the fourteenth transistor, and a control end electrically connected to the second power supply line; and a sixteenth transistor, comprising a control end electrically connected to the control end of the sixth transistor and an output end of the fifteenth transistor, an input end electrically connected to the control end thereof, and an output end electrically connected to the control end of the ninth transistor.
However, Luo et al. teaches a fourteenth transistor (T4 in Fig. 8a), comprising an input end (input end of T4 in Fig. 8a) electrically connected to the input end of the seventh transistor (T2 in Fig. 8a), and a control end (control end of T4 in Fig. 8a) electrically connected to the first clock signal line (CKA line in Fig. 8a) or the second clock signal line (CKB line in Fig. 8a);
a fifteenth transistor (T6 in Fig. 8a), comprising an input end (input end of T6 in Fig. 8a) electrically connected to an output end of the fourteenth transistor (T4 in Fig. 8a), and a control end (control end of T6 in Fig. 8a) electrically connected to the second power supply line (VGL1 in Fig. 8a); and a sixteenth transistor (T12 in Fig. 8a), comprising a control end (control end of T12 in Fig. 8a) electrically connected to the control end of the sixth transistor (T11 in Fig. 8a) and an output end of the fifteenth transistor(T6 in Fig. 8a), an input end (input end of T12 in Fig. 8a) electrically connected to the control end thereof (control end of T12 in Fig. 8a), and an output end (output end of T12 in Fig. 8a) electrically connected to the control end of the ninth transistor (T13 in Fig. 8a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify the device of Jeong such that each of the first gate driving circuits
further comprises a fourteenth transistor, fifteenth transistor, and a sixteenth transistor as taught by
Luo et al. in order to reduce generation of noise.
Allowable Subject Matter
Claims 5-12 and 21 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 04/12/2026 have been fully considered but they are not persuasive.
Examiner respectfully disagrees with the applicant’s argument that “Claim 1 is amended by rewriting the dependent claim 4 in independent form including all the limitations of the base claim” and “as such, the applicant respectfully submits that the currently amended claim 1 is patentable over Jeong in view of Luo.”
Claim 4 was objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 1 has not been amended by rewriting dependent claim 4 in independent form including all the limitation of the base claim and any intervening claims. All of the claim limitations of intervening claim 21 which claim 4 depended on, are not incorporated into claim 1.
The cited prior art teaches applicant’s claimed invention as noted in the office action above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
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