DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “memory device, configured to store…” in Claim 1; “computing device” in Claim 20; and “programmable hardware component” in Claim 21.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claim 19 is objected to because of the following informalities: Claim 19 recites the limitation “the first and second discrete means for processing are configured to obtain the respective firmware from the same means for storing information”. However, Claim 18, from which Claim 2 depends, recites the limitation “the first discrete means for processing, configured to access the firmware for the first discrete means for processing from the means for storing information” and “the second discrete means for processing, configured to access the firmware for the second discrete means for processing from the means for storing information”. Thus, Claim 18 necessarily requires that the first and second processing unit are configured to obtain the respective firmware from the same memory device, and Claim 19 does not provide any further limitation thereof. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5 recites the limitation “the memory device is a memory device comprising a plurality of predefined memory storage regions associated with the first discrete processor, with the memory device additionally comprising the separate second storage region with the firmware for the second discrete processor inserted into the plurality of predefined memory regions”. Applicant’s disclosure as originally filed does not recite any storage/insertion of the firmware for the second discrete processor into the plurality of predefined memory locations, which, as both disclosed and claimed, are associated with the first discrete processor.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 5 and 9-11 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “the memory device is a memory device comprising a plurality of predefined memory storage regions associated with the first discrete processor, with the memory device additionally comprising the separate second storage region with the firmware for the second discrete processor inserted into the plurality of predefined memory regions”. Claim 4, from which Claim 5 depends, recites the limitation “the memory device comprises a first storage region with the firmware for the first discrete processor and a separate second storage region with the firmware for the second discrete processor”. It is unclear as to how the plurality of predefined memory storage regions can have the firmware for the second discrete processor inserted therein, as the plurality of predefined memory storage regions are associated with the first discrete processor, and a separate second storage region is used to store the firmware for the second discrete processor.
Dependent claims inherit the indefiniteness of their parent claims and are rejected under the same reasoning.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 6, 8, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2021/0109762 to Feng et al. (“Feng”).
In reference to Claim 1, Feng discloses a computing device (See Figure 1 Number 100) comprising: a memory device (See Figure 1 Number 102), configured to store firmware (See Figure 1 FW#0 – FW#3 and Paragraph 24) for at least a first discrete processor (See Figure 1 Die#0 and Paragraph 24) and a second discrete processor (See Figure 1 Die#1 and Paragraph 24); the first discrete processor, configured to access the firmware for the first discrete processor from the memory device (See Figure 1 FW#0 and Paragraph 34), and to initialize itself using the firmware obtained from the memory device (See Paragraph 39); the second discrete processor, configured to access the firmware for the second discrete processor from the memory device (See Figure 1 FW#1 and Paragraph 34 [firmware is obtained from memory device via bus]), and to initialize itself using the firmware obtained from the memory device (See Paragraph 39).
In reference to Claim 4, Feng discloses the limitations as applied to Claim 1 above. Feng further discloses that the memory device comprises a first storage region with the firmware for the first discrete processor (See Figure 1 FW#1) and a separate second storage region with the firmware for the second discrete processor (See Figure 1 FW#2).
In reference to Claim 6, Feng discloses the limitations as applied to Claim 4 above. Feng further discloses that the memory device additionally comprise a separate third storage region (See Figure 1 FW#2) comprising firmware for a third discrete processor (See Figure 1 Die#2 and Paragraph 24).
In reference to Claim 8, Feng discloses the limitations as applied to Claim 1 above. Feng further discloses that the memory device comprises a shared region which includes codes for operating at least part of the first discrete processor and at least part of the second discrete processor (See Figure 1 FW#0 – FW#3 and Paragraph 24).
Claims 18 and 20 recite limitations which are substantially equivalent to those of Claim 1 and are rejected under similar reasoning.
In reference to Claim 19, Feng discloses the limitations as applied to Claim 18 above. Feng further discloses that the first and second discrete means for processing are configured to obtain the respective firmware from the same means for storing information (See Figure 1 and Paragraph 24).
Claim(s) 1, 4, 6-8, 12-13, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2021/0042035 to Futagi et al. (“Futagi”).
In reference to Claim 1, Futagi discloses a computing device (See Figure 1 Number 1) comprising: a memory device (See Figure 1 Number 30), configured to store firmware (See Figure 2 Number 31, 32-1, and 32-2 and Paragraph 21) for at least a first discrete processor (See Figure 1 Number 11 and Paragraph 21) and a second discrete processor (See Figure 1 Number 12-1 and Paragraph 21); the first discrete processor, configured to obtain the firmware for the first discrete processor from the memory device (See Figure 2 Number 31 and Paragraph 21), and to initialize itself using the firmware obtained from the memory device (See Paragraph 21); the second discrete processor, configured to obtain the firmware for the second discrete processor from the memory device (See Figure 2 Number 32-1 and Paragraph 21), and to initialize itself using the firmware obtained from the memory device (See Paragraph 21).
In reference to Claim 4, Futagi discloses the limitations as applied to Claim 1 above. Futagi further discloses that the memory device comprises a first storage region with the firmware for the first discrete processor (See Figure 2 Number 31) and a separate second storage region with the firmware for the second discrete processor (See Figure 2 Number 32-1).
In reference to Claim 6, Futagi discloses the limitations as applied to Claim 4 above. Futagi further discloses that the memory device additionally comprise a separate third storage region (See Figure 2 Number 32-2) comprising firmware for a third discrete processor (See Figure 2 Number 12-2 and Paragraph 21).
In reference to Claim 7, Futagi discloses the limitations as applied to Claim 4 above. Futagi further discloses that the memory device is configured to provide access to the first and second storage region such, that access by the second discrete processor is limited to the second storage region (See Paragraphs 21 and 51-55).
In reference to Claim 8, Futagi discloses the limitations as applied to Claim 1 above. Futagi further discloses that the memory device comprises a shared region (See Figure 4 Number 30A) which includes codes for operating at least part of the first discrete processor (See Figure 4 Number 33) and at least part of the second discrete processor (See Figure 4 Number 34-2).
In reference to Claim 12, Futagi discloses the limitations as applied to Claim 1 above. Futagi further discloses that the first and second discrete processor are configured to share one or more shared components of the computing device during a secure initialization procedure of the computing device, the one or more shared components comprising the memory device (See Figure 1 Number 30 and Paragraph 21).
In reference to Claim 13, Futagi discloses the limitations as applied to Claim 12 above. Futagi further discloses that the one or more shared components comprise at least one of security controller circuitry and flash controller circuitry (See Figure 1 Number 30 and Paragraph 18).
Claims 18 and 20 recite limitations which are substantially equivalent to those of Claim 1 and are rejected under similar reasoning.
In reference to Claim 19, Futagi discloses the limitations as applied to Claim 18 above. Futagi further discloses that the first and second discrete means for processing are configured to obtain the respective firmware from the same means for storing information (See Figure 2 Number 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futagi as applied to Claim 1 above, and further in view of knowledge commonly known in the art, as evidenced by US Patent Application Publication Number 2003/0028708 to Moran (“Moran”).
In reference to Claim 2, Futagi discloses the limitations as applied to Claim 1 above. Futagi further discloses that the memory device can be a flash memory device, but is silent as to the particular structure of the memory device, and does not explicitly disclose that the memory device is on a single die. Official Notice is taken that constructing a memory device, such as a flash memory device, on a single die is well known in the art, as evidenced by Moran (See Abstract and Paragraphs 7, 21, and 28).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Futagi using a well-known single die memory device as the memory device, resulting in the invention of Claim 2 because the simple substitution of well-known single die memory device as the memory device of Futagi would have yielded the predictable results of being more efficient for manufacturing and having lower costs (See Abstract and Paragraphs 7 and 21 of Moran).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futagi as applied to Claim 1 above, and further in view of knowledge commonly known in the art, as evidenced by US Patent Application Publication Number 2015/0288454 to Meinherz et al. (“Meinherz”) and admitted by Applicant to be prior art.
In reference to Claim 16, Futagi discloses the limitations as applied to Claim 1 above. Futagi further discloses that the first discrete processor is a central discrete processor (See Paragraph 19). However, Futagi does not explicitly disclose that the second discrete processor is one of a graphics discrete processor, a field-programmable gate array, a vision discrete processor, and an artificial intelligence accelerator. Official Notice is taken that the use of an FPGA to implement a discrete processor is well known in the art, as evidenced by Meinherz (See Paragraph 12). This has been admitted by Applicant to be prior art.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Futagi using a well-known FPGA as the second discrete processor, resulting in the invention of Claim 3, because the simple substitution of well-known FPGA as the second discrete processor of Futagi would have yielded the predictable results of having a faster time to market and a simpler design cycle (See Paragraph 12 of Meinherz).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futagi as applied to Claim 1 above, and further in view of US Patent Application Publication Number 2019/0220271 to Olderdissen et al. (“Olderdissen”).
In reference to Claim 9, Futagi discloses the limitations as applied to Claim 1 above. Futagi is silent as to the particular structure of the firmware, and does not explicitly disclose that the firmware for at least the second discrete processor comprises a device-specific portion and a device-agnostic portion, with the device-agnostic portion being configured to access the second discrete processor via a hardware abstraction layer being part of the device-specific portion. Olderdissen discloses firmware for a processor that comprises a device-specific portion and a device-agnostic portion, with the device-agnostic portion being configured to access the processor via a hardware abstraction layer being part of the device-specific portion (See Paragraphs 35-36, 41 and 46).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Futagi using the device specific and device agnostic firmware of Olderdissen, resulting in the invention of Claim 9, in order to abstract the interface between the firmware and the discrete processors, thus allowing for changes to be made in the firmware while maintaining compatibility with the discrete processors (See Paragraph 41 of Olderdissen).
In reference to Claim 10, Futagi and Olderhissen disclose the limitations as applied to Claim 9 above. Olderhissen further discloses that the device-specific portion comprises a device-specific static initialization portion (See Figure 1 Number 30 and Paragraph 41).
Claim(s) 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futagi as applied to Claims 1 and 12 above, and further in view of US Patent Application Publication Number 2018/0189223 to Nge et al. (“Nge”).
In reference to Claim 14, Futagi discloses the limitations as applied to Claim 12 above. Futagi is silent as to how the first and second discrete processors access the memory device, and does not explicitly disclose that at least one of the first discrete processor and the second discrete processor is configured to access the memory device via a master-attached flash sharing scheme. Nge discloses the use of a master-attached flash sharing scheme for accessing a memory device via an eSPI link by multiple processing devices (See Paragraph 16).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Futagi using the eSPI master attached flash sharing scheme of Nge to access the memory device by the first and second discrete processors, resulting in the invention of Claim 14, because Futagi is silent as to how the first and second discrete processors access the memory device, and the simple substitution of the eSPI master attached flash sharing scheme of Nge to access the memory device by the first and second discrete processors of Futagi would have yielded the predictable result of increasing security, simplifying manufacturing process, and minimizing cost (See Paragraph 16 of Nge).
In reference to Claim 15, Futagi discloses the limitations as applied to Claim 1 above. Futagi further discloses that the memory device is a flash-based memory device that is configured to communicate with the first and second discrete processors (See Paragraph 18). However, Futagi is silent as to how the first and second discrete processors communicate with the flash-based memory device, and does not explicitly disclose that the flash-based memory device that is configured to communicate with the first and second discrete processors via a serial peripheral interface. Nge discloses the use of a master-attached flash sharing scheme for accessing a memory device via an eSPI (enhanced serial peripheral interface) link by multiple processing devices (See Paragraph 16).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Futagi using the eSPI master attached flash sharing scheme of Nge to access the memory device by the first and second discrete processors, resulting in the invention of Claim 15, because Futagi is silent as to how the first and second discrete processors communicate with the flash-based memory device, and the simple substitution of the eSPI master attached flash sharing scheme of Nge to access the memory device by the first and second discrete processors of Futagi would have yielded the predictable result of increasing security, simplifying manufacturing process, and minimizing cost (See Paragraph 16 of Nge).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futagi as applied to Claim 1 above, and further in view of knowledge commonly known in the art, as evidenced by US Patent Application Publication Number 2009/0186195 to Spraker et al. (“Spraker”) and admitted by Applicant to be prior art.
In reference to Claim 16, Futagi discloses the limitations as applied to Claim 1 above. Futagi is silent as to the particular construction of the first and second discrete processors, and does not explicitly disclose that at least one of the first and the second discrete processor is a soldered-down processor. Official Notice is taken that the use of soldered down discrete processors is well known in the art, as evidenced by Spraker (See Paragraphs 13-16). This has been admitted by Applicant to be prior art.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Futagi using well known soldered-down discrete processors as the first and second discrete processors, resulting in the invention of Claim 16, because Futagi is silent as to the particular construction of the first and second discrete processors, and the simple substitution of well-known soldered-down discrete processors as the first and second discrete processors of Futagi would have yielded the predictable results of providing low thermal and electrical resistance (See Paragraph 16 of Spraker), and because devices such as CPUs benefit from a strong conductive metallic bond such as a solder bond (See Paragraph 13 of Spraker).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Futagi as applied to Claim 20 above, and further in view of knowledge commonly known in the art, as evidenced by US Patent Application Publication Number 2006/0206346 to Grand et al. (“Grand”) and admitted by Applicant to be prior art.
In reference to Claim 21, Futagi discloses the limitations as applied to Claim 20 above. Futagi is silent as to how the method is physically performed, and does not explicitly disclose a non-transitory, computer-readable medium having stored thereon a program code for performing the method of claim 20, when the computer program is executed on a computer, a processor, or a programmable hardware component. Official Notice is taken that the use of a non-transitory, computer-readable medium having stored thereon a program code for performing a method when the computer program is executed on a computer, a processor, or a programmable hardware component is well known in the art, as evidenced by Grand (See Paragraph 19). This has been admitted by Applicant to be prior art.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Futagi using well known non-transitory, computer-readable medium having stored thereon a program code for performing the method when the computer program is executed on a computer, a processor, or a programmable hardware component, resulting in the invention of Claim 21, because Futagi is silent as to how the method is physically performed, and the simple substitution of well-known non-transitory, computer-readable medium having stored thereon a program code for performing a method when the computer program is executed on a computer, a processor, or a programmable hardware component to perform the method of Futagi would have yielded the predictable results causing the computer to perform the process or task of the method in a manner that is well known (See Paragraph 19 of Grand).
Response to Arguments
Applicant's arguments filed 2 September 2025 have been fully considered but they are not persuasive.
Official Notice was taken in the previous Office Action. To adequately traverse such a finding, an Applicant must specifically point out the supposed errors in the Examiner’s action, which would include stating why the noticed fact is not considered to be common knowledge or well-known in the art. If the Applicant does not traverse the Examiner’s assertion of Official Notice, the common knowledge or well-known in the art statement is taken to be admitted prior art. (See MPEP 2144.03 C). The Examiner’s assertion of Official Notice is hereby taken to be admitted prior art due to the Applicant’s failure to traverse the assertion.
Applicant has argued that Feng does not disclose the slave dies (second discrete processors) accessing the storage device themselves (See Page 10). In response, the Examiner notes that while the claims recite the second discrete processor accessing the firmware from the memory device, the claims do not require that such access is direct access nor that the access is initiated by the second discrete processor. Applicant’s disclosure sets forth in Paragraph 38 (as published) “upon reset of the respective processing unit, the processing circuitry may be configured to fetch the firmware from the memory device (e.g., directly, or via the master processing unit, e.g., the CPU), and to execute the firmware to initialize the respective processing unit” [emphasis added]. Thus, the broadest reasonable interpretation consistent with Applicant’s disclosure includes indirect access via the first discrete processor. Thus, Feng discloses the aforementioned limitation, as the second discrete processor indirectly accesses the firmware stored in the memory device via the first discrete processor. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant has argued that Futagi does not disclose that the first and second processors are discrete processors as they are co-located within a single system-on-a-chip (See Page 11). In response, the Examiner notes that Paragraph 18 of Futagi, cited by Applicant, merely discloses an exemplary embodiment of a system-on-a-chip, but does not require such a structure. The broadest reasonable interpretation of “discrete” is ”individually separate and distinct”. As can be clearly seen in Figure 1 of Futagi, the individual processors 11, 12-1, and 12-2 are separate and distinct. Furthermore, even when implemented as a system-on-a-chip, the individual processors of Futagi are still separate and distinct from each other, and thus are “discrete”. Still further, Applicant’s disclosure states that the system may be implemented as a system-on-a-chip (See Paragraph 178 as published), thus supporting the interpretation of individual and distinct processors on a system-on-a-chip as being “discrete”.
Applicant has argued that the disclosure of Futagi is not directed to the boot process of a larger computing platform with physically separate, heterogenous processors, managing resources across a distributed heterogenous architecture, or booting a multi-chip, heterogenous platform (See Page 11). However, such features are not recited in the claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to disclose, either alone or in combination, all of the claimed limitations in the combinations as claimed. The most relevant prior art references are Feng, Futagi, and Olderdissen as applied in the above rejections. However, neither Feng, Futagi, nor Olderdissen disclose that the second discrete processor is configured to use the device-specific static initialization portion to initialize itself to the point of communication with the first discrete processor, and to continue initialization using the device-agnostic portion with help of the first discrete processor. Furthermore, such a feature would not have been obvious to one of ordinary skill in the art in view of the prior art.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175