DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 05/26/2026 has been considered by Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 9-10, 16, 18, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al (US 2021/0375212 A1) in view of Xiang et al (US 2019/0325815 A1) and Kim et al (US 2022/0148511 A1).
Claim 1, Kwon (Fig. 1-12) discloses a driving circuit (STi; Fig. 7 and 8; wherein figures show a gate driving circuit), comprising a first node control circuit (T6; Fig. 8), a second node control circuit (T13; Fig. 8) and a first output circuit (T7; Fig. 8);
wherein the second node control circuit (T13; Fig. 8) is electrically connected to a first low voltage input terminal (105; Fig. 8), a first node (N2; Fig. 8) and a second node (N5; Fig. 8) respectively (T13; Fig. 8), and is configured to control (T13; Fig. 8) to connect the first node (N2; Fig. 8) and the second node (N5; Fig. 8) under the control of a low voltage signal (VGL; Fig. 8) provided by the first low voltage input terminal (105; Fig. 8);
the first node control circuit (T6; Fig. 8) is electrically connected to a second low voltage input terminal (106; Fig. 8), a first clock signal line (108; Fig. 8) and the first node (N2; Fig. 8) respectively (T6; Fig. 8), and is configured to control (T6; Fig. 8) to connect the first node (N2; Fig. 8) and the second low voltage input terminal (106; Fig. 8) under the control of a first clock signal (CLK1; Fig. 8) provided by the first clock signal line (102; Fig. 8);
the first output circuit (T7; Fig. 8) is electrically connected to a pull-down node (N3; Fig. 8), a driving signal output terminal (104; Fig. 8) and a third low voltage input terminal (106; Fig. 8) respectively (T7; Fig. 8), and is configured to control (T7; Fig. 8) to connect the driving signal output terminal (104; Fig. 8) and the third low voltage input terminal (106; Fig. 8) under the control of a potential of the pull-down node (N3; Fig. 8).
Kwon does not expressly disclose low voltage signals respectively provided by at least two of the first low voltage input terminal, the second low voltage input terminal and the third low voltage input terminal are different from each other.
Xiang (Fig. 3-9) discloses low voltage signals (VGL1 and VGL2: Fig. 6) respectively provided by at least two of the first low voltage input terminal (VGL1(VGL2); Fig. 6; wherein figure shows gate of transistor M11 connected to one of the low voltages VGL1(VGL2)), the second low voltage input terminal (VGL1; Fig. 6; wherein figure shows electrode of transistor M4 connected to the low voltage VGL1) and the third low voltage input terminal (VGL2; Fig. 6; wherein figure shows electrode of transistor M10 connected to the low voltage VGL2) are different from each other (Paragraph [0025]; wherein discloses “the low level of the first low level signal can be less than the low level of the second low level signal”).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon’s driving circuit by applying different voltage signals, as taught by Xiang, so to use a driving circuit with different voltage signals for protecting transistors in the second node control module 2, thereby maintaining the second node control module 2 in normal operation (Paragraph [0025]).
Kwon in view of Xiang does not expressly disclose wherein the driving circuit further comprises a second output circuit;
the second output circuit is respectively electrically connected to a pull-up node, a first high voltage input terminal and the driving signal output terminal, and is configured to control to connect the first high voltage input terminal and the driving signal output terminal under the control of a potential of the pull-up node;
wherein the driving circuit further comprises a pull-up node control circuit;
the pull-up node control circuit is electrically connected to the third node, a second high voltage input terminal and the pull-up node, and is configured to control to connect the second high voltage input terminal and the pull-up node under the control of a potential of the third node;
high voltage signal provided by the first high voltage input terminal and high voltage signal provided by the second high voltage input terminal are different from each other;
wherein when transistors included in the second output circuit are p-type transistors, voltage value of the high voltage signal provided by the first high voltage input terminal is smaller than voltage value of the high voltage signal provided by the second high voltage input terminal;
when transistors included in the second output circuit are n-type transistors, voltage value of the high voltage signal provided by the first high voltage input terminal is greater than voltage value of the high voltage signal provided by the second high voltage input terminal.
Kim (Fig. 1-12) discloses wherein the driving circuit (Fig. 5A and 5B) further comprises a second output circuit (S9; Fig. 5A);
the second output circuit (S9; Fig. 5A) is respectively electrically connected to a pull-up node (X7; Fig. 5A), a first high voltage input terminal (VGH2; Fig. 5) and the driving signal output terminal (OUTPUT; Fig. 5A), and is configured to control to connect (Paragraph [0082]) the first high voltage input terminal (VGH2; Fig. 5A) and the driving signal output terminal (OUTPUT; Fig. 5A) under the control of a potential of the pull-up node (X7; Fig. 5A);
wherein the driving circuit (Fig. 5A and 5B) further comprises a pull-up node control circuit (S8; Fig. 8);
the pull-up node control circuit (S8; Fig. 5A) is electrically connected to the third node (X4; Fig. 5A), a second high voltage input terminal (VGH1; Fig. 5A) and the pull-up node (X7; Fig. 5A), and is configured to control to connect (Paragraph [0081]; wherein discloses “The eighth switching element S8 may control a connection between the first high voltage VGH1 and a seventh node X7 in response to a signal from the fourth node X4”) the second high voltage input terminal (VGH1; Fig. 5A) and the pull-up node (X7; Fig. 5A) under the control of a potential of the third node (X4; Fig. 5A);
high voltage signal provided by the first high voltage input terminal (VGH2; Fig. 5A) and high voltage signal provided by the second high voltage input terminal (VGH1; Fig. 5A) are different from each other (Fig. 3; Paragraph [0073]; wherein discloses “The power supply voltage generator 200 may generate a first high voltage VGH1, a first low voltage VGL1, a second high voltage VGH2 less or lower than the first high voltage VGH1, and a second low voltage VGL2 greater or higher than the first low voltage VGL1, based on the input voltage”);
wherein when transistors included in the second output circuit (S9; Fig. 5A; wherein figure discloses p-type transistor; wherein Kim reads on at least the p-type embodiment claimed invention) are p-type transistors (S9; Fig. 5A), voltage value of the high voltage signal provided by the first high voltage input terminal (VGH2; Fig. 5A) is smaller than (Fig. 3; Paragraph [0073]; wherein discloses “The power supply voltage generator 200 may generate a first high voltage VGH1, a first low voltage VGL1, a second high voltage VGH2 less or lower than the first high voltage VGH1, and a second low voltage VGL2 greater or higher than the first low voltage VGL1, based on the input voltage”) voltage value of the high voltage signal provided by the second high voltage input terminal (VGH1; Fig. 5A);
when transistors included in the second output circuit are n-type transistors, voltage value of the high voltage signal provided by the first high voltage input terminal is greater than voltage value of the high voltage signal provided by the second high voltage input terminal.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang’s driving circuit by applying a voltage difference, as taught by Kim, so to use a driving circuit with a voltage difference for providing a method of operating a display device to reduce power consumed by a scan driver and an emission driver (Paragraph [0006]).
Claim 16, Kwon (Fig. 1-12) discloses a driving circuit (Fig. 7 and 8), comprising a first transistor (T6; Fig. 8), a second transistor (T13; Fig. 8), an output reset transistor (T7; Fig. 8) and a sixth transistor (T12; Fig. 8);
wherein a control electrode of the first transistor (T6; Fig. 8) is electrically connected to a first clock signal line (102; Fig. 8), a first electrode of the first transistor (T6; Fig. 8) is electrically connected to a second low voltage input terminal (106; Fig. 8), and a second electrode of the first transistor (T6; Fig. 8) is electrically connected to a first node (N2; Fig. 8);
a control electrode of the second transistor (T13; Fig. 8) is electrically connected to a first low voltage input terminal (105; Fig. 8), a first electrode of the second transistor (T13; Fig. 8) is electrically connected to the first node (N2; Fig. 8), and a second electrode of the second transistor (T13; Fig. 8) is electrically connected to a second node (N5; Fig. 8);
the first output circuit includes the output reset transistor (T7; Fig. 8), a control electrode of the output reset transistor (T7; Fig. 8) is electrically connected to a pull-down node (N3; Fig. 8), a first electrode of the output reset transistor (T7; Fig. 8) is electrically connected to a driving signal output terminal (104; Fig. 8), and a second electrode of the output reset transistor (T7; Fig. 8) is electrically connected to a third low voltage input terminal (106; Fig. 8);
a control electrode of the sixth transistor (T12; Fig. 8) is electrically connected to a fourth low voltage input terminal (106; Fig. 8), a first electrode of the sixth transistor (T12; Fig. 8) is electrically connected to a third node (N1; Fig. 8), and a second electrode of the sixth transistor (T12; Fig. 8) is electrically connected to the pull-down node (N3; Fig. 8);
the first low voltage input terminal (105; Fig. 8), the second low voltage input terminal (106; Fig. 8), the third low voltage input terminal (106; Fig. 8) and the fourth low voltage input terminal (106; Fig. 8) are not completely the same (Fig. 8; wherein figure shows at least the gate of transistor T13 is connected to a low voltage input terminal 105 which is different than the low voltage terminal 106 connected to transistors T7, T12, and T6; therefore reading on the claimed limitation).
Kwon does not expressly disclose low voltage signals respectively provided by the first low voltage input terminal, the second low voltage input terminal, the third low voltage input terminal and the fourth low voltage input terminal are not the same.
Xiang (Fig. 3-9) discloses low voltage signals (VGL1 and VGL2; Fig. 6) respectively provided by the first low voltage input terminal (VGL1(VGL2); Fig. Fig. 6; wherein figure shows gate electrode connected to one of the low voltages VGL1(VGL2)), the second low voltage input terminal (VGL1; Fig. 6; wherein figure shows electrode of M4 connected to low voltage VGL1), the third low voltage input terminal (VGL2; Fig. 6; wherein figure shows electrode of M10 connected to VGL2) and the fourth low voltage input terminal are not the same (Fig. 6; wherein embodiment discloses the use of two different low voltages being applied to the driving circuit and therefore broadly reads on the claim limitation of the terminals be not the same).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon’s driving circuit by applying different voltage signals, as taught by Xiang, so to use a driving circuit with different voltage signals for protecting transistors in the second node control module 2, thereby maintaining the second node control module 2 in normal operation (Paragraph [0025]).
Kwon in view of Xiang does not expressly disclose wherein the driving circuit further comprises an output transistor and a third transistor;
a control electrode of the output transistor is electrically connected to a pull-up node, a first electrode of the output transistor is electrically connected to a first high voltage input terminal, and a second electrode of the output transistor is electrically connected to the driving signal output terminal;
a control electrode of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to a second high voltage input terminal, and a second electrode of the third transistor is electrically connected to the pull-up node;
high voltage signal provided by the first high voltage input terminal and high voltage signal provided by the second high voltage input terminal are different from each other;
wherein when the output transistor is a p-type transistor, voltage value of the high voltage signal provided by the first high voltage input terminal is smaller than voltage value of the high voltage signal provided by the second high voltage input terminal;
when the output transistor is an n-type transistor, voltage value of the high voltage signal provided by the first high voltage input terminal is greater than voltage value of the high voltage signal provided by the second high voltage input terminal.
Kim (Fig. 1-12) discloses wherein the driving circuit (Fig. 5A and 5B) further comprises an output transistor (S9; Fig. 5A) and a third transistor (S8; Fig. 5A);
a control electrode of the output transistor (S9; Fig. 5A) is electrically connected to a pull-up node (X7; Fig. 5A), a first electrode of the output transistor (S9; Fig. 5A) is electrically connected to a first high voltage input terminal (VGH2; Fig. 5A), and a second electrode of the output transistor (S9; Fig. 5A) is electrically connected to the driving signal output terminal (OUTPUT; Fig. 5A);
a control electrode of the third transistor (S8; Fig. 5A) is electrically connected to the third node (X4; Fig. 5A), a first electrode of the third transistor (S8; Fig. 5A) is electrically connected to a second high voltage input terminal (VGH1; Fig. 5A), and a second electrode of the third transistor (S8; Fig. 5A) is electrically connected to the pull-up node (X7; Fig. 5A);
high voltage signal provided by the first high voltage input terminal (VGH2; Fig. 5A) and high voltage signal provided by the second high voltage input terminal (VGH1; Fig. 5A) are different from each other (Fig. 3; Paragraph [0073]; wherein discloses “The power supply voltage generator 200 may generate a first high voltage VGH1, a first low voltage VGL1, a second high voltage VGH2 less or lower than the first high voltage VGH1, and a second low voltage VGL2 greater or higher than the first low voltage VGL1, based on the input voltage”);
wherein when the output transistor (S9; Fig. 5A; wherein figure discloses p-type transistor; wherein Kim reads on at least the p-type embodiment claimed invention) is a p-type transistor (S9; Fig. 5A), voltage value of the high voltage signal provided by the first high voltage input terminal (VGH2; Fig. 5A) is smaller than (Fig. 3; Paragraph [0073]; wherein discloses “The power supply voltage generator 200 may generate a first high voltage VGH1, a first low voltage VGL1, a second high voltage VGH2 less or lower than the first high voltage VGH1, and a second low voltage VGL2 greater or higher than the first low voltage VGL1, based on the input voltage”) voltage value of the high voltage signal provided by the second high voltage input terminal (VGH1; Fig. 5A);
when the output transistor is an n-type transistor, voltage value of the high voltage signal provided by the first high voltage input terminal is greater than voltage value of the high voltage signal provided by the second high voltage input terminal.
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang’s driving circuit by applying a voltage difference, as taught by Kim, so to use a driving circuit with a voltage difference for providing a method of operating a display device to reduce power consumed by a scan driver and an emission driver (Paragraph [0006]).
Claim 6, Kwon (Fig. 1-12) discloses further comprising a pull-down node control circuit (T12; Fig. 8);
wherein the pull-down node control circuit (T12; Fig. 8) is electrically connected to a fourth low voltage input terminal (106; Fig. 8), a third node (N1; Fig. 8), and the pull-down node (N3; Fig. 8), and is configured to control (T12; Fig. 8) to connect the third node (N1; Fig. 8) and the pull-down node (N3; Fig. 8) under the control of a low voltage signal (VGL; Fig. 8) provided by the fourth low voltage input terminal (106; Fig. 8);
the fourth low voltage input terminal (106; Fig. 8) is different from at least one of the first low voltage input terminal (105; Fig. 8), the second low voltage input terminal, or the third low voltage input terminal,
wherein the pull-down node control circuit (T12; Fig. 8) comprises a sixth transistor (T12; Fig. 8);
a control electrode of the sixth transistor (T12; Fig. 8) is electrically connected to the fourth low voltage input terminal (106; Fig. 8), a first electrode of the sixth transistor (T12; Fig. 8) is electrically connected to the third node (N1; Fig. 8), and a second electrode of the sixth transistor (T12; Fig. 8) is electrically connected to the pull-down node (N3; Fig. 8).
Claim 9, Kwon (Fig. 1-12) discloses wherein the first node control circuit (T6; Fig. 8) comprises a first transistor (T6; Fig. 8), and the second node control circuit (T13; Fig. 8) comprises a second transistor (T13; Fig. 8);
a control electrode of the first transistor (T6; Fig. 8) is electrically connected to the first clock signal line (102; Fig. 8), a first electrode of the first transistor (T6; Fig. 8) is electrically connected to the second low voltage input terminal (106; Fig. 8), and a second electrode of the first transistor (T6; Fig. 8) is electrically connected to the first node (N2; Fig. 8);
a control electrode of the second transistor (T13; Fig. 8) is electrically connected to the first low voltage input terminal (105; Fig. 8), a first electrode of the second transistor (T13; Fig. 8) is electrically connected to the first node (N2; Fig. 8), and a second electrode of the second transistor (T13; Fig. 8) is electrically connected to the second node (N5; Fig. 8);
the first output circuit (T7; Fig. 8) includes an output reset transistor (T7; Fig. 8);
a control electrode of the output reset transistor (T7; Fig. 8) is electrically connected to the pull-down node (N3; Fig. 8), a first electrode of the output reset transistor (T7; Fig. 8) is electrically connected to the driving signal output terminal (104; Fig. 8), and a second electrode of the output reset transistor (T7; Fig. 8) is electrically connected to the third low voltage input terminal (106; Fig. 8).
Claim 10, Kwon (Fig. 1-12) discloses wherein the second output circuit comprises an output transistor (T8; Fig. 8), and the pull-up node control circuit comprises a third transistor (T11; Fig. 8) and a first capacitor (C3; Fig. 8);
a control electrode of the output transistor (T8; Fig. 8) is electrically connected to the pull-up node (N4; Fig. 8), a first electrode of the output transistor (T8; Fig. 8) is electrically connected to the first high voltage input terminal (107; Fig. 8), and a second electrode of the output transistor (T8; Fig. 8) is electrically connected to the driving signal output terminal (104; Fig. 8);
a control electrode of the third transistor (T11; Fig. 8) is electrically connected to the third node (N1; Fig. 8), a first electrode of the third transistor (T11; Fig. 8) is electrically connected to the second high voltage input terminal (107; Fig. 8), and a second electrode of the third transistor (T11; Fig. 8) is electrically connected to the pull-up node (N4; Fig. 8);
a first electrode plate of the first capacitor (C3; Fig. 8) is electrically connected to the pull-up node (N4; Fig. 8), and a second electrode plate of the first capacitor (C3; Fig. 8) is electrically connected to the first high voltage input terminal (107; Fig. 8).
Claim 18, Kwon (Fig. 1-12) discloses a display panel (1000; Fig. 1), comprising the driving circuit (Fig. 7 and 8) according to claim 1 (see rejection to claim 1 above);
wherein the display panel (1000; Fig. 1) further comprises a display driving chip (STi; Fig. 7 and 8);
the first low voltage input terminal is electrically connected to a first low voltage line, the second low voltage input terminal is electrically connected to a second low voltage line, the third low voltage input terminal is electrically connected to a third low voltage line, and the first low voltage line, the second low voltage line, and the third low voltage line are electrically connected to different pins of the display driving chip, and the display driving chip is configured to provide a first low voltage signal for the first low voltage line, provide a second low voltage signal for the second low voltage line, and provide a third low voltage signal for the third low voltage line; or,
the first low voltage input terminal (105; Fig. 7 and 8) is electrically connected to the first low voltage line (GPL1; Fig. 7 and 8), the second low voltage input terminal (106; Fig. 7 and 8) and the third low voltage input terminal (106; Fig. 7 and 8) are both electrically connected to the second low voltage line (GPL2; Fig. 7 and 8), and the first low voltage line (GPL1; Fig. 7 and 8) and the second low voltage line (GPL2; Fig. 7 and 8) are respectively electrically connected to different pins (105 and 106; Fig. 7 and 8) of the display driving chip (STi; Fig. 7 and 8), the display driving chip (STi; Fig. 7 and 8) is configured to provide the first low voltage signal (VGL; Fig. 7 and 8) for the first low voltage line (GPL1; Fig. 7 and 8), and provide the second low voltage signal (VGL; Fig. 7 and 8) for the second low voltage line (GPL2; Fig. 7 and 8); or,
both the first low voltage input terminal and the second low voltage input terminal are electrically connected to the first low voltage line, the third low voltage input terminal is electrically connected to the second low voltage line, and the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driving chip, the display driving chip is configured to provide the first low voltage signal for the first low voltage line, and provide the second low voltage signal for the second low voltage line; or,
both the first low voltage input terminal and the third low voltage input terminal are electrically connected to the first low voltage line, the second low voltage input terminal is electrically connected to the second low voltage line, and the first low voltage line and the second low voltage line are respectively electrically connected to different pins of the display driving chip, and the display driving chip is configured to provide the first low voltage signal for the first low voltage line, and provide the second low voltage signal for the second low voltage line.
Claim 23, Kwon (Fig. 1-12) discloses a display device (1000; Fig. 1) comprising the driving circuit (Fig. 7 and 8) according to claim 1 (see rejection to claim 1 above).
Claims 2-3, 5, 7-8, 11-12, 14-15, 17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al (US 2021/0375212 A1) in view of Xiang et al (US 2019/0325815 A1) and Kim et al (US 2022/0148511 A1) as applied to claims 1 and 16 above, and further in view of In (US 2021/0383760 A1).
Claim 2, Kwon in view of Xiang and Kim discloses the driving circuit according to claim 1.
Kwon in view of Xiang and Kim does not expressly disclose further comprising a fourth node control circuit;
the fourth node control circuit is electrically connected to the first node, a fourth node and a fourth high voltage input terminal, and is configured to control to connect the fourth node and the fourth high voltage input terminal under the control of a potential of the first node;
the first high voltage input terminal is different from the fourth high voltage input terminal.
In (Fig. 1-17) discloses further comprising a fourth node control circuit (T2; Fig. 5);
wherein the fourth node control circuit (T2; Fig. 5) is electrically connected to the first node (Fig. 5; wherein figure shows gate of transistor T2 connected to a node which is equal to the previously claimed first node), a fourth node (Fig. 5; wherein figure shows an electrode of transistor T2 connected to a node between transistor T3 and capacitor C3) and a fourth high voltage input terminal (IN2; Fig. 5), and is configured to control (T2; Fig. 5) to connect the fourth node (Fig. 5; wherein figure shows an electrode of transistor T2 connected to a node between transistor T3 and capacitor C3) and the fourth high voltage input terminal (IN2; Fig. 5) under the control of a potential of the first node (Fig. 5; wherein figure shows gate of transistor T2 connected to a node which is equal to the previously claimed first node);
the first high voltage input terminal (IN1; Fig. 5) is different from the fourth high voltage input terminal (IN2; Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 3, In (Fig. 1-17) discloses further comprising a third node reset circuit (T13; Fig. 5);
wherein the third node reset circuit (T13; Fig. 5) is respectively electrically connected to a reset line (RST; Fig. 5), a third high voltage input terminal (IN1; Fig. 5) and a third node (Fig. 5; wherein figure shows an electrode of transistor T13 connected to a node between transistor T12 and transistor T1), and is configured to control (T13; Fig. 5) to connect the third high voltage input terminal (IN1; Fig. 5) and the third node (Fig. 5; wherein figure shows an electrode of transistor T13 connected to a node between transistor T12 and transistor T1) under the control of a reset signal (RST; Fig. 5) provided by the reset line (RST; Fig. 5);
the third high voltage input terminal (IN1; Fig. 5) is different from at least one of the first high voltage input terminal or the fourth high voltage input terminal (IN2; Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 5, In (Fig. 1-17) discloses further comprising a pull-up node control circuit (T8; Fig. 9);
wherein the pull-up node control circuit (T8; Fig. 9) is electrically connected to the third node (Fig. 9; wherein figure shows gate of transistor T8 connected to a node between transistor T12 and transistor T1), the second high voltage input terminal (IN2; Fig. 9) and the pull-up node (QB; Fig. 9), and is configured to control (T8; Fig. 9) to connect the second high voltage input terminal (IN2; Fig. 9) and the pull-up node (QB; Fig. 9) under the control of the potential of the third node Fig. 9; wherein figure shows gate of transistor T8 connected to a node between transistor T12 and transistor T1);
the second high voltage input terminal (IN2; Fig. 9) is different from the third high voltage input terminal (IN1; Fig. 9).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 7, Kwon (Fig. 1-12) discloses further comprising a fifth node control circuit (T10 and C2; Fig. 8) and a pull-up node control circuit (T9; Fig. 8);
wherein the fifth node control circuit (T10 and C2; Fig. 8) is electrically connected to the second node (N5; Fig. 8), a fifth node (Fig. 8; wherein figure shows an electrode of transistor T10 connected to node between capacitor C2 and transistor T9), and a second clock signal line (CLK2; Fig. 8), and is configured to connect (T10; Fig. 8) the second clock signal line (CLK2; Fig. 8) and the fifth node (Fig. 8; wherein figure shows an electrode of transistor T10 connected to node between capacitor C2 and transistor T9) under the control of the potential of the second node (N5; Fig. 8), and control (C2; Fig. 8) a potential of the fifth node (Fig. 8; wherein figure shows an electrode of transistor T10 connected to node between capacitor C2 and transistor T9) according to the potential of the second node (N5; Fig. 8);
the pull-up node control circuit (T9; Fig. 8) is also electrically connected to the fifth node (Fig. 8; wherein figure shows an electrode of transistor T9 connected to node between capacitor C2 and transistor T10), the second clock signal line (CLK2; Fig. 8) and the pull-up node (N4; Fig. 8), and is configured to control (T9; Fig. 8) to connect the fifth node (Fig. 8; wherein figure shows an electrode of transistor T9 connected to node between capacitor C2 and transistor T10) and the pull-up node (N4; Fig. 8) under the control of a second clock signal (CLK2; Fig. 8) provided by the second clock signal line (103; Fig. 8) and maintain the potential of the pull-up node (N4; Fig. 8) under the control of the second clock signal (CLK2; Fig. 8) provided by the second clock signal line (103; Fig. 8).
Claim 8, Kwon (Fig. 1-12) discloses further comprising a third node control circuit (T4; Fig. 8);
wherein the third node control circuit (T4; Fig. 8) is electrically connected to a start voltage terminal (SSP; Fig. 8), the first clock signal line (102; Fig. 8) and the third node (N1; Fig. 8), and is configured to control (T4; Fig. 8) to connect the start voltage terminal (SSP; Fig. 8) and the third node (N1; Fig. 8) under the control of the first clock signal (CLK1; Fig. 8) provided by the first clock signal line (102; Fig. 8);
the first node control circuit (T5; Fig. 8) is also electrically connected to the third node (N1; Fig. 8), the first node (N2; Fig. 8), and the first clock signal line (102; Fig. 8), and is configured to control (T5; Fig. 8) to connect the first node (N2; Fig. 8) and the first clock signal line (102; Fig. 8) under the control of the potential of the third node (N1; Fig. 8).
Kwon in view of Xiang and Kim does not expressly disclose the fourth node control circuit is also electrically connected to the pull-down node and the second clock signal line, and is configured to control to connect the fourth node and the second clock signal line under the control of the potential of the pull-down node and control the potential of the fourth node according to the potential of the pull-down node.
In (Fig. 1-17) discloses the fourth node control circuit (T3 and C3; Fig. 5) is also electrically connected to the pull-down node (Q; Fig. 5) and the second clock signal line (CIN2; Fig. 5), and is configured to control (T3; Fig. 5) to connect the fourth node (Fig. 5; wherein figure shows an electrode of transistor T3 connected to a node between transistor T2 and capacitor C3) and the second clock signal line (CIN2; Fig. 5) under the control of the potential of the pull-down node (Q; Fig. 5) and control (C3; Fig. 5) the potential of the fourth node (Fig. 5; wherein figure shows an electrode of transistor T3 connected to a node between transistor T2 and capacitor C3) according to the potential of the pull-down node (Q; Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 11, In (Fig. 1-17) discloses wherein the third node reset circuit comprises a fourth transistor (T13; Fig. 5);
a control electrode of the fourth transistor (T13; Fig. 5) is electrically connected to the reset line (RST; Fig. 5), a first electrode of the fourth transistor (T13; Fig. 5) is electrically connected to the third high voltage input terminal (IN1; Fig. 5), and a second electrode of the fourth transistor (T13; Fig. 5) is electrically connected to the third node (Fig. 5; wherein figure shows an electrode of transistor T13 connected to a node between transistor T12 and transistor T1).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 12, In (Fig. 1-17) discloses wherein the fourth node control circuit comprises a fifth transistor (T2; Fig. 5);
a control electrode of the fifth transistor (T2; Fig. 5) is electrically connected to the first node (Fig. 5; wherein figure shows gate of transistor T2 connected to a node which is equal to the previously claimed first node), a first electrode of the fifth transistor (T2; Fig. 5) is electrically connected to the fourth high voltage input terminal (IN2; Fig. 5), and a second electrode of the fifth transistor (T2; Fig. 5) is electrically connected to the fourth node (Fig. 5; wherein figure shows an electrode of transistor T2 connected to a node between transistor T3 and capacitor C3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 14, Kwon (Fig. 1-12) discloses wherein the fifth node control circuit comprises a seventh transistor (T10; Fig. 8) and a second capacitor (C2; Fig. 8);
the pull-up node control circuit further comprises an eighth transistor (T9; Fig. 8);
a control electrode of the seventh transistor (T10; Fig. 8) is electrically connected to the second node (N5; Fig. 8), a first electrode of the seventh transistor (T10; Fig. 8) is electrically connected to the second clock signal line (103; Fig. 8), and a second electrode of the seventh transistor (T10; Fig. 8) is electrically connected to a fifth node (Fig. 8; wherein figure shows an electrode of transistor T10 connected to node between capacitor C2 and transistor T9);
a first electrode plate of the second capacitor (C2; Fig. 8) is electrically connected to the second node (N5; Fig. 8), and a second electrode plate of the second capacitor (C2; Fig. 8) is electrically connected to the fifth node (Fig. 8; wherein figure shows electrode of capacitor C2 is connected to node between transistors T10 and T9);
a control electrode of the eighth transistor (T9; Fig. 8) is electrically connected to the second clock signal line (103; Fig. 8), a first electrode of the eighth transistor (T9; Fig. 8) is electrically connected to the fifth node (Fig. 8; wherein an electrode of transistor T9 is connected to node between capacitor C2 and transistor T10), and a second electrode of the eighth transistor (T9; Fig. 8) is electrically connected to the pull-up node (N4; Fig. 8).
Claim 15, Kwon (Fig. 1-12) discloses wherein the first node control circuit further comprises a ninth transistor (T5; Fig. 8);
a control electrode of the ninth transistor (T5; Fig. 8) is electrically connected to the third node (N1; Fig. 8), a first electrode of the ninth transistor (T5; Fig. 8) is electrically connected to the first clock signal line (102; Fig. 8), and a second electrode of the ninth transistor (T5; Fig. 8) is electrically connected to the first node (N2; Fig. 8);
the third node control circuit includes an eleventh transistor (T4; Fig. 8);
a control electrode of the eleventh transistor (T4; Fig. 8) is electrically connected to the first clock signal line (102; Fig. 8), a first electrode of the eleventh transistor (T4; Fig. 8) is electrically connected to the start voltage terminal (SSP; Fig. 8), and a second electrode of the eleventh transistor (T4; Fig. 8) is electrically connected to the third node (N1; Fig. 8).
In (Fig. 1-17) discloses the fourth node control circuit further includes a tenth transistor (T3; Fig. 5) and a third capacitor (C3; Fig. 5);
a control electrode of the tenth transistor (T3; Fig. 5) is electrically connected to the pull-down node (Q; Fig. 5), a first electrode of the tenth transistor (T3; Fig. 5) is electrically connected to the second clock signal line (CIN2; Fig. 5), and a second electrode of the tenth transistor (T3; Fig. 5) is electrically connected to the fourth node (Fig. 5; wherein figure shows an electrode of transistor T3 connected to a node between capacitor C3 and transistor T2);
a first electrode plate of the third capacitor (C3; Fig. 5) is electrically connected to the pull-down node (Q; Fig. 5), and a second electrode plate of the third capacitor (C3; Fig. 5) is electrically connected to the fourth node (Fig. 5; wherein figure shows an electrode of capacitor C3 connected to a node between transistors T2 and T3);
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 17, Kwon discloses the driving circuit according to claim 16.
Kwon in view of Xiang and Kim does not expressly disclose further comprising a fourth transistor and a fifth transistor;
wherein a control electrode of the fourth transistor is electrically connected to a reset line, a first electrode of the fourth transistor is electrically connected to a third high voltage input terminal, and a second electrode of the fourth transistor is electrically connected to the third node;
a control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to a fourth high voltage input terminal, and a second electrode of the fifth transistor is electrically connected to a fourth node.
In (Fig. 1-17) discloses further comprising a fourth transistor (T13; Fig. 5) and a fifth transistor (T2; Fig. 5);
wherein a control electrode of the fourth transistor (T13; Fig. 5) is electrically connected to a reset line (RST; Fig. 5), a first electrode of the fourth transistor (T13; Fig. 5) is electrically connected to a third high voltage input terminal (IN1; Fig. 5), and a second electrode of the fourth transistor (T13; Fig. 5) is electrically connected to the third node (Fig. 5; wherein figure shows electrode of transistor T13 is connected to node between transistors T1 and T12);
a control electrode of the fifth transistor (T2; Fig. 5) is electrically connected to the first node (Fig. 5; wherein figure shows gate electrode of transistor T2 is connected to node between transistors T5 and T11), a first electrode of the fifth transistor (T2; Fig. 5) is electrically connected to a fourth high voltage input terminal (IN2; Fig. 5), and a second electrode of the fifth transistor (T2; Fig. 5) is electrically connected to a fourth node (Fig. 5; wherein figure shows electrode of T2 connected to node between capacitor C3 and transistor T3).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 19, Kwon in view of Xiang and Kim discloses comprising the driving circuit according to claim 1.
Kwon in view of Xiang and Kim does not expressly disclose a display panel, comprising the driving circuit according to claim 4;
wherein the display panel further comprises a display driving chip;
the first high voltage input terminal is electrically connected to a first high voltage line, and the second high voltage input terminal is electrically connected to a second high voltage line;
the first high voltage line and the second high voltage line are respectively electrically connected to different pins of the display driving chip, the display driving chip is configured to provide a first high voltage signal for the first high voltage line, and the display driving chip is configured to provide a second high voltage signal for the second high voltage line.
In (Fig. 1-17) discloses a display panel (DD; Fig. 1),
wherein the display panel (DD; Fig. 1) further comprises a display driving chip (GC_ST1; Fig. 4);
the first high voltage input terminal (IN2; Fig. 4) is electrically connected to a first high voltage line (VGHL2; Fig. 4), and the second high voltage input terminal (IN1; Fig. 4) is electrically connected to a second high voltage line (VGHL1; Fig. 4);
the first high voltage line (VGHL2; Fig. 4) and the second high voltage line (VGHL1; Fig. 4) are respectively electrically connected to different pins (IN1 and IN2; Fig. 4) of the display driving chip (GC_ST1; Fig. 4), the display driving chip (GC_ST1; Fig. 4) is configured to provide a first high voltage signal (VGH2; Fig. 5) for the first high voltage line (VGHL2; Fig. 5), and the display driving chip (GC_ST1; Fig. 4) is configured to provide a second high voltage signal (VGH1; Fig. 5) for the second high voltage line (VGHL1; Fig. 5).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al (US 2021/0375212 A1) in view of Xiang et al (US 2019/0325815 A1) and Kim et al (US 2022/0148511 A1) as applied to claim 1 above, and further in view of In (US 2021/0383760 A1) and Wang et al (US 2019/0304374 A1).
Claim 20, Kwon (Fig. 1-12) discloses a display substrate (1; Fig. 4), comprising a base substrate (1; Fig. 4) and the driving circuit (Fig. 7 and 8) according to claim 1 (see rejection to claim 1 above) arranged on the base substrate (1; Fig. 4),
wherein the driving circuit (STi; Fig. 7 and 8) comprises a first low voltage line (GPL2; Fig. 8), a second low voltage line (GPL1; Fig. 8), a first high voltage line (GPL3; Fig. 8), a first node control circuit (T6; Fig. 8), a second node control circuit (T13; Fig. 8), a first output circuit (T7; Fig. 8), a second output circuit (T8; Fig. 8), a pull-up node control circuit (T11; Fig. 8), a pull-down node control circuit (T12; Fig. 8), and a fifth node control circuit (T10; Fig. 8) and a third node control circuit (T4; Fig. 8);
the second low voltage line (GPL1; Fig. 8) is arranged on a side of the driving circuit (STi; Fig. 7 and 8) away from a display area (100; Fig. 4), and the first low voltage line (GPL2; Fig. 8) is arranged on a side of the driving circuit (STi; Fig. 7 and 8) close to the display area (100; Fig. 4);
the first high voltage line (VGH1; Fig. 5) and the second high voltage line (VGH2; Fig. 5) are arranged between a first circuit part (Fig. 5; wherein figure shows each VGH signal line provided to the driving circuits which is arranged in the middle of each driving circuit) included in the driving circuit (220, 240, and 260; Fig. 5) and a second circuit part (Fig. 5; wherein figure shows each VGH signal line provided to the driving circuits which is arranged in the middle of each driving circuit) included in the driving circuit (220, 240, and 260; Fig. 5);
the first circuit part (Fig. 8) includes the first node control circuit (T6; Fig. 8), the second node control circuit (T13; Fig. 8), the pull-up node control circuit (T11; Fig. 8), the pull-down node control circuit (T12; Fig. 8), and the fifth node control circuit (T10; Fig. 8), and the third node control circuit (T4; Fig. 8). the second circuit part (Fig. 8) includes the first output circuit (T7; Fig. 8) and the second output circuit (T8; Fig. 8);
the second circuit part (Fig. 8) is arranged between the first high voltage line (GPL3; Fig. 8) and the first low voltage line (GPL2; Fig. 8).
Kwon in view of Xiang and Kim does not expressly disclose wherein the driving circuit comprises a first high voltage line, a second high voltage line, and a fourth node control circuit;
the first circuit part includes the fourth node control circuit, and the third node control circuit;
wherein the driving circuit further includes a third node reset circuit, and the first circuit part includes the third node reset circuit.
In (Fig. 1-17) discloses wherein the driving circuit (Fig. 4 and 5) comprises a first high voltage line (VGHL1; Fig. 5), a second high voltage line (VGHL2; Fig. 5), and a fourth node control circuit (T2 and T3; Fig. 5);
the first circuit part (Fig. 5) includes the fourth node control circuit (T2 and T3; Fig. 5);
wherein the driving circuit (Fig. 4 and 5) further includes a third node reset circuit (T13; Fig. 8), and the first circuit part (Fig. 5) includes the third node reset circuit (T13; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang and Kim’s driving circuit by applying different high voltage input terminals, as taught by In, so to use a driving circuit with different high voltage input terminals for providing a display device capable of reducing or preventing a luminance difference due to a fluctuation of a gate signal (Paragraph [0008]).
Kwon in view of Xiang, Kim, and In does not expressly disclose the first circuit part is arranged between the second low voltage line and the second high voltage line.
Wang (Fig. 7 and 8) discloses the first circuit part (Fig. 7) is arranged between the second low voltage line (VGL: Fig. 8; wherein figure shows a second VGL arrange away from output) and the second high voltage line (VGH; Fig. 8).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Kwon in view of Xiang, Kim, and In’s driving circuit by applying a circuit arrangement, as taught by Wang, so to use a driving circuit with a circuit arrangement for a display device using a sub-gate electrode, thus preventing current leakage, and reducing a dead space (Paragraph [0006]).
Response to Arguments
Applicant's arguments with respect to claims 1-3, 5-12, 14-20, and 23 have been considered but are moot in view of the new ground(s) of rejection.
In view of arguments, the references of Kwon et al (US 2021/0375212 A1), Xiang et al (US 2019/0325815 A1), Kim et al (US 2022/0148511 A1), In (US 2021/0383760 A1), and Wang et al (US 2019/0304374 A1) have been used for new ground rejection.
Claims 1 and 16 are rejected in view of newly discovered reference(s) to Kim et al (US 2022/0148511 A1).
Conclusion
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/Adam J Snyder/Primary Examiner, Art Unit 2623 06/08/2026
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