Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to communications filed on 10/2/2023. Accordingly, claims 1- 14 are pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1- 14—in particular Independent claims 1, 6, 8 & 14—are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claims recite processing (and analyzing, determining for claim 8 and/or providing for claim 6--respectively) data. These limitations, as drafted, are processes that, under its broadest reasonable interpretation, covers performance of the limitations in the mind. But for the processing device and memory language, the claims encompass a user simply comparing the collected data to a predetermined/configurable threshold in his/her mind. The mere nominal recitation of a generic bus, processor and memory does not take the claim limitation out of the mental processes grouping. Thus, the claims recite a mental process which is an abstract idea.
This judicial exception is not integrated into a practical application. The claims recite the elements of processing and that a generic computer performs this step. The processing step is recited at a high level of generality (i.e., as a general means of receiving/transmitting and storing data for processing), and as such they amount to mere data gathering, which is a form of insignificant extra-solution activity. The processor that performs the processing step is recited at a high level of generality and merely automates the process. Each of the additional limitations are no more than mere instructions to apply the exception using a generic computer component (the processor). The combination of these additional elements are no more than mere instructions to apply the exception using a generic computer component (the processor). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application. The claims are directed to an abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed with respect to Step 2A Prong Two, the additional elements in the claim amount to no more than mere instructions to apply the exception using a generic computer component. The same analysis applies here in 2B and does not provide an inventive concept.
For the processing steps were considered extra-solution activity in Step 2A, this has been re-evaluated in Step 2B and determined to be well-understood, routine, conventional activity in the field. The background does not provide any indication that the processor is anything other than a generic, off-the-shelf computer component, and the Symantec, TLI, and OIP Techs. court decisions (MPEP 2106.05(d)(II)) indicate that mere collection or receipt of data over a network is a well‐understood, routine, and conventional function when it is claimed in a merely generic manner (as it is here). For these reasons, there is no inventive concept. The claim is not patent eligible.
As per claims 2-7 & 9-13, they all depend from claims 1, 6, 8 and 14 and as such are rejected for having the same deficiencies as those detailed above with respect to claims 1, 6, 8 & 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1- 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al (hereinafter Wang, “Big data driven Hierarchical Digital Twin Predictive Remanufacturing paradigm: Architecture, control mechanism, application scenario and benefits”).
Wang discloses:
1: A device having a digital twin of an electronic component, wherein the device has
at least one data medium having reprocessing data regarding the component and at least one processor for processing the reprocessing data (see Wang at least fig. 1-10 and Abstract, Introduction; BDHDTPREMfg, CPS-Digital twin).
2: wherein the data medium is a data memory (see Wang at least fig. 1-10 and Abstract, Introduction; data processing and storage, data warehouse, data integration).
3: wherein the reprocessing data comprise information pertaining to at least one group member selected from the following group: bill of materials of the electronic component, work steps for manufacturing the electronic component, prices of raw materials used to manufacture the component, possible reprocessing methods for the electronic component and legal requirements for reprocessing the electronic component (see Wang at least fig. 1-10 and Abstract, Introduction).
4: wherein the reprocessing data comprise up-to-date reprocessing data (see Wang at least fig. 1-10 and Abstract, Introduction).
5: wherein the device is equipped with a data interface for providing the reprocessing data of the data medium (see Wang at least fig. 1-10 and Abstract, Introduction).
6: A method for producing a device having a digital twin as claimed in claim 1, wherein the reprocessing data are provided (see Wang at least fig. 1-10 and Abstract, Introduction).
7: wherein the digital twin of the device is produced while the electronic component is being designed (see Wang at least fig. 1-10 and Abstract, Introduction).
8: A method of using a device having a digital twin as claimed in claim 1 to determine a reprocessing process of an electronic component, wherein the following work steps are carried out: a) analyzing the reprocessing data of the data medium and b) using the analysis to determine the reprocessing process, wherein the processor is used to analyze the reprocessing data and/or determine the reprocessing process (see Wang at least fig. 1-10 and Abstract, Introduction).
8: wherein the method is carried out repeatedly (see Wang at least fig. 1-10 and Abstract, Introduction).
10: wherein the reprocessing process is determined while the electronic component is being designed (see Wang at least fig. 1-10 and Abstract, Introduction).
11: wherein up-to-date reprocessing data are provided for analyzing the reprocessing data (see Wang at least fig. 1-10 and Abstract, Introduction).
12: wherein at least one item of information selected from the following group is evaluated for analyzing the reprocessing data: information pertaining to the general feasibility of the reprocessing of the component, information pertaining to expenditure and/or costs of the reprocessing of the component, information pertaining to legal requirements for the reprocessing of the component, information pertaining to the extent of the reprocessing of the component, information pertaining to possible reprocessing processes for the component, information about costs of the reprocessing of the component and information pertaining to the profit that can be expected as a result of the reprocessing of the component (see Wang at least fig. 1-10 and Abstract, Introduction).
13: wherein at least one mathematical optimization method is used for analyzing the reprocessing data and/or for determining the reprocessing process (see Wang at least fig. 1-10 and Abstract, Introduction).
14: A method for reprocessing an electronic component, wherein the following work steps are carried out: a') using the device having a digital twin as claimed in claim 1 to select the reprocessing process and b') carrying out the reprocessing process (see Wang at least fig. 1-10 and Abstract, Introduction).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MACEEH ANWARI whose telephone number is 571-272-7591. The examiner can normally be reached on 9-9:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Angela Ortiz can be reached on 571-272-1206. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MACEEH . ANWARI
Primary Examiner
Art Unit 3663
/MACEEH ANWARI/ Primary Examiner, Art Unit 3663
Prosecution Insights