Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/9/23, 2/11/25, 10/21/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-15, drawn to digital to analog converter, classified in class 341 subclass 145.
II. Claim17-18, drawn to photon counting, classified in class 327 subclass 552.
The inventions are independent or distinct, each from the other because:
Group I relates to a resistive digital to analog converter which can be used in many electronic devices and Group lI relates to photon counting device particular for medical diagnostics.
During a telephone conversation with Mr. Jason Gordon on 8/5/25 a provisional election was made with traverse to prosecute the invention of Group I, claims 1-15. Affirmation of this election must be made by applicant in replying to this Office action. Claims 16-17 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
An art rejection of the selected claims appears below.
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
9. Claim(s) 1, 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho (US 5,940,020).
With regard to claim 1, Ho discloses:
A digital to analogue voltage converter comprising: a first resistor string having a plurality of resistors (10 Ra1-Ra(n) Fig. 2) between a first end of the first resistor string (Vrefp Fig.2) and a second end of the first resistor string (Vredn Fig. 2) ; and a plurality of digital to analogue voltage converter stages, each digital to analogue voltage converter stage coupled to said first resistor string and comprising: a voltage buffer (24 Fig. 2) ; a first switching stage (13 Fig. 2) coupled to the first resistor string, the first switching stage configured to provide an input to the voltage buffer (24 Fig. 2) in dependence on receiving a first sub-word of a digital input of the digital to analogue voltage converter (from decoded 16 Fig.12); a second resistor string (26 Rb1 Rb(p) Fig. 2) having one or more resistors, wherein a first end of the second resistor string is coupled to a current source (25 Fig. 2) and a second end of the second resistor string is coupled to an output of the voltage buffer (24 Fig. 2) ; and a second switching stage (712 fig. 5) coupled to the second resistor string, the second switching stage (not labeled: switches connected to the resistor string) configured to provide an analogue voltage (14 Fig. 2) as an output of the digital to analogue voltage converter stage in dependence on receiving a second sub-word (from decoder 16 Fig. 2) of the digital input of the digital to analogue voltage converter (14 Fig. 2).
Ho fails to teach a plurality of digital converter stages capable of producing more than one output voltage from a corresponding digital input. It would have been obvious to anyone having skilled in the art to adapt any single resistive DAC to multiple analog outputs based on routine experimentations or system requirements or the environment the converter is to be used.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho (US 5,940,020) in view of Rivoir (US 5,703,588).
With regard to claim 12, Ho fails to disclose:
The digital to analogue voltage converter of claim 1, wherein the current source is not controlled by said input voltage and delivers a fixed current to the second resistor string.
Rivoir discloses in Fig. 6 resistor string DAC whose least significant bit string is driven by a fixed current (54). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to have applied the teachings of Rivoir in the DAC of Ho for the benefit to prevent conversion non-linearity from occurring independent of the value of the resistors.
With regard to claim 13, Ho discloses:
The digital to analogue voltage converter of claim 12, wherein: a first end of the first resistor string is coupled to a first reference voltage or an output of a first reference voltage buffer comprising a voltage amplifier (Vrefp Fig. 2), wherein the voltage amplifier is arranged to receive the first reference voltage as an input (21 Fig. 2); and a second end of the first resistor string (10 Fig. 2) is coupled to a second reference voltage (Vrefn Fig.2) or an output of a second reference voltage buffer comprising a voltage amplifier (23 Fig. 2) , wherein the voltage amplifier is arranged to receive the second reference voltage as an input, wherein the second reference voltage is lower than the first reference voltage (Vrefn (negative) is less than Vrefp(positive)).
Allowable Subject Matter
Claims 2-11 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Oo (US 2010/0182175) discloses a digital to analog converter.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845