DETAILED ACTION
This Action is a response to the reply filed 19 February 2026. Claim 22 is amended; no claims are canceled or newly added. Claims 1-16 and 19-22 remain pending for examination. In view of the amendments, the rejection of claim 22 under 35 U.S.C. § 101 is withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. §§ 102 and 103 (or as subject to pre-AIA 35 U.S.C. §§ 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 21-22 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Kilzer et al., U.S. 9,377,507 B2 (“Kilzer”).
Regarding claim 1, Kilzer teaches: An apparatus comprising: processing circuitry to execute a sequence of instructions that includes a plurality of debug information triggering instructions; and debug information generating circuitry for coupling to a debug port (Kilzer, e.g., FIG. 1 and 4:13-19, “CPU 110 is coupled with hardware breakpoint unit 135, event detection unit 140, control logic unit 145 and background interface 155 through an internal bus. Multiplexer 160 is used to allow coupling of the debug unit with an external debugger through dedicated debug clock and data pins 165 …” See also, e.g., 4:35-43, “breakpoint debugging is implemented such that execution is halted …”); wherein:
the processing circuitry is arranged, on executing a given debug information triggering instruction in the plurality of debug information triggering instructions, to trigger the debug information generating circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction, and to output the generated debug information signal from the debug port for reference by a debugger apparatus (Kilzer, e.g., 4:63-5:11, “internal or external events can generate a trigger that causes the debugging circuitry in the processor to insert a respective data packet into the trace data stream. The external event can be an external signal applied to the trigger in input TRGIN 185. The internal event can be any event such as a breakpoint/watchpoint, a master clear, an interrupt, an exceptional execution condition …” See also, e.g., 4:13-19, “Multiplexer 160 is used to allow coupling of the debug unit with an external debugger through dedicated debug clock and data pins 165 …” See also, e.g., FIG. 4 and 7:56-60, “When the ‘trigger in’ pulse occurs in the middle of a trace instruction stream, a ‘TRG TRC’ packet is inserted into the regular trace stream …” and 10:10-24, “Trace payload packets encode the instructions that the CPU core executes and selected data events …”); and
the control parameter is such that the form of the debug information signal enables the debugger apparatus to determine a state of the processing circuitry when the given debug information triggering instruction was executed (Kilzer, e.g., FIG. 4 and 7:56-60, “When the ‘trigger in’ pulse occurs in the middle of a trace instruction stream, a ‘TRG TRC’ packet is inserted into the regular trace stream …” See also, e.g., 10:10-24, “Trace payload packets encode the instructions that the CPU core executes and selected data events …”).
Regarding claim 2, the rejection of claim 1 is incorporated, and Kilzer further teaches: wherein one or more of the debug information triggering instructions in the plurality of debug information triggering instructions has a control parameter that differs to the control parameter specified by one or more other debug information triggering instructions in the plurality of debug information triggering instructions, such that the form of the debug information signal generated by the debug information generating circuitry is dependent on which debug information triggering instruction is executed (Kilzer, e.g., TABLE 5 and 11:22-12:25, describing different trace encodings based on different types of events and instructions triggering trace data to be output).
Regarding claim 3, the rejection of claim 2 is incorporated, and Kilzer further teaches: wherein the debug information generating circuitry is arranged to generate a series of debug information signals in response to a series of debug information triggering instructions in the plurality being executed, to enable the debugger apparatus to determine the state of the processing circuitry when the given debug information triggering instruction was executed based on both the form of the debug information signal generated as a result of executing the given debug information triggering instruction and the form of one or more previously generated debug information signals (Kilzer, e.g., TABLE 5 and 11:22-12:25, describing different trace encodings based on different types of events and instructions triggering trace data to be output; see also, e.g., TABLE 5 and 11:22-12:25, describing different trace encodings based on different types of events and instructions triggering trace data to be output).
Regarding claim 4, the rejection of claim 1 is incorporated, and Kilzer further teaches: wherein the state of the processing circuitry is an indication of which instructions within the sequence of instructions had been executed by the processing circuitry at the time the given debug information triggering instruction was executed (Kilzer, e.g., FIG. 4 and 7:56-60, “When the ‘trigger in’ pulse occurs in the middle of a trace instruction stream, a ‘TRG TRC’ packet is inserted into the regular trace stream …” See also, e.g., 10:10-24, “Trace payload packets encode the instructions that the CPU core executes and selected data events …”).
Regarding claim 5, the rejection of claim 1 is incorporated, and Kilzer further teaches: wherein the debug information generating circuitry is arranged to determine a duration of time for which the debug information signal is output from the debug port in dependence on the control parameter specified by the given debug information triggering instruction (Kilzer, e.g., 7:22-31, “Another control bit may be used to control the filter, for example, to define that the input must be in the active state for a minimum time in order to be recognized …”).
Regarding claim 6, the rejection of claim 5 is incorporated, and Kilzer further teaches: wherein the debug information generating circuitry is arranged to control, in dependence on the control parameter, at least one of a number of pulses, a duration of individual pulses and a time gap between pulses when generating the form of the debug information signal output during the determined duration of time (Kilzer, e.g., 7:22-31, “Another control bit may be used to control the filter, for example, to define that the input must be in the active state for a minimum time in order to be recognized. Shorter pulses are then ignored …”).
Regarding claim 7, the rejection of claim 5 is incorporated, and Kilzer further teaches: wherein the determined duration of a time is one or more clock cycles, where the number of clock cycles is dependent on the control parameter (Kilzer, e.g., 7:22-31, “Another control bit may be used to control the filter, for example, to define that the input must be in the active state for a minimum time in order to be recognized …” See also, e.g., 5:47-53, “cycle counter 150 is a counter used to provide a stopwatch function so that user code can be profiled … counter 150 may be incremented at the end of every Q-cycle of the CPU …”).
Regarding claim 8, the rejection of claim 5 is incorporated, and Kilzer further teaches: wherein a time taken by the processing circuitry to execute the given debug information triggering instruction is independent of the determined duration of time over which the debug information signal is output from the debug port (Kilzer, e.g., 7:22-31, “Another control bit may be used to control the filter, for example, to define that the input must be in the active state for a minimum time in order to be recognized …” See also, e.g., 5:47-53, “cycle counter 150 is a counter used to provide a stopwatch function so that user code can be profiled … counter 150 may be incremented at the end of every Q-cycle of the CPU …” Examiner’s note: the TRGIN input signal is the debug information triggering instruction, for which the input duration time is determined and evaluated. No mention is made of the duration of the debug information signal output, and thus the triggering instruction time is independent thereof).
Regarding claim 21, Kilzer teaches: A method of generating debug information (Kilzer, e.g., 2:40-45, “a method for debugging executable code within a processor device …”), comprising: executing within processing circuitry a sequence of instructions that includes a plurality of debug information triggering instructions; coupling debug information generating circuitry to a debug port (Kilzer, e.g., FIG. 1 and 4:13-19, “CPU 110 is coupled with hardware breakpoint unit 135, event detection unit 140, control logic unit 145 and background interface 155 through an internal bus. Multiplexer 160 is used to allow coupling of the debug unit with an external debugger through dedicated debug clock and data pins 165 …” See also, e.g., 4:35-43, “breakpoint debugging is implemented such that execution is halted …”);
on executing within the processing circuitry a given debug information triggering instruction in the plurality of debug information triggering instructions, triggering the debug information generating circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction; and outputting the generated debug information signal from the debug port for reference by a debugger apparatus (Kilzer, e.g., 4:63-5:11, “internal or external events can generate a trigger that causes the debugging circuitry in the processor to insert a respective data packet into the trace data stream. The external event can be an external signal applied to the trigger in input TRGIN 185. The internal event can be any event such as a breakpoint/watchpoint, a master clear, an interrupt, an exceptional execution condition …” See also, e.g., 4:13-19, “Multiplexer 160 is used to allow coupling of the debug unit with an external debugger through dedicated debug clock and data pins 165 …” See also, e.g., FIG. 4 and 7:56-60, “When the ‘trigger in’ pulse occurs in the middle of a trace instruction stream, a ‘TRG TRC’ packet is inserted into the regular trace stream …” and 10:10-24, “Trace payload packets encode the instructions that the CPU core executes and selected data events …”);
wherein the control parameter is such that the form of the debug information signal enables the debugger apparatus to determine a state of the processing circuitry when the given debug information triggering instruction was executed (Kilzer, e.g., FIG. 4 and 7:56-60, “When the ‘trigger in’ pulse occurs in the middle of a trace instruction stream, a ‘TRG TRC’ packet is inserted into the regular trace stream …” See also, e.g., 10:10-24, “Trace payload packets encode the instructions that the CPU core executes and selected data events …”).
Regarding claim 22, Kilzer teaches: A non-transitory computer-readable storage medium storing a computer program for controlling a host data processing apparatus to provide an instruction execution environment (Kilzer, e.g., 15:31-50, describing the use of software to facilitate the methods and procedures described throughout), comprising: processing program logic to execute a sequence of instructions that includes a plurality of debug information triggering instructions; and debug information generating program logic for coupling to a debug port (Kilzer, e.g., FIG. 1 and 4:13-19, “CPU 110 is coupled with hardware breakpoint unit 135, event detection unit 140, control logic unit 145 and background interface 155 through an internal bus. Multiplexer 160 is used to allow coupling of the debug unit with an external debugger through dedicated debug clock and data pins 165 …” See also, e.g., 4:35-43, “breakpoint debugging is implemented such that execution is halted …”); wherein:
the processing program logic is arranged, on executing a given debug information triggering instruction in the plurality of debug information triggering instructions, to trigger the debug information generating program logic to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction, and to output the generated debug information signal from the debug port for reference by a debugger apparatus (Kilzer, e.g., 4:63-5:11, “internal or external events can generate a trigger that causes the debugging circuitry in the processor to insert a respective data packet into the trace data stream. The external event can be an external signal applied to the trigger in input TRGIN 185. The internal event can be any event such as a breakpoint/watchpoint, a master clear, an interrupt, an exceptional execution condition …” See also, e.g., 4:13-19, “Multiplexer 160 is used to allow coupling of the debug unit with an external debugger through dedicated debug clock and data pins 165 …” See also, e.g., FIG. 4 and 7:56-60, “When the ‘trigger in’ pulse occurs in the middle of a trace instruction stream, a ‘TRG TRC’ packet is inserted into the regular trace stream …” and 10:10-24, “Trace payload packets encode the instructions that the CPU core executes and selected data events …”); and
the control parameter is such that the form of the debug information signal enables the debugger apparatus to determine a state of the processing program logic when the given debug information triggering instruction was executed (Kilzer, e.g., FIG. 4 and 7:56-60, “When the ‘trigger in’ pulse occurs in the middle of a trace instruction stream, a ‘TRG TRC’ packet is inserted into the regular trace stream …” See also, e.g., 10:10-24, “Trace payload packets encode the instructions that the CPU core executes and selected data events …”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. § 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of Hervin et al., U.S. 6,205,560 B1 (“Hervin”).
Regarding claim 10, the rejection of claim 1 is incorporated, but Kilzer does not more particularly teach that the processing circuitry comprises a plurality of pipeline stages and processes each debug information triggering instruction in a manner that prevents the execution of that instruction causing a subsequent instruction in the sequence to stall within one or more pipeline stages. However, Hervin does teach: wherein the processing circuitry comprises a plurality of pipeline stages and is arranged to process each debug information triggering instruction in a manner that prevents the execution of that debug information triggering instruction causing a subsequent instruction in the sequence to stall within one or more pipeline stages of the processing circuitry (Hervin, e.g., 16:29-48, “compares the decoded instruction with the instruction identified in the debug configuration registers and determines whether the instructions match. If a match occurs … the particular ID2 stage determines whether the HOLDF or HOLDB bit or both bits is enabled. If the HOLDF bit is enabled, the pipe control unit 28 stalls the matched instruction in the particular ID2 stage until both the X and Y pipelines complete execution of any prior instructions and contain no further instructions. The matched instruction is then executed by either the X or Y pipeline as normal along with any subsequent instructions …” See also, e.g., 16:63-17:6, “… allows an identified instruction to be executed in isolation from subsequent instructions or from prior instructions or from both. This ability enables a person debugging a stream of instructions to execute an instruction with interaction errors and proceed with diagnosing and debugging the remainder of the stream of instructions …”) for the purpose of enabling execution of an instruction in isolation from prior or subsequent instructions or both in order to isolate errors and determine whether said errors may arise from interaction with prior or subsequent instructions (Hervin, e.g., 16:29-17:6).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer to provide that the processing circuitry comprises a plurality of pipeline stages and processes each debug information triggering instruction in a manner that prevents the execution of that instruction causing a subsequent instruction in the sequence to stall within one or more pipeline stages because the disclosure of Hervin shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for providing debugging functions with respect to processor instructions to provide that the processing circuitry comprises a plurality of pipeline stages and processes each debug information triggering instruction in a manner that prevents the execution of that instruction causing a subsequent instruction in the sequence to stall within one or more pipeline stages for the purpose of enabling execution of an instruction in isolation from prior or subsequent instructions or both in order to isolate errors and determine whether said errors may arise from interaction with prior or subsequent instructions (Hervin, Id.).
Claim 11 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of Hervin, and in further view of Burger et al., U.S. 2017/0083431 A1 (“Burger”) and Key et al., U.S. 6,173,386 B1 (“Key”).
Regarding claim 11, the rejection of claim 10 is incorporated, but Kilzer in view of Hervin does not more particularly teach that the pipeline stages include a given stage where the debug information triggering instruction becomes non-speculative. However, Burger does teach: wherein the plurality of pipeline stages includes a given pipeline stage where the debug information triggering instruction becomes non-speculative (Burger, e.g., ¶¶97-98, “During the default mode of the execute state, instructions … are being executed … instruction block can be executing … non-speculatively … During the debug mode of the execute state, instructions of the instruction block can be single-stepped … one instruction of the instruction block can be executed. The intermediate state of the processor core can be scanned or read out of the processor core … ‘next’ instruction can be determined based on … an order generated outside of the processor core (such as by debug software running on a different core) …”) for the purpose of providing processor state mapping, changing, retrieving and debugging (Burger, e.g., ¶¶89-102).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer in view of Hervin to provide that the pipeline stages include a given stage where the debug information triggering instruction becomes non-speculative because the disclosure of Burger shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for providing debugging operations for a block-based processor to provide that the pipeline stages include a given stage where the debug information triggering instruction becomes non-speculative for the purpose of providing processor state mapping, changing, retrieving and debugging (Burger, Id.).
Kilzer in view of Hervin and Burger does not more particularly teach that each debug information triggering instruction executes in a single clock cycle within the given pipeline stage. However, Key does teach: each debug information triggering instruction is executed in a single clock cycle within the given pipeline stage (Key, e.g., 5:2-20, “debug capabilities may be triggered by one or more predetermined events to put processing complex elements … of the parallel processor into a debug mode … element’s internal state may be examined, and the processing executed by the element may be made to following a ‘single-step’ mode of operation … processing executed by a processing element … may be made to advance, upon command, in single clock-cycle increments …”) for the purpose of performing debugging operations in a single-step mode of operation to inspect processor internal state data (Key, e.g., 5:2-51).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer in view of Hervin and Burger to provide that each debug information triggering instruction executes in a single clock cycle within the given pipeline stage because the disclosure of Key shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for providing debugging functions with respect to a parallel processor to provide that each debug information triggering instruction executes in a single clock cycle within the given pipeline stage for the purpose of performing debugging operations in a single-step mode of operation to inspect processor internal state data (Key, Id.).
Claim 12 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of Lee et al., U.S. 2011/0119656 A1 (“Lee”).
Regarding claim 12, the rejection of claim 1 is incorporated, but Kilzer does not more particularly teach that the control parameter is specified as an immediate value within the given debug information triggering instruction. However, Lee does teach: wherein the control parameter is specified as an immediate value within the given debug information triggering instruction (Lee, e.g., ¶¶60-63, “debug code lines 211, 221, and 231 may use the printf() function to output a value of a predetermined parameter … line 211 may indicate that a value of an integer of an integer parameter ‘val1’ may be output with ‘Msg1:’ …”) for the purpose of permitting the specification of particular instructions to debug, including a specification of the information to be retrieved and the method for doing so in a debugging information instruction (Lee, e.g., ¶¶12-16, 49-63).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer to provide that the control parameter is specified as an immediate value within the given debug information triggering instruction because the disclosure of Lee shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for processing debugging information in a computing system to provide that the control parameter is specified as an immediate value within the given debug information triggering instruction for the purpose of permitting the specification of particular instructions to debug, including a specification of the information to be retrieved and the method for doing so in a debugging information instruction (Lee, Id.).
Claim 13 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of Borkenhagen et al., U.S. 5,790,843 A (“Borkenhagen”).
Regarding claim 13, the rejection of claim 1 is incorporated, but Kilzer does not more particularly teach that the control parameter is specified within an opcode portion of the given debug information triggering instruction. However, Borkenhagen does teach: wherein the control parameter is specified within an opcode portion of the given debug information triggering instruction (Borkenhagen, e.g., 2:12-39, “debugging capabilities are achieved by providing a microprocessor device with an instruction match register for storing a predetermined binary opcode, an instruction matching system for comparing the predetermined binary opcode with each instruction being executed on the microprocessor … altering the operation of the microprocessor … may include … any other modification that may enhance debugging operations … loading an opcode … upon a match between the opcode and one of the instructions being dispatched for execution, performing one of the non-uniform microprocessor operations …”) for the purpose of facilitating the selection of specific instructions for debugging using opcodes (Borkenhagen, e.g., 2:12-49).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer to provide that the control parameter is specified within an opcode portion of the given debug information triggering instruction because the disclosure of Borkenhagen shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for modifying processor operations for debugging to provide that the control parameter is specified within an opcode portion of the given debug information triggering instruction for the purpose of facilitating the selection of specific instructions for debugging using opcodes (Borkenhagen, Id.).
Claim 14 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of White et al., U.S. 7,665,002 B2 (“White”).
Regarding claim 14, the rejection of claim 1 is incorporated, but Kilzer does not more particularly teach that the control parameter identifies one or more registers, and the debug information generating circuitry references current values of those registers when determining the form of the debug information signal to be generated. However, White does teach: wherein the control parameter identifies one or more registers, and the debug information generating circuitry is arranged to reference current values of those one or more registers when determining the form of the debug information signal to be generated (White, e.g., 9:36-59, “mask register 160 may be an element of the register set …Values may be written into this registers … by placing data on a TDI line of a debug port interface … debug or test commands received by the debug controller … may include as mask … as part of the command that specified, selects or otherwise indicates to which logic cores the particular command applies …” See also, e.g., 10:15-39, “In response to an asserted DBREQ 260, core debug controller 150 of logic cores selected via mask register 160 may be … put into an debug … mode. Subsequently core debug controller 150 may respond to commands issued by the ATE, such as via the TAP interface, to … read values from certain processor core registers, and/or perform other testing or debugging functions … When DBREQ 260 is asserted for more than one logic core simultaneously, such as by storing a value indicating multiple logic cores in mask register 160, a DBRDY line from each of the selected logic cores 120 may be directed to combinational logic …”) for the purpose of providing a directly controllable debugging instruction selection and data gathering capability (White, e.g., 9:7-12:19).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer to provide that the control parameter identifies one or more registers, and the debug information generating circuitry references current values of those registers when determining the form of the debug information signal to be generated because the disclosure of White shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for providing debugging capabilities with respect to a multi-core integrated circuit to provide that the control parameter identifies one or more registers, and the debug information generating circuitry references current values of those registers when determining the form of the debug information signal to be generated for the purpose of providing a directly controllable debugging instruction selection and data gathering capability (White, Id.).
Claim 15 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of Kiciman et al., U.S. 2009/0083714 A1 (“Kiciman”).
Regarding claim 15, the rejection of claim 1 is incorporated, but Kilzer does not more particularly teach that the control parameter causes the debug information generating circuitry to derive the form of the debug information signal by modifying the form of one or more previously issued debug information signals. However, Kiciman does teach: wherein the control parameter causes the debug information generating circuitry to derive the form of the debug information signal by modifying the form of one or more previously issued debug information signals (Kiciman, e.g., claims 1-2, “identify instrumentation points … selecting a subset from among the identified instrumentation points … modifying the remotely executed portion of the application program to provide for debugging computer-executable instructions … associated with the selected filtered instrumentation points … wherein the selecting and the modifying is adjusted according to information received from previous debugging computer-executable instructions that were provided for by previously modified remotely executed portions …”) for the purpose of providing a dynamically adjustable debugging environment wherein intercepted instructions may be modified for monitoring, wherein subsequent interceptions of instructions can result in further modifications of the debugging commands based on various monitoring information (Kiciman, e.g., ¶¶5-8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer to provide that the control parameter causes the debug information generating circuitry to derive the form of the debug information signal by modifying the form of one or more previously issued debug information signals because the disclosure of Kiciman shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for providing debugging capabilities to distributed applications to provide that the control parameter causes the debug information generating circuitry to derive the form of the debug information signal by modifying the form of one or more previously issued debug information signals for the purpose of providing a dynamically adjustable debugging environment wherein intercepted instructions may be modified for monitoring, wherein subsequent interceptions of instructions can result in further modifications of the debugging commands based on various monitoring information (Kiciman, Id.).
Claim 16 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of Key.
Regarding claim 16, the rejection of claim 1 is incorporated, but Kilzer does not more particularly teach an input to receive an enable signal and that the debug information generating circuitry is arranged to inhibit generation of the debug information signal in the absence of the enable signal being asserted. However, Key does teach: an input to receive an enable signal; wherein the debug information generating circuitry is arranged to inhibit generation of the debug information signal in the absence of the enable signal being asserted (Key, e.g., 15:52-16:4, “remote processor may, by issuing appropriate commands to the circuitry 1000, cause the circuitry 1000 to write values into those registers that enable and control execution of debug features of the processor 300 … remote processor issues commands to the circuitry 1000 via bus 293 that cause the circuitry 1000 to write into the register 1007 a debug enable or ‘set’ value …” See also, e.g., 17:59-18:21, “if the remote processor resets the value contained in the enable register 1007 such that it no longer indicates that global debug mode is desired for the processor 300 … then the global fault signal is no longer generated … causes the elements 400, IHB 700, and OHB 900 to cease being in debug mode, and return to their above-described normal operations … components … do not necessarily all have to be in respective debug modes contemporaneously”) for the purpose of providing a dynamically selectable debugging operation enabled and inhibited through the use of registers storing debug enable flags based on the receipt of enabling and disabling commands (Key, e.g., 15:52-18:52).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer to provide for an input to receive an enable signal and that the debug information generating circuitry is arranged to inhibit generation of the debug information signal in the absence of the enable signal being asserted because the disclosure of Key shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for providing debugging functions with respect to a parallel processor to provide for an input to receive an enable signal and that the debug information generating circuitry is arranged to inhibit generation of the debug information signal in the absence of the enable signal being asserted for the purpose of providing a dynamically selectable debugging operation enabled and inhibited through the use of registers storing debug enable flags based on the receipt of enabling and disabling commands (Key, Id.).
Claim 19 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of Zwerg et al., U.S. 2017/0185139 A1 (“Zwerg”).
Regarding claim 19, the rejection of claim 1 is incorporated, but Kilzer does not more particularly teach that the apparatus receives power from an energy harvesting source and comprises a controller to save state of the apparatus to non-volatile memory and restore state therefrom in dependence on an energy state of the source. However, Zwerg does teach: wherein the apparatus is arranged to receive power from an energy harvesting source, and further comprises: a controller to save state of the apparatus to non-volatile memory, and restore state from the non-volatile memory, in dependence on an energy state of the energy harvesting source (Zwerg, e.g., claim 1, “a power management unit configured to detect multiple levels of available power for the central processing unit and to effect switching power on or off for the [CPU]; an energy storage unit connected to provide power to the computing device apparatus and configured to hold enough power to operate the computing device apparatus after removal of power from the computing device apparatus … a non-volatile memory controller configured to … have direct access to volatile storage elements embedded in or associated with one or more of the [CPU] … wherein the power management unit is configured to … effect entry of the [CPU] into a low power mode in response to detecting a power loss event initiated by the power management unit due to detection of a power loss scenario … trigger the non-volatile memory controller to store data stored in the volatile storage elements in the non-volatile memory, the data representing a state of the … [CPU] … detect restoration of power … trigger the non-volatile memory controller to restore the data to the volatile storage elements from the non-volatile memory …”) for the purpose of facilitating the storage and retrieval of processor state information when a low power mode is entered or exited, including with respect to sudden power interruption events, such that a CPU’s stable operating state parameters are readily available and restorable from non-volatile storage without consuming power (Zwerg, e.g., ¶¶5-6, 27-31).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer to provide that the apparatus receives power from an energy harvesting source and comprises a controller to save state of the apparatus to non-volatile memory and restore state therefrom in dependence on an energy state of the source because the disclosure of Zwerg shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for facilitating processor state management in power interruption scenarios to provide that the apparatus receives power from an energy harvesting source and comprises a controller to save state of the apparatus to non-volatile memory and restore state therefrom in dependence on an energy state of the source for the purpose of facilitating the storage and retrieval of processor state information when a low power mode is entered or exited, including with respect to sudden power interruption events, such that a CPU’s stable operating state parameters are readily available and restorable from non-volatile storage without consuming power (Zwerg, Id.).
Claim 20 is rejected under 35 U.S.C. § 103 as being unpatentable over Kilzer in view of Pellon, Leopold Ernest, U.S. 6,271,781 B1 (“Pellon”).
Regarding claim 20, the rejection of claim 1 is incorporated, but Kilzer does not more particularly teach that the debug information generating circuitry, in response to a calibration trigger, outputs a sequence known to the debugger apparatus, for use by the debugger apparatus to calibrate for noise on a communication channel between the debug port and the debugger apparatus. However, Pellon does teach: wherein the debug information generating circuitry is arranged, in response to a calibration trigger, to output a sequence known to the debugger apparatus, for use by the debugger apparatus to calibrate for noise on a communication channel between the debug port and the debugger apparatus (Pellon, e.g., 1:40-2:14, “Parallel digital signals representing the analog input signals applied to input port 16i are produced at output port 16o. The digital signals at output port 16o are applied to the address input ports of a programmable ROM and to a static DC level calibrator 20. PROM 18 is preprogrammed at each memory location with error correction values established by the static DC level calibrator 20, for producing corrected signals y(n) at its output port 18 … averaging in block 20 removes quantization noise … during calibration procedure, produces a direct level, such as a direct voltage or bias, which is applied over a signal path 24 to input port 14i of summing circuit, for addition or injection of the direct level for measuring direct (DC) offsets at the output … measured offsets are subtracted from the corresponding level values, to produce look-up table values which compensate for the offsets when applied to PROM 18 … After the … calibration period … PROM 18 removes error introduced into the passband …”) for the purpose of calibrating the signals input and output from a circuit using a known direct level signal in order to generate a look-up table with offset values usable to eliminate noise in the signals input and output from the circuit (Pellon, e.g., 1:40-2:20, 3:35-4:8).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system and method for providing processor instruction tracing and debugging operations as taught by Kilzer to provide that the debug information generating circuitry, in response to a calibration trigger, outputs a sequence known to the debugger apparatus, for use by the debugger apparatus to calibrate for noise on a communication channel between the debug port and the debugger apparatus because the disclosure of Pellon shows that it was known to those of ordinary skill in the pertinent art to improve a system and method for calibrating input and output signals of a circuit to provide that the debug information generating circuitry, in response to a calibration trigger, outputs a sequence known to the debugger apparatus, for use by the debugger apparatus to calibrate for noise on a communication channel between the debug port and the debugger apparatus for the purpose of calibrating the signals input and output from a circuit using a known direct level signal in order to generate a look-up table with offset values usable to eliminate noise in the signals input and output from the circuit (Pellon, Id.).
Response to Arguments
In the Remarks, Applicant Argues: Kilzer fails to disclose at least the following features of claim 1: “the processing circuitry is arranged, on executing a given debug information triggering instruction … to trigger the debug … circuitry to generate a debug information signal whose form is dependent on a control parameter specified by the given debug information triggering instruction” (Resp. at 7-8). The external signal, interrupt, exceptional execution condition, and debugger overflow condition “cannot be reasonably considered to disclose or be equivalent to executing a debug information triggering instruction” (id. at 8). “Even if Kilzer did teach that breakpoints were triggered by a breakpoint instruction … there is no teaching in Kilzer that a trace packet inserted into a trace stream in response to a breakpoint instruction has a form which depends on a control parameter specified by the instruction” (id.). Further, even “if Kilzer disclosed execution of an instruction to trigger a signal output to a debug port … Kilzer simply does not modify an instruction to specify a control parameter and generate a signal whose form is dependent on said control parameter” (id. at 9).
Examiner’s Response: The claim requires execution of a debug information triggering instruction; Examiner is giving this compound claim term its broadest reasonable interpretation which is an instruction, which when executed, triggers the output or processing of debug information. Each of the cited examples in Kilzer are the result of executing one or more instructions, and in response to each of these examples an external signal is triggered and applied to TRGIN, which results in the output of debug information. Thus, each of these is a “debug information triggering instruction” consistent with how that term is presented in the claims.
Further, the claim defines that the control parameter “is such that the form of the debug information signal enables the debugger apparatus to determine a state of the processing circuitry when the given debug information triggering instruction was executed” (see claim 1 at lines 12-14). Kilzer describes that in response to the debug information triggering instruction (i.e. the instruction that when executed causes the TRGIN input signal), a TRG TRC packet is inserted into the trace stream, the payload of which encodes instructions that the CPU core executes and selected data events (i.e., a state of the processing circuitry when the instruction was executed).
Examiner notes that further detail regarding the examples provided in the Specification that provides further and/or more detailed description of each of these terms may provide distinctions over the disclosures of Kilzer. At this time, however, Examiner does not import these details into the claims so as to avoid improperly narrowing claim scope.
In view of the foregoing, Examiner does not find persuasive the argument that Kilzer fails to teach or suggest the identified claim terms, and maintains the rejections under the complete grounds set forth in full above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Examiner has identified particular references contained in the prior art of record within the body of this action for the convenience of Applicant. Although the citations made are representative of the teachings in the art and are applied to the specific limitations within the enumerated claims, the teaching of the cited art as a whole is not limited to the cited passages. Other passages and figures may apply. Applicant, in preparing the response, should consider fully the entire reference as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art and/or disclosed by Examiner.
Examiner respectfully requests that, in response to this Office Action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
When responding to this Office Action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Examiner interviews are available via telephone and video conferencing using a USPTO-supplied web-based collaboration tool. Applicant is encouraged to submit an Automated Interview Request (AIR) which may be done via https://www.uspto.gov/patent/uspto-automated-interview-request-air-form, or may contact Examiner directly via the methods below.
Any inquiry concerning this communication or earlier communication from Examiner should be directed to Andrew M. Lyons, whose telephone number is (571) 270-3529, and whose fax number is (571) 270-4529. The examiner can normally be reached Monday to Friday from 10:00 AM to 6:00 PM ET. If attempts to reach Examiner by telephone are unsuccessful, Examiner’s supervisor, Wei Mui, can be reached at (571) 272-3708. Information regarding the status of an application may be obtained from the Patent Center system. For more information about the Patent Center system, see https://www.uspto.gov/patents/apply/patent-center. If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (in USA or Canada) or (571) 272-1000.
/Andrew M. Lyons/Primary Examiner, Art Unit 2191