DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Applicant's amendment filed on September 9, 2025 was received. No claims were amended, added or canceled. Claims 17-20 were added.
The text of those sections of Title 35. U.S.C. code not included in this action can be found in the prior Office Action Issued June 11, 2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 9-10 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Avuthu (US20180336993).
Regarding claim 1, Avuthu teaches a method of for printing a plurality of inductive coils (paragraphs 0016, 0051, abstract, see figure 2). Avuthu teaches to provide a substate having a top surface and a bottom surface (paragraphs 0019 and 0051). Avuthu teaches to provide vias through the substrate for all of the plurality of coils (electrical device) (paragraph 0051, see figure 2). Avuthu teaches to print the conductive traces (circuit elements) for the plurality of electrical devices on the top surface and bottom surface of the substrate using a conductive ink (paragraphs 0048-0049, 0051 and 0053). Avuthu teaches printing the circuit elements on the top and bottom surfaces causes the ink to flow though the vias to provide an electrical connection between the circuit elements on the top and bottom surfaces of the surface (paragraphs 0051 and 0053).
Regarding claim 6, Avuthu teaches the electrical devices are RFID devices and the circuit elements are RFID antennas (pargraph 0047).
Regarding claim 9, Avuthu teaches the conductive ink is a silver ink (paragraph 0048).
Regarding claim 10, Avuthu teaches the subsea is a flexible substate (paragraph 0016 and 0019), thus, making the electronic a flexible hybrid electronic.
Regarding claim 12, Avuthu teaches a method of for printing a plurality of inductive coils (paragraphs 0016, 0051, abstract, see figure 2). Avuthu teaches to provide a substate having a top surface and a bottom surface (paragraphs 0019 and 0051), wherein the substrate is flexible (paragraph 0019). Avuthu teaches to provide vias through the substrate for all of the plurality of coils (electrical device) (paragraph 0051, see figure 2), wherein the coils are RFID antennas (plurality of RFID devices). Avuthu teaches to print the conductive traces (circuit elements) for the plurality of electrical devices on the top surface and bottom surface of the substrate using a conductive ink (paragraphs 0048-0049, 0051 and 0053), wherein the traces are polygonal or spiral coil (wound antennas) (pargraph 0048). Avuthu teaches printing the circuit elements on the top and bottom surfaces causes the ink to flow though the vias to provide an electrical connection between the circuit elements on the top and bottom surfaces of the surface (paragraphs 0051 and 0053).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Avuthu (US20180336993) as applied to claims 1, 6, 9-10 and 12 above, and further in view of Bonora (US20090001616).
Regarding claim 2, Avuthu teaches all limitations of this claim, except printing graphics that identify the electrical devices on the surface of the substrate. Bonora teaches to print graphics that identify the electrical device on the surface of the substrate (abstract, paragraph 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to print the graphic on the surface of the substrate as suggested by Bonora in the method of Avuthu because Bonora teaches the printing of graphic will capture the information in a manner that would enhance throughput, reduce handling, improve readability, minimize misreads and be able to withstand the harsh processing conditions experienced by the wafer (paragraph 0003).
Regarding claim 3, Avuthu teaches the vias are formed in the substrate to allow the conductive connection through the via by the printed traces on the both sides of the surface (paragraph 0051). Thus, Avuthu teaches the vias are formed before the printing of the circuit elements. However, Avuthu does not explicitly teach the printing the graphic is performed before the vias are provided. However, it is obvious to choose from a finite number of identified, predictable solutions, with a reasonable expectation of success (MEPE 2143 I E). In this case, the printing of graphics can be formed before, during or after the vias are formed with the same result. Thus, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to print the graphics before the vias are provided in light of the teaching of Avuthu in view of Bonora.
Regarding claim 14, Avuthu teaches all limitations of this claim, except printing graphics that identify the electrical devices on the surface of the substrate. Bonora teaches to print graphics that identify the electrical device on the surface of the substrate (abstract, paragraph 0041). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to print the graphic on the surface of the substrate as suggested by Bonora in the method of Avuthu because Bonora teaches the printing of graphic will capture the information in a manner that would enhance throughput, reduce handling, improve readability, minimize misreads and be able to withstand the harsh processing conditions experienced by the wafer (paragraph 0003).
Regarding claim 15, Avuthu teaches the vias are formed in the substrate to allow the conductive connection through the via by the printed traces on the both sides of the surface (paragraph 0051). Thus, Avuthu teaches the vias are formed before the printing of the circuit elements. However, Avuthu does not explicitly teach the printing the graphic is performed before the vias are provided. However, it is obvious to choose from a finite number of identified, predictable solutions, with a reasonable expectation of success (MEPE 2143 I E). In this case, the printing of graphics can be formed before, during or after the vias are formed with the same result. Thus, it would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to print the graphics before the vias are provided in light of the teaching of Avuthu in view of Bonora.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Avuthu (US20180336993) as applied to claims 1, 6, 9-10 and 12 above, and further in view of Bartley (US20160320443).
Regarding claim 4, Avuthu teaches all the limitations of this claim, except drilling the substrate the vias by a drilling machine. However, Bartley teaches a method of creating vias on a substrate (paragraph 0002). Bartley teaches to provide the vias by drilling through a substrate by drilling machine having a drill bit (paragraphs 0016-0017, 0019-0020). Bartley teaches to periodically inspecting the drill bit and cleaning and inspecting the drilled vias (paragraphs 0019-0020 and 0025). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to drill the vias as suggested by Barley in the method of Avuthu because Bartley teaches such drilling process is an improvised system with more manual control over the quality and completeness of the via drilling process, increasing overall quality (pargraph 0025).
Claims 5 and 16 is rejected under 35 U.S.C. 103 as being unpatentable over Avuthu (US20180336993) as applied to claims 1, 6, 9-10 and 12 above, and further in view of Wable (US20160307092).
Regarding claim 5, Avuthu teaches all limitations for this claim, except manually connecting an integrated circuit to the circuit elements. Wable teaches a method of making RFID chip and antenna (abstract, paragraph 0008) and discloses to manually connecting an integrated circuit to the circuit elements to form the RFID chip (electrical device) (paragraph 0024 and claim 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach an integrated circuit to the circuit elements as suggested by Wable in the method of Avuthu because Wable teaches such integrated circuit provide wireless communication functionality (paragraph 0003).
Regarding claim 16, Avuthu teaches all limitations for this claim, except manually connecting an integrated circuit to the circuit elements. Wable teaches a method of making RFID chip and antenna (abstract, paragraph 0008) and discloses to manually connecting an integrated circuit to the circuit elements to form the RFID chip (electrical device) (paragraph 0024 and claim 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach an integrated circuit to the circuit elements as suggested by Wable in the method of Avuthu because Wable teaches such integrated circuit provide wireless communication functionality (paragraph 0003).
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Avuthu (US20180336993) as applied to claims 1, 6, 9-10 and 12 above,
Regarding claim 7, Avuthu teaches the antennas includes polygonal or spiral coil (pargraph 0048), which reads on the limitation of wound traces. Avuthu teaches the printed line widths and gaps have an averaged dimensions of with ± values (paragraphs 0056), thus indicating there are some variations of the dimensions of width and gaps (trance spacing) between the coils. In addition, it is well settled that proportion/size/dimension of a claimed feature was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the proportion/size/dimension of the claimed feature was significant (MPEP 2144.04 IV. A.). Thus, it would be obvious to one of ordinary skill in the art to change the relative proportion of the traces from each other (different widths or spacing) in light of the teaching of Avuthu.
Regarding claim 13, Avuthu teaches the antennas includes polygonal or spiral coil (pargraph 0048), which reads on the limitation of wound traces. Avuthu teaches the printed line widths and gaps have an averaged dimensions of with ± values (paragraphs 0056), thus indicating there are some variations of the dimensions of width and gaps (trance spacing) between the coils. In addition, it is well settled that proportion/size/dimension of a claimed feature was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the proportion/size/dimension of the claimed feature was significant (MPEP 2144.04 IV. A.). Thus, it would be obvious to one of ordinary skill in the art to change the relative proportion of the traces from each other (different widths or spacing) in light of the teaching of Avuthu.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Avuthu (US20180336993) as applied to claims 1, 6, 9-10 and 12 above, and further in view of Lochun (US20040103808),
Regarding claim 8, Avuthu teaches the substrate is polymer but does not explicitly teach the polymer is polyester. However, Lochun teaches a method of forming an electrical circuit (abstract) and the substrate for forming electrical circuit is polyester (paragraph 0012, 0029). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use polyester as the substrate as suggested by Lochun in the the method of Avuthu because Lochun teaches polyester can include additives to improve fire retardancy, mechanical strength, thermal strength and/or dielectric properties (paragraphs 0029 and 0034).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Avuthu (US20180336993) as applied to claims 1, 6, 9-10 and 12 above, and further in view of Shizuno (US20060082003).
Regarding claim 11, Avuthu teaches all the limitations of this claim, except to dice the substrate to separate the plurality of electrical devices. Shizuno teaches a method of dicing semiconductors substrate (abstract). Shizuno teaches to dice the substrate to separate the plurality of electrical device by using laser light and blade (paragraphs 0025, 0052 and 0073). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dice the substrate as suggested by Shizuno in the method of Avuthu because Shizuno teaches such dicing has higher efficiency, thus reducing the manufacturing cost (paragraph 0113).
Response to Arguments
Applicant's arguments filed on September 9, 2025 have been fully considered but they are not persuasive.
Applicant’s principal arguments are:
Avuthu discloses creating the via 202 after the coil traces 104a are deposited, and then depositing conductive ink in the via 202, Avuthu cannot anticipate independent claim 1 and 12 (also claim 3).
Bonora, Bartley, Wable, Lochun and Shizuno do not cure the deficiency in Avuthu.
In response to Applicant’s arguments, please consider the following comments:
Avuthu’s deposited conductive ink in the via 202 is considered as part of the printing of the circuit elements on the top and bottom surfaces. Those conductive ink in the via 202 provide conductive connection of the traces, thus, reads on the limitations of circuit elements. Especially, Avuthu teaches those conductive ink dispensed to the via may occur on both sides of the substrate (pargraph 0058), which reads on the limitations of printing the circuit elements on the top and bottom surfaces of the substrate. Regarding claim 3, the vias are formed in the substrate to allow the conductive connection through the via by the printed traces on the both sides of the surface (paragraph 0051). Thus, Avuthu teaches the vias are formed at least before the printing of the circuit elements completed.
As discussed above, there is no deficiency in Avuthu.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/N.V.L/Examiner, Art Unit 1717
/Dah-Wei D. Yuan/Supervisory Patent Examiner, Art Unit 1717