DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 8-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter as explained below.
Regarding the term “computer-readable memory device” in claim 8; the broadest reasonable interpretation of a claim drawn to a computer-readable memory device, as the claim presented, covers both forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, particularly when the specification is silent (see MPEP 2111.01). Because the broadest reasonable interpretation covers a signal per se, a rejection under 35 USC 101 is appropriate as covering non-statutory subject matter. See 1351 OG 212, Feb 23 2010.
Claims 9-14 are rejected based on their dependency to Claim 8.
The Examiner suggests that the Applicant replaces “computer-readable memory device” in claim 8 with --non-transitory computer-readable memory device--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pfeil et al., hereinafter Pfeil, US Publication No. 2003/0131332.
Regarding Claim 1, Pfeil teaches a method comprising:
distributing, by a computing device (Pfeil paragraph [0025], see processor), virtual product models to multiple printed circuit board layout tools (Pfeil paragraphs [0027], [0030] and [0033]-[0036], wherein areas of a master design of a PCB are distributed to a plurality of user groups, the user groups comprising clients with layout tools), wherein the virtual product models each correspond to a shared product model describing a product having an electronic device with multiple printed circuit boards (Pfeil paragraph [0047], wherein the master design is the shared product model having a plurality of areas corresponding to multiple printed circuit boards), wherein the printed circuit board layout tools are configured to separately modify the corresponding virtual product models to generate layout designs for the multiple print circuit boards in the product (Pfeil paragraph [0034], wherein each user may request modifications to the areas of master design) and to generate at least one system-level design rule describing a physical limitation for the electronic device based on a constraint in at least one of the layout designs for the multiple print circuit boards (Pfeil paragraph [0055], wherein design rules may be specified);
updating, by the computing system, the shared product model based, at least in part, on the modifications to at least one of the virtual product models by the printed circuit board layout tools (Pfeil paragraphs [0036]-[0040], wherein edit requests are processed and the master design is updated with the edits); and
transmitting, by the computing system, a notification to at least one of the printed circuit board layout tools when the updated shared product model conflicts with the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraphs [0036], [0040] and [0055], wherein edit requests that are rejected based on conflict checking of design rules are reported back to the user).
Regarding Claim 2, Pfeil further teaches wherein the system-level design rule describes the physical limitation for the electronic device based on a physical constraint or an electrical constraint in at least one of the layout designs for the multiple print circuit boards (Pfeil paragraph [0055], wherein design rules define physical constraints).
Regarding Claim 3, Pfeil further teaches wherein the modification of the virtual product models by the print circuit board layout tools generates the notification for transmission to the at least one of the printed circuit board layout tools (Pfeil paragraph [0036], wherein the request for editing generates a report to the client when it is rejected).
Regarding Claim 4, Pfeil further teaches performing, by the computing system, a system-level design rule check to compare the updated shared product model to the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraph [0055], wherein the conflict checking and resolution performs a design rule check on the edit); and
generating, by the computing system, the notification to at least one of the printed circuit board layout tools when the system-level design rule check determines the updated shared product model conflicts with the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraphs [0036], [0040] and [0055], wherein edit requests that are rejected based on conflict checking of design rules are reported back to the user).
Regarding Claim 5, Pfeil further teaches wherein the notification is configured to identify which portion of the electronic device is in a conflict with the physical limitation for the electronic device and identify a suggested alteration for at least one of the printed circuit board layout tools to perform to resolve the conflict (Pfeil paragraph [0055]-[0059], wherein the design rule checker identifies the location of the design rule violation and if the violation may be corrected, e.g. by moving traces, etc.).
Regarding Claim 6, Pfeil further teaches transmitting, by the computing system, at least the modified portion of the updated shared product model to one or more of the multiple printed circuit board layout tools, wherein the printed circuit board layout tools are configured to modify the corresponding virtual product model based on the at least the modified portion of the updated shared product model (Pfeil paragraphs [0059]-[0060], wherein if the edit is accepted, the master design is updated and subsequently the synchronizer tool swaps out the client copy of the master design with the updated design for further editing).
Regarding Claim 7, Pfeil further teaches receiving, by the computing system, a mechanical design from a mechanical system, wherein the mechanical design describes a physical structure of the product to include an electronic device comprising the multiple printed circuit boards (Pfeil paragraphs [0004] and [0033], wherein the master PCB design is a physical design that is received by the server to distribute to the clients); and
incorporating, by the computing system, the mechanical design into the shared product model for distribution to the printed circuit board layout tools as the virtual product models (Pfeil paragraph [0034], wherein the clients receive copies of the master PCB design).
Regarding Claim 8, Pfeil teaches an apparatus comprising at least one computer-readable memory device (Pfeil paragraph [0026], see machine readable medium) storing instructions configured to cause one or more processing devices to perform operations comprising:
distributing virtual product models to multiple printed circuit board layout tools (Pfeil paragraphs [0027], [0030] and [0033]-[0036], wherein areas of a master design of a PCB are distributed to a plurality of user groups, the user groups comprising clients with layout tools), wherein the virtual product models each correspond to a shared product model describing a product having an electronic device with multiple printed circuit boards (Pfeil paragraph [0047], wherein the master design is the shared product model having a plurality of areas corresponding to multiple printed circuit boards), wherein the printed circuit board layout tools are configured to separately modify the corresponding virtual product models to generate layout designs for the multiple print circuit boards in the product (Pfeil paragraph [0034], wherein each user may request modifications to the areas of the master design) and to generate at least one system-level design rule describing a physical limitation for the electronic device based on a constraint in at least one of the layout designs for the multiple print circuit boards (Pfeil paragraph [0055], wherein design rules may be specified);
updating the shared product model based, at least in part, on the modifications to at least one of the virtual product models by the printed circuit board layout tools (Pfeil paragraphs [0036]-[0040], wherein edit requests are processed and the master design is updated with the edits); and
transmitting a notification to at least one of the printed circuit board layout tools when the updated shared product model conflicts with the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraphs [0036], [0040] and [0055], wherein edit requests that are rejected based on conflict checking of design rules are reported back to the user).
Regarding Claim 9, Pfeil further teaches wherein the system-level design rule describes the physical limitation for the electronic device based on a physical constraint or an electrical constraint in at least one of the layout designs for the multiple print circuit boards (Pfeil paragraph [0055], wherein design rules define physical constraints).
Regarding Claim 10, Pfeil further teaches wherein the modification of the virtual product models by the print circuit board layout tools generates the notification for transmission to the at least one of the printed circuit board layout tools (Pfeil paragraph [0036], wherein the request for editing generates a report to the client when it is rejected).
Regarding Claim 11, Pfeil further teaches wherein the instructions configured to cause the one or more processing devices to perform operations further comprising
performing a system-level design rule check to compare the updated shared product model to the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraph [0055], wherein the conflict checking and resolution performs a design rule check on the edit); and
generating the notification to at least one of the printed circuit board layout tools when the system-level design rule check determines the updated shared product model conflicts with the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraphs [0036], [0040] and [0055], wherein edit requests that are rejected based on conflict checking of design rules are reported back to the user).
Regarding Claim 12, Pfeil further teaches wherein the notification is configured to identify which portion of the electronic device is in a conflict with the physical limitation for the electronic device and identify a suggested alteration for at least one of the printed circuit board layout tools to perform to resolve the conflict (Pfeil paragraph [0055]-[0059], wherein the design rule checker identifies the location of the design rule violation and if the violation may be corrected, e.g. by moving traces, etc.).
Regarding Claim 13, Pfeil further teaches wherein the instructions configured to cause the one or more processing devices to perform operations further comprising transmitting at least the modified portion of the updated shared product model to one or more of the multiple printed circuit board layout tools, wherein the printed circuit board layout tools are configured to modify the corresponding virtual product model based on the at least the modified portion of the updated shared product model (Pfeil paragraphs [0059]-[0060], wherein if the edit is accepted, the master design is updated and subsequently the synchronizer tool swaps out the client copy of the master design with the updated design for further editing).
Regarding Claim 14, Pfeil further teaches wherein the instructions configured to cause the one or more processing devices to perform operations further comprising:
receiving a mechanical design from a mechanical system, wherein the mechanical design describes a physical structure of the product to include an electronic device comprising the multiple printed circuit boards (Pfeil paragraphs [0004] and [0033], wherein the master PCB design is a physical design that is received by the server to distribute to the clients); and
incorporating the mechanical design into the shared product model for distribution to the printed circuit board layout tools as the virtual product models (Pfeil paragraph [0034], wherein the clients receive copies of the master PCB design).
Regarding Claim 15, Pfeil teaches a system comprising:
a memory device configured to store machine-readable instructions (Pfeil paragraph [0026], see machine readable medium); and
a computing system including one or more processing devices (Pfeil paragraph [0025], see processor), in response to executing the machine-readable instructions, configured to
distribute virtual product models to multiple printed circuit board layout tools (Pfeil paragraphs [0027], [0030] and [0033]-[0036], wherein areas of a master design of a PCB are distributed to a plurality of user groups, the user groups comprising clients with layout tools), wherein the virtual product models each correspond to a shared product model describing a product having an electronic device with multiple printed circuit boards (Pfeil paragraph [0047], wherein the master design is the shared product model having a plurality of areas corresponding to multiple printed circuit boards), wherein the printed circuit board layout tools are configured to separately modify the corresponding virtual product models to generate layout designs for the multiple print circuit boards in the product (Pfeil paragraph [0034], wherein each user may request modifications to the areas of the master design) and to generate at least one system-level design rule describing a physical limitation for the electronic device based on a constraint in at least one of the layout designs for the multiple print circuit boards (Pfeil paragraph [0055], wherein design rules may be specified);
update the shared product model based, at least in part, on the modifications to at least one of the virtual product models by the printed circuit board layout tools (Pfeil paragraphs [0036]-[0040], wherein edit requests are processed and the master design is updated with the edits); and
transmit a notification to at least one of the printed circuit board layout tools when the updated shared product model conflicts with the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraphs [0036], [0040] and [0055], wherein edit requests that are rejected based on conflict checking of design rules are reported back to the user).
Regarding Claim 16, Pfeil further teaches wherein the system-level design rule describes the physical limitation for the electronic device based on a physical constraint or an electrical constraint in at least one of the layout designs for the multiple print circuit boards (Pfeil paragraph [0055], wherein design rules define physical constraints).
Regarding Claim 17, Pfeil further teaches wherein the modification of the virtual product models by the print circuit board layout tools generates the notification for transmission to the at least one of the printed circuit board layout tools (Pfeil paragraph [0036], wherein the request for editing generates a report to the client when it is rejected).
Regarding Claim 18, Pfeil further teaches wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to:
perform a system-level design rule check to compare the updated shared product model to the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraph [0055], wherein the conflict checking and resolution performs a design rule check on the edit); and
generate the notification to at least one of the printed circuit board layout tools when the system-level design rule check determines the updated shared product model conflicts with the physical limitation for the electronic device described in the at least one system-level design rule (Pfeil paragraphs [0036], [0040] and [0055], wherein edit requests that are rejected based on conflict checking of design rules are reported back to the user).
Regarding Claim 19, Pfeil further teaches wherein the notification is configured to identify which portion of the electronic device is in a conflict with the physical limitation for the electronic device and identify a suggested alteration for at least one of the printed circuit board layout tools to perform to resolve the conflict (Pfeil paragraph [0055]-[0059], wherein the design rule checker identifies the location of the design rule violation and if the violation may be corrected, e.g. by moving traces, etc.).
Regarding Claim 20, Pfeil further teaches wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to transmit at least the modified portion of the updated shared product model to one or more of the multiple printed circuit board layout tools, wherein the printed circuit board layout tools are configured to modify the corresponding virtual product model based on the at least the modified portion of the updated shared product model (Pfeil paragraphs [0059]-[0060], wherein if the edit is accepted, the master design is updated and subsequently the synchronizer tool swaps out the client copy of the master design with the updated design for further editing).
Conclusion
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC D LEE/Primary Examiner, Art Unit 2851
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