CTFR 18/556,265 CTFR 97902 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment Applicant’s addition of claim 7 is acknowledged. Applicant’s amendment to claim 3 corrects the antecedent basis issue originally present. The 112 rejection of claim 3 is withdrawn. Applicant’s replacement drawing filed 04/13/2026 is acknowledged. Applicant’s amendment to the abstract is acknowledged. The objection to the abstract is withdrawn. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “power semiconductor elements” in claims 1 - 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The specification only refers to the drawings as having “semiconductor elements” and does not state what numeral in the drawings is “power semiconductor elements”. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 07-31-01 Claims 1 - 7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 1 – 7 claim “power semiconductor elements”. The specification only uses the term “power semiconductor elements” to discuss a different patent document and background art (immediate invention Par. [0001 – 0005]), and refers to the semiconductor elements throughout the specification as only “semiconductor elements” (immediate invention from Par. [0007] and on). The specification does not make clear or describe the different between a power semiconductor element and a semiconductor element. The specification does not state what comprises a power semiconductor element and does not appear to state that the immediate invention contains power semiconductor elements, but instead only refers to the immediate invention as having “semiconductor elements” (Par. [0007], [0029] describes metallization of an upper electrode of a semiconductor element and not a power semiconductor element, Par. [0014 – 0015] describes figure 2 as showing semiconductor elements and not power semiconductor elements). It is unclear what the difference between semiconductor elements and power semiconductor elements are, as the specification does not provide details describing the difference or what a power semiconductor element is comprised of. Further, the figures and specification only refer to the elements in the drawings as “semiconductor elements” with no mention that they are “power semiconductor elements”. Because the specification and drawings only refers to elements in the immediate invention as semiconductor elements and allows for multiple interpretations for what “power semiconductor elements” are, the specification lacks written description for the term “power semiconductor elements”. Applicant’s arguments filed 04/13/2026 on page 10 of applicant’s remarks appears to state a difference exists regarding the current level of the elements or device, but this difference is not provided in the specification and is not made clear in the immediate invention that this is what a power semiconductor element refers to or if the elements in the immediate invention are power semiconductor elements. For the purpose of compact prosecution, examiner is interpreting the term “power semiconductor element” as referring to a semiconductor element that allows current to flow through it or is electrically connected. This appears to match the specification in Par. [0007 – 0008] and Par. [0029]. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1 – 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160300770 A1 hereinafter Taya in further view of US 20100065963 A1 hereinafter Eldridge . For claim 1, Taya teaches a power module (Taya, fig. 10) comprising a plurality of power semiconductor elements (fig. 10 numeral 31 and 32) through which a main current flows in a thickness direction (Par. [0070]; Par. [0079]; fig. 10 shows the power semiconductor elements 31 and 32 arranged in a thickness direction allowing for a current to flow through the elements in a thickness direction); a substrate on which the plurality of power semiconductor elements are mounted (fig. 10 numeral 2); a base plate on which the substrate is mounted (fig. 10 numeral 1); a case that is bonded to the base plate and houses the plurality of power semiconductor elements (fig. 10 numeral 8; Par. [0028]); a plurality of main wiring boards incorporated in an upper portion of the case on a side opposite to the base plate and arranged in parallel to the base plate (fig. 10 numeral 5); and a plurality of wires bonded to lower surfaces of the plurality of main wiring boards that face the plurality of power semiconductor elements (fig. 10 numeral 7), wherein an upper surface electrode of each of the plurality of power semiconductor elements is electrically connected to a corresponding one of the plurality of main wiring boards with the plurality of wires (fig. 10 numeral 4; Par. [0027] and [0029]). Although Taya does not explicitly state that the current flows in a thickness direction, the structure of Taya is capable of performing the intended use of the power semiconductor elements, that being the current flow flowing in a thickness direction. Claim language referring intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey , 152 USPQ 235 (CCPA 1967); In re Otto , 136 USPQ 458, 459 (CCPA 1963). Taya is silent regarding a bonding material connecting the main wiring boards and the power semiconductor elements. Eldridge teaches a forming power modules (Eldridge, Par. [0889]; fig. 36A – 36C) including power semiconductor elements (fig. 36A numeral 3602, 3603) with wires (fig. 36A numeral 3610) and bonding material (fig. 36A numeral 3612) connecting the power semiconductor elements to other parts of the device (fig. 36A numeral 3620). Eldridge also teaches using a bonding material and wires to connect power semiconductor elements to different structures (fig. 5 – 6C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the bonding material in Eldridge with the wires and main wiring boards in Taya to help prevent the wiring from disconnecting (Eldridge, Par. [0021]). For claim 2, Taya and Eldridge teach all of claim 1. Eldridge also teaches the wires being made of copper or copper alloy (Eldridge, Par. [0226 – 0227]) and the bonding material being made of solder (Par. [0094]; Par. [0251 – 0254]). For claim 3, Taya and Eldridge teach all of claim 2. Taya teaches both ends of each of the plurality of wires are bonded to a corresponding one of the plurality of main wiring boards so as to have a loop shape protruding form a lower surface of the corresponding one of the plurality of main wiring boards, and a tip of a loop is bonded to the upper surface electrode or a corresponding one of the plurality of power semiconductor elements (Taya, fig. 10 numeral 7 shows the wires forming a loop shape, the loop shape having a tip bonded to the upper surface of the electrode 4 and having ends bonded to one of the plurality of main wiring boards 5 and 10). Eldridge teaches attaching the ends of the wires using a bonding material (Eldridge, fig. 9A numeral 914; fig. 10F numeral 1052) . 07-21-aia AIA Claim (s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160300770 A1 hereinafter Taya in view of US 20100065963 A1 hereinafter Eldridge in further view of US 20090115049 A1 hereinafter Shiraishi . For claim 4, Taya and Eldridge teach all of claim 2. Taya also teaches the plurality of wires are bonded to the upper surface electrode of the corresponding one of the plurality of power semiconductor elements (Taya, fig. 10 numeral 4). Eldridge teaches using a bonding material to bond the wires to various elements including electrodes (Eldridge, Par. [0008]; fig. 2, Par. [0420 – 0424]; fig. 5 numeral 512 shows a terminal bonded to a wire 502 with a bonding material 544). Taya and Eldridge is silent regarding the case including an upper and lower portion, the lower portion is bonded to the base plate, and the upper portion is bonded to the lower portion. Taya does teach a lower part of the case bonded to the base plate (Taya, fig. 10 numeral 8; Par. [0028 - 0030]). Shirashi teaches a semiconductor package (Shirashi, fig. 3) including multiple power semiconductor elements (fig. 3 numeral 16A and 16B) bonded with wires (fig. 3 numeral 22). A case surrounds the power semiconductor elements (fig. 3 numeral 120) and comprises an upper and lower portion (fig. 3 numeral 12A and 12B). The upper and lower portions are bonded together (Par. [0032]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the upper and lower portion case in Shirashi with the power semiconductor elements and bonding material in Taya and Eldridge in order to access the power semiconductor elements in the device while assuring an airtight seal after construction (Shirashi, Par. [0032 – 0033]) while having a package with a reduced thickness (Par. [0002]; Par. [0016]) . 07-21-aia AIA Claim (s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160300770 A1 hereinafter Taya in view of US 20100065963 A1 hereinafter Eldridge in further view of US 20200126947 A1 hereinafter Karasawa . For claim 6, Taya and Eldridge teach all of claim 1. Taya also teaches the power semiconductor elements including a free wheeling diode (Taya, Par. [0027]) and switching elements including insulated gate bipolar transistors (IGBT). Taya and Eldridge are silent regarding the transistor being a reverse-conducting transistor. Karasawa teaches a power module (Karasawa, fig. 6 – fig. 8) with a free wheeling diode (fig. 6 numeral 25) and transistor elements including a reverse-conducting IGBT as a switching element (fig. 6 numeral 24; fig. 7 numeral 24; Par. [0041]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the reverse-conducting IGBT in Karasawa with the power semiconductor elements in Taya and Eldridge in order to handle both forward and reverse currents and to have a transistor with high voltage capacity and current capability . Response to Arguments 07-37 AIA Applicant's arguments filed 04/13/2026 have been fully considered but they are not persuasive. Applicant’s argument that the prior art Eldridge only relates to lower current devices is not persuasive as Eldridge appears to state that the teachings apply to a variety of electronic components including semiconductor wafer and dies, interposers, or other devices (Eldridge, Abstract) and does not specifically limit the bonding method to lower current devices. Specifically, Eldridge notes the bonding method can be used in a high current environment (Eldridge, Par. [0484]) and states the materials used are selected for their current-carrying capabilities (Par. [0516]). The only reference to low current applications in Eldridge appears to refer to the limit of using pure gold usage. However, Eldridge also provides the use of other metals for different applications (Par. [0563 – 0564]). Although low current devices may be preferred embodiment in Eldridge, Eldridge does not appear to limit itself to only low current devices or teach away from higher current devices. The prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed. See In re Fulton, 391 F.3d 1195, 1201, 73 USPQ2d 1141, 1146 (Fed. Cir. 2004). Applicant’s arguments that Taya teaches away from the sue of solder is not persuasive as Taya does use solder in multiple instances (Taya, Par. [0006];Par. [0026]; Par. [0032]) and does not appear to teach explicitly that solder should not be used. The problem to be solved in Taya is stress caused not by the solder, but by thermal differences between the plate shaped main terminal and the power semiconductor devices (Par. [0007]). Taya alleviates the stress through metal bumps created by ultrasonic welding. Taya does not state that solder is avoided or should not be used, only that the metal bumps alleviate the stress exerted. Taya does not appear to teach away from using other bonding techniques such as soldering, molding, or other techniques that apply another material to the wire such as taught in Eldridge. Taya and Eldridge do not appear to teach the ultrasonic welding preventing the use of solder or other bonding covering techniques in addition to the technique taught in Taya. Further, Taya directly teaches that the thermal expansion coefficient difference issue is addressed through the ultrasonic welding and would alleviate the stress exerted on solder joints (Par. [0007]). One of ordinary skill in the art before the effective filing date of the immediate invention would understand that the benefit of the ultrasonic welding in Taya can be combine with the benefits of the bonding material in Eldridge to obtain the befit of alleviating stress through the creation of the buffer layer in Taya (Par. [0007]) while also using the bonding material in Eldridge to help prevent the wiring from disconnecting (Eldridge, Par. [0021]). Taya does not appear to teach anywhere that the inclusion of solder or other bonding material with the ultrasonic welding would render the benefits of the ultrasonic welding useless. Applicant’s arguments that the prior art does not teach “power semiconductor elements” is not persuasive as it is unclear what a “power semiconductor element” is in context of the immediate invention. The immediate invention appears to be lacking written description that makes clear what a power semiconductor element is and what the difference is between a power semiconductor element and a semiconductor element is. See the above 112(a) rejection to claims 1 – 7 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20200328178 A1 teaches wire bonding with semiconductor chips using a bonding material surrounding the wires. US 20220157767 A1 teaches wires used to bond two circuit boards suing a U-shape in the wires and a bonding material on top of semiconductor chips. US 20210066175 A1 teaches multiple semiconductor elements bonded to wires through a bonding material and connected to wiring boards above the semiconductor elements. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.T.N./Examiner, Art Unit 2815 /MONICA D HARRISON/Primary Examiner, Art Unit 2815 Application/Control Number: 18/556,265 Page 2 Art Unit: 2815 Application/Control Number: 18/556,265 Page 3 Art Unit: 2815 Application/Control Number: 18/556,265 Page 4 Art Unit: 2815 Application/Control Number: 18/556,265 Page 5 Art Unit: 2815 Application/Control Number: 18/556,265 Page 6 Art Unit: 2815 Application/Control Number: 18/556,265 Page 7 Art Unit: 2815 Application/Control Number: 18/556,265 Page 8 Art Unit: 2815 Application/Control Number: 18/556,265 Page 9 Art Unit: 2815 Application/Control Number: 18/556,265 Page 10 Art Unit: 2815 Application/Control Number: 18/556,265 Page 11 Art Unit: 2815
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