Prosecution Insights
Last updated: April 19, 2026
Application No. 18/556,265

POWER MODULE

Non-Final OA §103§112
Filed
Oct 19, 2023
Examiner
NELSON, JACOB THEODORE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
3y 0m
To Grant
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
99 granted / 116 resolved
+17.3% vs TC avg
Moderate +10% lift
Without
With
+10.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
42 currently pending
Career history
158
Total Applications
across all art units

Statute-Specific Performance

§103
54.8%
+14.8% vs TC avg
§102
27.7%
-12.3% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 116 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) were submitted on 10/19/2023 and 06/11/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The abstract of the disclosure is objected to because the abstract repeats information given in the title. The language should be clear and concise and should not repeat information given in the title. Specifically, the abstract states “The present disclosure relates to a power module including…”. The title already states that the invention is a power module. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 3 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 3 recites the limitation "a bonding material" in line 5 of claim 3. There is insufficient antecedent basis for this limitation in the claim. Claim 1 states “a bonding material”. As claim 3 also states “a bonding material”. It is unclear if the bonding material in claim 1 and claim 3 are the same bonding material or different bonding materials, as claim 3 appears to introduce another bonding material that is not the same as the bonding material used in claim 1 but uses the same terminology as claim 1. This results in multiple interpretations wherein the bonding material in claim 1 is either the same bonding material as in claim 3 or the bonding material in claim 1 is a different bonding material than the bonding material in claim 3. As multiple interpretations are present, claim 3 is rejected as being indefinite. For the purpose of compact prosecution, examiner is interpreting claim 3 as “…with the bonding material”, so that the bonding material in claim 3 is the same bonding material as claim 2 and claim 1. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 – 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160300770 A1 hereinafter Taya in further view of US 20100065963 A1 hereinafter Eldridge. For claim 1, Taya teaches a power module (Taya, fig. 10) comprising a plurality of semiconductor elements (fig. 10 numeral 31 and 32) through which a main current flows in a thickness direction (Par. [0070]; Par. [0079]; fig. 10 shows the semiconductor elements 31 and 32 arranged in a thickness direction allowing for a current to flow through the elements in a thickness direction); a substrate on which the plurality of semiconductor elements are mounted (fig. 10 numeral 2); a base plate on which the substrate is mounted (fig. 10 numeral 1); a case that is bonded to the base plate and houses the plurality of semiconductor elements (fig. 10 numeral 8; Par. [0028]); a plurality of main wiring boards incorporated in an upper portion of the case on a side opposite to the base plate and arranged in parallel to the base plate (fig. 10 numeral 5); and a plurality of wires bonded to lower surfaces of the plurality of main wiring boards that face the plurality of semiconductor elements (fig. 10 numeral 7), wherein an upper surface electrode of each of the plurality of semiconductor elements is electrically connected to a corresponding one of the plurality of main wiring boards with the plurality of wires (fig. 10 numeral 4; Par. [0027] and [0029]). Although Taya does not explicitly state that the current flows in a thickness direction, the structure of Taya is capable of performing the intended use of the semiconductor elements, that being the current flow flowing in a thickness direction. Claim language referring intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). Taya is silent regarding a bonding material connecting the main wiring boards and the semiconductor elements. Eldridge teaches a forming power modules (Eldridge, Par. [0889]; fig. 36A – 36C) including semiconductor elements (fig. 36A numeral 3602, 3603) with wires (fig. 36A numeral 3610) and bonding material (fig. 36A numeral 3612) connecting the semiconductor elements to other parts of the device (fig. 36A numeral 3620). Eldridge also teaches using a bonding material and wires to connect semiconductor elements to different structures (fig. 5 – 6C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the bonding material in Eldridge with the wires and main wiring boards in Taya to help prevent the wiring from disconnecting (Eldridge, Par. [0021]). For claim 2, Taya and Eldridge teach all of claim 1. Eldridge also teaches the wires being made of copper or copper alloy (Eldridge, Par. [0226 – 0227]) and the bonding material being made of solder (Par. [0094]; Par. [0251 – 0254]). For claim 3, Taya and Eldridge teach all of claim 2. Taya teaches both ends of each of the plurality of wires are bonded to a corresponding one of the plurality of main wiring boards so as to have a loop shape protruding form a lower surface of the corresponding one of the plurality of main wiring boards, and a tip of a loop is bonded to the upper surface electrode or a corresponding one of the plurality of semiconductor elements (Taya, fig. 10 numeral 7 shows the wires forming a loop shape, the loop shape having a tip bonded to the upper surface of the electrode 4 and having ends bonded to one of the plurality of main wiring boards 5 and 10). Eldridge teaches attaching the ends of the wires using a bonding material (Eldridge, fig. 9A numeral 914; fig. 10F numeral 1052). Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160300770 A1 hereinafter Taya in view of US 20100065963 A1 hereinafter Eldridge in further view of US 20090115049 A1 hereinafter Shiraishi. For claim 4, Taya and Eldridge teach all of claim 2. Taya also teaches the plurality of wires are bonded to the upper surface electrode of the corresponding one of the plurality of semiconductor elements (Taya, fig. 10 numeral 4). Eldridge teaches using a bonding material to bond the wires to various elements including electrodes (Eldridge, Par. [0008]; fig. 2, Par. [0420 – 0424]; fig. 5 numeral 512 shows a terminal bonded to a wire 502 with a bonding material 544). Taya and Eldridge is silent regarding the case including an upper and lower portion, the lower portion is bonded to the base plate, and the upper portion is bonded to the lower portion. Taya does teach a lower part of the case bonded to the base plate (Taya, fig. 10 numeral 8; Par. [0028 - 0030]). Shirashi teaches a semiconductor package (Shirashi, fig. 3) including multiple semiconductor elements (fig. 3 numeral 16A and 16B) bonded with wires (fig. 3 numeral 22). A case surrounds the semiconductor elements (fig. 3 numeral 120) and comprises an upper and lower portion (fig. 3 numeral 12A and 12B). The upper and lower portions are bonded together (Par. [0032]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the upper and lower portion case in Shirashi with the semiconductor elements and bonding material in Taya and Eldridge in order to access the semiconductor elements in the device while assuring an airtight seal after construction (Shirashi, Par. [0032 – 0033]) while having a package with a reduced thickness (Par. [0002]; Par. [0016]). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160300770 A1 hereinafter Taya in view of US 20100065963 A1 hereinafter Eldridge in further view of US 20200126947 A1 hereinafter Karasawa. For claim 6, Taya and Eldridge teach all of claim 1. Taya also teaches the semiconductor elements including a free wheeling diode (Taya, Par. [0027]) and switching elements including insulated gate bipolar transistors (IGBT). Taya and Eldridge are silent regarding the transistor being a reverse-conducting transistor. Karasawa teaches a power module (Karasawa, fig. 6 – fig. 8) with a free wheeling diode (fig. 6 numeral 25) and transistor elements including a reverse-conducting IGBT as a switching element (fig. 6 numeral 24; fig. 7 numeral 24; Par. [0041]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the reverse-conducting IGBT in Karasawa with the semiconductor elements in Taya and Eldridge in order to handle both forward and reverse currents and to have a transistor with high voltage capacity and current capability. Allowable Subject Matter Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. For claim 5, Taya does teach a plurality of main wiring boards (Taya, fig. 10 numeral 10 and 5) that are connected to semiconductor elements (fig. 10 numeral 31 and 32) by wires (fig. 10 numeral 7) and that switching elements are present (Par. [0079]) with variable potentials (Par. [0079; Par. [0028]). However, Taya does not appear to teach an insulating material interposed between a second main wiring board and a first main wiring board and wherein a third main wiring board is connected to a connection node between the first switching element and a second switching element. Taya appears to teach gaps between the various boards that is filled with a sealant 11 in figure 10, but no distinct third board is shown connected to the two switching elements. The other prior art of record (Eldridge, Karasawa, and Shirashi) do not appear to teach the third main wiring board and the multiple switching elements connected to the third main wiring board while also having an insulating member between the first and second main wiring boards. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20210066175 A1 teaches a power module with multiple wiring boards with insulating members located in between two wiring boards and wires connecting semiconductor elements to wiring boards. The wires are shown to form loop shapes with bonding materials located on the wires. It appears to be silent regarding multiple switching elements with multiple potentials and a case with an upper and lower portion bonded together. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.T.N./Examiner, Art Unit 2815 /MONICA D HARRISON/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Oct 19, 2023
Application Filed
Jan 06, 2026
Non-Final Rejection — §103, §112
Mar 02, 2026
Interview Requested
Mar 04, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604592
DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME
2y 5m to grant Granted Apr 14, 2026
Patent 12588336
DISPLAY DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12575095
FLASH MEMORY AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 10, 2026
Patent 12575159
HIGH VOLTAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
2y 5m to grant Granted Mar 10, 2026
Patent 12538843
PIXEL UNIT AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Jan 27, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+10.3%)
3y 0m
Median Time to Grant
Low
PTA Risk
Based on 116 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month