Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species h Figure 8, in the reply filed on 9-18-2025 is acknowledged. The traversal is on the ground(s) that alleged duplicative patent applications and associated financial burdens may result from a restriction requirement. This is not found persuasive because the argument appears to be a boilerplate general allegation of restriction practice itself to be improper. No explicit specific error in the restriction or arguments that the inventions are not distinct were discussed as required by MPEP 818.
The requirement is still deemed proper and is therefore made FINAL.
Claims 4-6, 17-20, and 24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 9-18-2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9, 14-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, Claim 8 includes “second emission control signal and second light-emission control end” which do not appear to be in elected Figure 8. Furthermore, paragraph 142 of the instant specification includes: “In the pixel circuit in Fig. 8…both the first light-emission control end and the second light-emission control end are, but not limited to, the light-emission control end.” Thus, as best understood and for purposes of this Office Action second emission control signal and second light-emission control end will be interpreted to be correspondingly the same as the first emission control signal and the first light-emission control end, (i.e., EM1 in Figure 8). Claim 9 inherits this deficiency as dependent on claim 8. Claims 14 and 15 are similarly respectively rejected.
Claim 9 also includes a fourth initialization circuit, fourth initial voltage, and fourth initial voltage line without reference to a third initialization circuit, third initial voltage, and third initial voltage line. It is unclear as to whether a third is required to meet the limitations of the claim. As best understood and for purposes of this Office Action the fourth initialization circuit, fourth initial voltage, and fourth initial voltage line will be interpreted to be third initialization circuit, third initial voltage, and third initial voltage line. Claim 15 is similarly rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-11, 14, 15, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US App. 20210287605) in view of Park et al. (US App. 20230140902).
In regard to claim 1, Wang teaches a pixel circuit (see at least Fig. 5), comprising a driving circuit (T1), a first initialization circuit and a second bias circuit (Vint1 and Vbias); a control end of the driving circuit is electrically connected to a first node (N2), a first end of the driving circuit is electrically connected to a second node (N1), and a second end of the driving circuit is electrically connected to a third node (N3), and the driving circuit is configured to generate a current flowing from the second node to the third node under control of a potential at the first node (see Fig. 5 source and drain of transistor T1); the first initialization circuit is electrically connected to a first control end, a first initial voltage line and the first node, and configured to write a first initial voltage from the first initial voltage line into the first node under control of a first control signal from the first control end (T4 is connected to VINT1 and N2 while controlled by GI); the second bias circuit is electrically connected to control end, a second initial voltage line (Vbias) and the third node, and configured to write a second initial voltage from the second initial voltage line into the third node under control of a control signal end (see Fig. 5, T8 controlled by EB to apply Vbias to N3).
Wang is not relied upon to teach Bias is initialization; Control is a first scanning; and first scanning signal from the first scanning end.
However, Park teaches Bias is initialization (See Fig. 4,VINT2); Control is a first scanning (SIj); and first scanning signal from the first scanning end (SIj).
It would have been obvious to a person of ordinary skill in the art to modify the display of Wang to include the initialization of Park to improve display quality (See Para. 7-8). Examiner also notes Wang discloses the base product/process of a display with two initialization lines while Park teaches the known technique of multiple additional initialization voltage lines so as to yield predictable results of multiple initialization voltage lines in the device of pixel of Wang.
Regarding claim 2, Wang in view of Park teaches all the limitations of claim 1. Wang further teaches wherein the driving circuit comprises a driving transistor which is a p-type transistor, and a difference between a voltage value of the first initial voltage and a voltage value of the second initial voltage is less than a threshold voltage of the driving transistor (see Fig. 5, T1 is ptype); or, the driving circuit comprises a driving transistor which is an n-type transistor, and a difference between a voltage value of the first initial voltage and a voltage value of the second initial voltage is greater than a threshold voltage of the driving transistor.
Regarding claim 3, Wang in view of Park teaches all the limitations of claim 1. Wang further teaches further comprising a data written-in circuit (see Fig. 5, T2), a compensation control circuit and an energy storage circuit (T3 and CST); wherein, the data written-in circuit is electrically connected to a second scanning end, a data line and the second node (T2 between Dk and N1 with GW at the gate), and configured to write a data voltage on the data line into the second node under control of a second scanning signal from the second scanning end (T2 between Dk and N1 with GW at the gate); the compensation control circuit is electrically connected to a second control end, the first node and the third node (T3 between N2 and N3), and configured to control the first node to be electrically connected to, or electrically disconnected from, the third node under control of a second control signal from the second control end (T3 controlled by GC); a first end of the energy storage circuit is electrically connected to the first node, a second end of the energy storage circuit is electrically connected to a first voltage end, and the energy storage circuit is configured to store electric energy (CST is a capacitor between VDD and N2).
Regarding claim 8, Wang in view of Park teaches all the limitations of claim 1. Wang further teaches further comprising a light-emitting element (see Fig. 5, ED), a first light-emission control circuit and a second light-emission control circuit (T5 and T6); wherein, the first light-emission control circuit is electrically connected to a first light- emission control end, a power source voltage end and the first end of the driving circuit, and configured to control the power source voltage end to be electrically connected to, or electrically disconnected from, the first end of the driving circuit under control of a first light-emission control signal from the first light-emission control end (T5 controlled by EM between VDD and N1); the second light-emission control circuit is electrically connected to a second light- emission control end, the second end of the driving circuit and a first electrode of the light-emitting element, and configured to control the second end of the driving circuit to be electrically connected to, or electrically disconnected from, the first electrode of the light-emitting element under control of a second light-emission control signal from the second light-emission control end (T6 between N3/T1 and N4/ED and controlled by EM); a second electrode of the light-emitting element is electrically connected to a second voltage terminal (ED to Vss).
Regarding claim 9, Wang in view of Park teaches all the limitations of claim 8. Park further teaches comprising a fourth initialization circuit (See Fig. 4, T7); wherein the fourth initialization circuit is electrically connected to the first scanning end, a fourth initial voltage line and the first electrode of the light-emitting element, and configured to write a fourth initial voltage from the fourth initial voltage line into the first electrode of the light-emitting element under control of the first scanning signal from the first scanning end (T7 controlled by Sbj between T6 and ED to send voltage from VAINT).
It would have been obvious to a person of ordinary skill in the art to modify the display of Wang to include the initialization of Park to improve display quality (See Para. 7-8). Examiner also notes Wang discloses the base product/process of a display with two initialization lines while Park teaches the known technique of multiple additional initialization voltage lines so as to yield predictable results of multiple initialization voltage lines in the device of pixel of Wang.
Regarding claim 10, Wang in view of Park teaches all the limitations of claim 1. Wang further teaches wherein the driving circuit comprises a driving transistor (See Fig. 5, T1), the first initialization circuit comprises a second transistor (T4), and the bias circuit comprises a third transistor (T8); a gate electrode of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the second node, and a second electrode of the driving transistor is electrically connected to the third node (T1 connected to N1 and N3 as well as N2 at the gate); a gate electrode of the second transistor is electrically connected to the first control end (GI), a first electrode of the second transistor is electrically connected to the first initial voltage line (VINT1), and a second electrode of the second transistor is electrically connected to the first node (N2); and a second electrode of the third transistor is electrically connected to the third node (T8 connected to N3).
Wang is not relied upon to teach Bias circuit is second initialization circuit; a gate electrode of the third transistor is electrically connected to the first scanning end, a first electrode of the third transistor is electrically connected to the second initial voltage line,
However, Park teaches Bias circuit is second initialization circuit (see Fig. 4, T3_E and T4_E); a gate electrode of the third transistor is electrically connected to the first scanning end, a first electrode of the third transistor is electrically connected to the second initial voltage line (T3_E gate to SC_Ej and source to VINT2 through T4_E).
It would have been obvious to a person of ordinary skill in the art to modify the display of Wang to include the initialization of Park to improve display quality (See Para. 7-8). Examiner also notes Wang discloses the base product/process of a display with two initialization lines while Park teaches the known technique of multiple additional initialization voltage lines so as to yield predictable results of multiple initialization voltage lines in the device of pixel of Wang.
Regarding claim 11, Wang in view of Park teaches all the limitations of claim 3. Wang further teaches wherein the data written-in circuit comprises a fourth transistor (see Fig. 5, T2); a gate electrode of the fourth transistor is electrically connected to the second scanning end (GW controls T2), a first electrode of the fourth transistor is electrically connected to the data line (Dk), and a second electrode of the fourth transistor is electrically connected to the second node (N1); the energy storage circuit comprises a storage capacitor (CST); a first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to a power source voltage end (CST is between N2 and VDD).
Regarding claim 14, Wang in view of Park teaches all the limitations of claim 8. Wang further teaches wherein the first light- emission control circuit comprises a fifth transistor (T5), and the second light-emission control circuit comprises a sixth transistor (T6); a gate electrode of the fifth transistor is electrically connected to the first light- emission control end, a first electrode of the fifth transistor is electrically connected to the power source voltage end, and a second electrode of the fifth transistor is electrically connected to the first end of the driving circuit (T5 between T1 and VDD); a gate electrode of the sixth transistor is electrically connected to the second light- emission control end, a first electrode of the sixth transistor is electrically connected to the second end of the driving circuit, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element (T6 between T1 and ED controlled by EM).
Regarding claim 15, Wang in view of Park teaches all the limitations of claim 9. Park further teaches wherein the fourth initialization circuit comprises a seventh transistor(See Fig. 4, T7); a gate electrode of the seventh transistor is electrically connected to the first scanning end, a first electrode of the seventh transistor is electrically connected to the fourth initial voltage line, and a second electrode of the seventh transistor is electrically connected to the first electrode of the light-emitting element (T7 controlled by Sbj between T6 and ED to send voltage from VAINT).
It would have been obvious to a person of ordinary skill in the art to modify the display of Wang to include the initialization of Park to improve display quality (See Para. 7-8). Examiner also notes Wang discloses the base product/process of a display with two initialization lines while Park teaches the known technique of multiple additional initialization voltage lines so as to yield predictable results of multiple initialization voltage lines in the device of pixel of Wang.
Regarding claim 26, Wang in view of Park teaches all the limitations of claim 1. Wang further teaches a display device comprising the pixel circuit according to claim 1 (see Abstract and Fig. 5).
Allowable Subject Matter
Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kim et al. (US APP. 20210295784).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW YEUNG whose telephone number is (571)272-4115. The examiner can normally be reached M-F 9am-5pm EST.
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/MATTHEW YEUNG/Primary Examiner, Art Unit 2625