DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “the signal receiving module receives a data signal from a data signal source and transmits the data signal to the signal storage module and the switch module, the signal storage module is configured to store the data signal, the switch module is configured to transmit an adjustment current from the adjustment module to the light-emitting device; “wherein the mirror current source module is configured to adjust the adjustment currents input to the adjustment modules;” in claims 1 and 20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. Fig. 3 and 4 and pages 6-8 describes the structure for claimed signal receiving module, signal storage module, switch module and mirror current source module. Fig. 4 shows the signal receiving module and switch module as being transistors and storage module as being capacitor. Further fig. 4 shows the circuit of the mirror current source 200.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 6-8, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitoba et al (US Pub 2005/0174307) in view of Chen et al (US Pub 2007/0205968).
With respect to claim 1, Nishitoba discloses a display backplane, (fig. 3; display device with panel 50) comprising: a plurality of sub-pixel units (fig. 3; discloses the panel 50 comprises plurality of pixels 12), each of the sub-pixel units comprising a pixel drive circuit and a light-emitting device (fig. 4; discloses each pixel 12 comprises a light emitting element 3 and pixel drive circuit), wherein in each sub-pixel unit, the pixel drive circuit comprises a signal receiving module, (fig. 5; transistor 26) a signal storage module, (fig. 5; capacitor 27) a switch module, (fig. 5; transistor 28) and an adjustment module, (fig. 5; circuit 9) the signal receiving module receives a data signal from a data signal source and transmits the data signal to the signal storage module and the switch module, the signal storage module is configured to store the data signal, (par 0065; discloses The potential hold circuit 10 (i.e. receiving module 26 and storage capacitor 27) functions as a control circuit for controlling the turn-on and turn-off of the switch 11. The potential hold circuit 10 is configured to develop on the signal output 10a a potential substantially equal to the potential of the data signal generated on the data line 6 while the data-line control line 7 is activated, and to hold the potential of the signal output 10a while the data-line control line 7 is deactivated) the switch module is configured to transmit an adjustment current from the adjustment module to the light-emitting device (par 0065; discloses The potential hold circuit 10 functions as a control circuit for controlling the turn-on and turn-off of the switch 11; par 0070; discloses The switch 11 includes an N-channel MOS transistor 28. The N-channel MOS transistor 28 has a drain connected to the current output 9c of the current hold circuit 9, and a source connected to the organic EL element 3. A gate of the N-channel MOS transistor 28 is connected to the signal output 10a of the potential hold circuit 10);
Nishitoba discloses current supply circuit connected to each of the pixels (fig. 3; current supply circuit 13);
Nishitoba doesn’t expressly a mirror current source module, electrically connected to the adjustment modules of the pixel drive circuits, wherein the mirror current source module is configured to adjust the adjustment currents input to the adjustment modules; wherein the sub-pixel units comprise a plurality of first sub-pixel units, a plurality of second sub-pixel units, and a plurality of third sub-pixel units, wherein the first sub-pixel units, the second sub-pixel units, and the third sub-pixel unit emit different colors, and wherein the mirror current source module input different adjustment currents to the adjustment modules of the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units;
In the same field of endeavor, Chen discloses display device and driving method (see abstract); Chen discloses a mirror current source module, electrically connected to the adjustment modules of the pixel drive circuits, (fig. 4; driving device 413) wherein the mirror current source module is configured to adjust the adjustment currents input to the adjustment modules (par 0021; discloses the driving device of the above-mentioned OLED display includes a first current mirror, a second current mirror and a third current mirror to drive red sub-pixels, green sub-pixels and-blue sub-pixels); wherein the sub-pixel units comprise a plurality of first sub-pixel units, a plurality of second sub-pixel units, and a plurality of third sub-pixel units, wherein the first sub-pixel units, the second sub-pixel units, and the third sub-pixel unit emit different colors, (par 0033; discloses every display pixel 411 includes a plurality of sub-pixels, for example, a sub-pixel SP.sub.R, a sub-pixel SP.sub.G and a sub-pixel SP.sub.B. In the embodiment, the sub-pixels SP.sub.R, SP.sub.G and SP.sub.B correspond, but not limited to by the present invention, to red color, the green color and blue color) and wherein the mirror current source module input different adjustment currents to the adjustment modules of the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units (par 0034; discloses The driving device 413 provided by the present invention includes a current mirror CM 1, a current mirror CM2 and a current mirror CM3 for correspondingly receiving one of the data currents I.sub.data come from the driving circuit 430 and creating a driving current I.sub.R, a driving current I.sub.G and a driving current I.sub.B sent to the corresponding sub-pixels SP.sub.R, SP.sub.G and SP.sub.B, respectively);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba to incorporate the teachings of Chen to use individual current mirror source to supply the driving current to each of the subpixels of different color in order to achieve the full colorization goal of an OLED display by adjusting the luminance of sub-pixels by controlling the ratios between the channel width and channel length of the driving transistors in the current mirrors, so that the luminance ratios among the red sub-pixel, the green red sub-pixel and the blue red sub-pixel meet the requirement to form white light and to achieve the full colorization goal of an OLED display.
With respect to claim 2, Nishitoba as modified by Chen further discloses wherein the mirror current source module comprises a first mirror current unit, a second mirror current unit, and a third mirror current unit; the first mirror current unit is connected to the adjustment modules of at least one column of the first sub-pixel units; the second mirror current unit is electrically connected to the adjustment modules of at least one column of the second sub-pixel units; and the third mirror current unit is electrically connected to the adjustment modules of at least one column of the third sub-pixel units (Chen; par 0034; discloses the driving device 413 provided by the present invention includes a current mirror CM 1, a current mirror CM2 and a current mirror CM3 for correspondingly receiving one of the data currents I.sub.data come from the driving circuit 430 and creating a driving current I.sub.R, a driving current I.sub.G and a driving current I.sub.B sent to the corresponding sub-pixels SP.sub.R, SP.sub.G and SP.sub.B, respectively).
With respect to claim 6, Nishitoba as modified by Chen discloses wherein a first end of the signal receiving module is connected to a scan signal source (Nishitoba; fig. 5; discloses a gate electrode of the transistor 26 is connected to line 7); a second end of the signal receiving module is connected to the data signal source (Nishitoba ; fig. 5; discloses a second electrode of the transistor 26 is connected to data line 6); a third end of the signal receiving module, a first end of the signal storage module, and a first end of the switch module are connected to a first node (Nishitoba; fig. 5; third electrode of the transistor 26, a first electrode of the capacitor 27 and a gate electrode of the switch transistor 28 is connected to each other (i.e. first node)); a second end of the switch module is connected to the adjustment module; a third end of the switch module is connected to the light-emitting device (Nishitoba; fig. 5; disclose second electrode of the switch transistor 28 is connected to circuit 9 and third electrode of the transistor 28 is connected to light emitting element 3); and a second end of the signal storage module and the adjustment module are connected to a constant voltage high-level source (Nishitoba; fig. 5; discloses second electrode of the capacitor 27 and circuit 9 are connected to power line 1).
With respect to claim 7, Nishitoba as modified by Chen discloses wherein the switch module comprises a first transistor, (Nishitoba; fig. 5; discloses switch 11 comprises transistor 28) the signal receiving module comprises a second transistor, (Nishitoba; fig. 5; discloses signal receiving module comprises transistor 26) the adjustment module comprises a third transistor, (Nishitoba; fig. 5; discloses circuit 9 comprises transistor 23) and the signal storage module comprises a storage capacitor; (Nishitoba; fig. 5; storage capacitor 27) and a gate of the second transistor is connected to the scan signal source, (Nishitoba; fig. 5; discloses a gate electrode of the transistor 26 is connected to line 7) a source of the second transistor is connected to a first data signal source, (Nishitoba ; fig. 5; discloses a second electrode of the transistor 26 is connected to data line 6) a drain of the second transistor is connected to a first electrode of the storage capacitor and a gate of the first transistor, (Nishitoba; fig. 5; third electrode of the transistor 26, a first electrode of the capacitor 27 and a gate electrode of the switch transistor 28 is connected to each other (i.e. first node)) a source of the first transistor is connected to a drain of the third transistor, a drain of the first transistor is connected to an anode of the light-emitting device, (Nishitoba; fig. 5; disclose second electrode of the switch transistor 28 is connected to transistor 23 via transistor 25 and third electrode of the transistor 28 is connected to light emitting element 3) a source of the third transistor is connected to the constant voltage high-level source and a second electrode of the storage capacitor (Nishitoba; fig. 5; discloses second electrode of the capacitor 27 and an electrode of the transistor 23 are connected to power line 1), and a gate of the third transistor is connected to the mirror current source module (Nishitoba; fig. 5; discloses gate electrode of the transistor 23 is connected current line 4 via transistor 21 and 22).
With respect to claim 8, Nishitoba as modified by Chen discloses wherein the first transistor, the second transistor, and the third transistor are P-type transistors (Nishitoba; par 0067; discloses The current hold circuit 9 includes p-channel MOS transistors 22, 23; par 0105; discloses the N-channel MOS transistor 26 within the potential hold circuit 10 is replaced with a P-channel MOS transistor 26', and the N-channel MOS transistor 28 constituting the switch 11 is replaced with a P-channel MOS transistor 28').
With respect to claim 20, Nishitoba discloses a display device, comprising a display backplane, (fig. 3; display device with panel 50) comprising: a plurality of sub-pixel units (fig. 3; discloses the panel 50 comprises plurality of pixels 12), each of the sub-pixel units comprising a pixel drive circuit and a light-emitting device (fig. 4; discloses each pixel 12 comprises a light emitting element 3 and pixel drive circuit), wherein in each sub-pixel unit, the pixel drive circuit comprises a signal receiving module, (fig. 5; transistor 26) a signal storage module, (fig. 5; capacitor 27) a switch module, (fig. 5; transistor 28) and an adjustment module, (fig. 5; circuit 9) the signal receiving module receives a data signal from a data signal source and transmits the data signal to the signal storage module and the switch module, the signal storage module is configured to store the data signal, (par 0065; discloses The potential hold circuit 10 (i.e. receiving module 26 and storage capacitor 27) functions as a control circuit for controlling the turn-on and turn-off of the switch 11. The potential hold circuit 10 is configured to develop on the signal output 10a a potential substantially equal to the potential of the data signal generated on the data line 6 while the data-line control line 7 is activated, and to hold the potential of the signal output 10a while the data-line control line 7 is deactivated) the switch module is configured to transmit an adjustment current from the adjustment module to the light-emitting device (par 0065; discloses The potential hold circuit 10 functions as a control circuit for controlling the turn-on and turn-off of the switch 11; par 0070; discloses The switch 11 includes an N-channel MOS transistor 28. The N-channel MOS transistor 28 has a drain connected to the current output 9c of the current hold circuit 9, and a source connected to the organic EL element 3. A gate of the N-channel MOS transistor 28 is connected to the signal output 10a of the potential hold circuit 10);
Nishitoba discloses current supply circuit connected to each of the pixels (fig. 3; current supply circuit 13);
Nishitoba doesn’t expressly a mirror current source module, electrically connected to the adjustment modules of the pixel drive circuits, wherein the mirror current source module is configured to adjust the adjustment currents input to the adjustment modules; wherein the sub-pixel units comprise a plurality of first sub-pixel units, a plurality of second sub-pixel units, and a plurality of third sub-pixel units, wherein the first sub-pixel units, the second sub-pixel units, and the third sub-pixel unit emit different colors, and wherein the mirror current source module input different adjustment currents to the adjustment modules of the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units;
In the same field of endeavor, Chen discloses display device and driving method (see abstract); Chen discloses a mirror current source module, electrically connected to the adjustment modules of the pixel drive circuits, (fig. 4; driving device 413) wherein the mirror current source module is configured to adjust the adjustment currents input to the adjustment modules (par 0021; discloses the driving device of the above-mentioned OLED display includes a first current mirror, a second current mirror and a third current mirror to drive red sub-pixels, green sub-pixels and-blue sub-pixels); wherein the sub-pixel units comprise a plurality of first sub-pixel units, a plurality of second sub-pixel units, and a plurality of third sub-pixel units, wherein the first sub-pixel units, the second sub-pixel units, and the third sub-pixel unit emit different colors, (par 0033; discloses every display pixel 411 includes a plurality of sub-pixels, for example, a sub-pixel SP.sub.R, a sub-pixel SP.sub.G and a sub-pixel SP.sub.B. In the embodiment, the sub-pixels SP.sub.R, SP.sub.G and SP.sub.B correspond, but not limited to by the present invention, to red color, the green color and blue color) and wherein the mirror current source module input different adjustment currents to the adjustment modules of the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units (par 0034; discloses The driving device 413 provided by the present invention includes a current mirror CM 1, a current mirror CM2 and a current mirror CM3 for correspondingly receiving one of the data currents I.sub.data come from the driving circuit 430 and creating a driving current I.sub.R, a driving current I.sub.G and a driving current I.sub.B sent to the corresponding sub-pixels SP.sub.R, SP.sub.G and SP.sub.B, respectively);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba to incorporate the teachings of Chen to use individual current mirror source to supply the driving current to each of the subpixels of different color in order to achieve the full colorization goal of an OLED display by adjusting the luminance of sub-pixels by controlling the ratios between the channel width and channel length of the driving transistors in the current mirrors, so that the luminance ratios among the red sub-pixel, the green red sub-pixel and the blue red sub-pixel meet the requirement to form white light and to achieve the full colorization goal of an OLED display.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitoba et al (US Pub 2005/0174307) in view of Chen et al (US Pub 2007/0205968) and Kim et al (US Pub 2004/0080471).
With respect to claim 3, Nishitoba as modified by Chen further discloses wherein one of the first mirror current units is electrically connected to the adjustment modules of one column of the first sub-pixel units, one of the second mirror current units is electrically connected to the adjustment modules of one column of the second sub-pixel units, and one of the third mirror current units is electrically connected to the adjustment modules of one column of the third sub-pixel units (Chen; par 0034; discloses the driving device 413 provided by the present invention includes a current mirror CM 1, a current mirror CM2 and a current mirror CM3 for correspondingly receiving one of the data currents I.sub.data come from the driving circuit 430 and creating a driving current I.sub.R, a driving current I.sub.G and a driving current I.sub.B sent to the corresponding sub-pixels SP.sub.R, SP.sub.G and SP.sub.B, respectively);
Nishitoba as modified by Chen don’t expressly disclose wherein the mirror current source module comprises cascaded multiple first mirror current units, cascaded multiple second mirror current units, and cascaded multiple third mirror current units;
In the same field of endeavor, Kim discloses a display device and driving method (see abstract); Kim discloses wherein the mirror current source module comprises cascaded multiple first mirror current units, cascaded multiple second mirror current units, and cascaded multiple third mirror current units (par 0051; discloses In FIGS. 6 to 8, a data driver 46 may include a plurality of current sink data drive IC's 52a, 52b, 52c, . . . , which may be interconnected in a cascade circuit configuration. Each of the current sink data drive IC's 52a, 52b, 52c, . . . may include a reference current supply/path part 54a and a current sink data drive IC 54b that may be driven by a reference current from the reference current supply/path part 54a);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen to incorporate the teachings of Kim cascade connect the current mirror circuits in order to reduces output deviations between current mirror of same type and reduces a control time of a current source from an external voltage source.
Claim(s) 4, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitoba et al (US Pub 2005/0174307) in view of Chen et al (US Pub 2007/0205968) and CHO et al (US Pub 2022/0415227).
With respect to claim 4, Nishitoba as modified by Chen don’t expressly discloses wherein the sub- pixel units comprise a first sub-pixel group and a second sub-pixel group arranged along a column direction; and the display backplane comprises a first mirror current source module and a second mirror current source module mirrored on two sides of the sub-pixel units, the first mirror current source module is electrically connected to the adjustment modules of the first sub-pixel group, and the second mirror current source module is electrically connected to the adjustment modules in the second sub-pixel group;
In the same field of endeavor, CHO discloses display device wherein the sub- pixel units comprise a first sub-pixel group and a second sub-pixel group arranged along a column direction and the display backplane comprises a first mirror current source module and a second mirror current source module mirrored on two sides of the sub-pixel units, the first mirror current source module is electrically connected to the adjustment modules of the first sub-pixel group, and the second mirror current source module is electrically connected to the adjustment modules in the second sub-pixel group (par 0190; discloses the active area 610 may be divided into a seventh active area 6103 and an eighth active area 6104. The first driver 6301 may control an image signal output from the seventh active area 6103. The second driver 6302 may control an image signal output from the eighth active area 6104; par 0193; discloses the first driver 6301 may drive pixels (not shown) included in the seventh active area 6103 via fifth gate lines G1a_i and G1b_i, and may provide the image signal to the pixels (not shown) included in the seventh active area 6103 via the third data lines D1_j. Similarly, the second driver 6302 may drive pixels (not shown) included in the eighth active area 6104 via sixth gate lines G2a_i and G2b_i, and may provide the image signal to the pixels (not shown) included in the eighth active area 6104 via the fourth data lines D2_j.; see par 0194-0195 as well);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen to incorporate the teachings of CHO to divide panel into regions where each regions are controller using respective drivers in order to achieve a display panel that can be partially controlled as well as achieve a device that can be foldable and bendable.
With respect to claim 17, Nishitoba as modified by Chen don’t expressly discloses wherein the sub-pixel units comprise a first sub-pixel group and a second sub-pixel group arranged along a column direction; the display backplane comprises a first mirror current source module and a second mirror current source module arranged on two sides of the sub-pixel units; and the first mirror current source module is electrically connected to the adjustment modules in the first sub-pixel group, and the second mirror current source module is electrically connected to the adjustment modules in the second sub-pixel group;
In the same field of endeavor, CHO discloses display device wherein the sub-pixel units comprise a first sub-pixel group and a second sub-pixel group arranged along a column direction; the display backplane comprises a first mirror current source module and a second mirror current source module arranged on two sides of the sub-pixel units; and the first mirror current source module is electrically connected to the adjustment modules in the first sub-pixel group, and the second mirror current source module is electrically connected to the adjustment modules in the second sub-pixel group; (par 0190; discloses the active area 610 may be divided into a seventh active area 6103 and an eighth active area 6104. The first driver 6301 may control an image signal output from the seventh active area 6103. The second driver 6302 may control an image signal output from the eighth active area 6104; par 0193; discloses the first driver 6301 may drive pixels (not shown) included in the seventh active area 6103 via fifth gate lines G1a_i and G1b_i, and may provide the image signal to the pixels (not shown) included in the seventh active area 6103 via the third data lines D1_j. Similarly, the second driver 6302 may drive pixels (not shown) included in the eighth active area 6104 via sixth gate lines G2a_i and G2b_i, and may provide the image signal to the pixels (not shown) included in the eighth active area 6104 via the fourth data lines D2_j.; see par 0194-0195 as well);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen to incorporate the teachings of CHO to divide panel into regions where each regions are controller using respective drivers in order to achieve a display panel that can be partially controlled as well as achieve a device that can be foldable and bendable.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitoba et al (US Pub 2005/0174307) in view of Chen et al (US Pub 2007/0205968) and Yu (US Pub 2022/0122547).
With respect to claim 5, Nishitoba as modified by Chen further discloses further comprising a plurality of first transmission lines, a plurality of second transmission lines, and a plurality of third transmission lines, wherein the first mirror current unit is electrically connected to the corresponding adjustment modules through the first transmission lines, the second mirror current unit is electrically connected to the corresponding adjustment modules through the second transmission lines, and the third mirror current unit is electrically connected to the corresponding adjustment modules through the third transmission lines, (Chen; fig. 4; discloses the first current mirror circuit CM1 is connected to first column of pixels via a first transmission line, the second current mirror circuit CM2 is connected to second column of pixels via a second transmission line, and the third current mirror circuit CM3 is connected to third column of pixels via a third transmission line; see annotated fig. 4 below);
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Nishitoba as modified by Chen don’t expressly disclose wherein the first transmission lines, the second transmission lines, and the third transmission lines are arranged in different layers;
In the same field of endeavor, Yu discloses display device wherein the first transmission lines, the second transmission lines, and the third transmission lines are arranged in different layers (par 0161; discloses : providing a base substrate comprising a display area, and a peripheral area surrounding the display area and comprising a first peripheral area located on one side of the display area and a corner area adjacent to the first peripheral area; forming a plurality of sub-pixels located at the display area; forming a plurality of data lines located at the display area, electrically connected to the plurality of sub-pixels, and configured to provide a data signal to the plurality of sub-pixels; forming a plurality of power lines located at the display area, electrically connected to the plurality of sub-pixels, and configured to provide a first power signal to the plurality of sub-pixels… one of the plurality of data signal input lines, and at least two of the plurality of data lines; forming a first power bus located at the first peripheral area and the corner area, electrically connected to the plurality of power lines, and located in a different layer from the plurality of data signal input lines; forming a plurality of control signal connecting lines located in a different layer from the plurality of data signal input lines, and located between the first power bus and the display area, each of the plurality of control signal connecting lines is electrically connected to one of the plurality of control signal lines);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen to incorporate the teachings of Yu to arrange the plurality of transmission lines on different layers of the display substrate in order to increase the number of lines in the substrate while preventing any interferences between them.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitoba et al (US Pub 2005/0174307) in view of Chen et al (US Pub 2007/0205968), Kim et al (US Pub 2004/0080471) and Sun (US Pub 2005/0225517).
With respect to claim 9, Nishitoba as modified by Chen don’t expressly disclose wherein each of the mirror current units in the mirror current source module comprises a current source, a fourth transistor, a fifth transistor, and a sixth transistor; a first end of the current source is connected to a digital-to-analog converter; a second end of the current source is connected to a gate of the fifth transistor, a gate of the sixth transistor, and a source of the sixth transistor; drains of the fifth transistor and the sixth transistor are connected to a constant low-level voltage source; a source of the fifth transistor is connected to the gate of the third transistor, a gate of the fourth transistor, and a drain of the fourth transistor; and a source of the fourth transistor is connected to the constant high-level voltage source;
In the sane field of endeavor, Kim discloses a display device comprising pixel circuits where each pixel is connected to a current mirror; Kim discloses wherein each of the mirror current units in the mirror current source module comprises a current source, a fourth transistor, a fifth transistor, and a sixth transistor; (fig. 8; transistor D4 (i.e fourth transistor), D1 (i.e. sixth transistor), D2 (i.e. fifth transistor)) a second end of the current source is connected to a gate of the fifth transistor, a gate of the sixth transistor, and a source of the sixth transistor (fig. 8; discloses second end of the current source is connected to a gate of the fifth transistor D2, a gate of the sixth transistor D1, and a source of the sixth transistor D1) ; drains of the fifth transistor and the sixth transistor are connected to a constant low-level voltage source (fig. 8; discloses second electrode of the transistors D1 and D2 are grounded); a source of the fifth transistor is connected to the gate of the third transistor, a gate of the fourth transistor, and a drain of the fourth transistor (fig. 8; discloses first electrode of the transistor D2 is connected to gate of the transistor D5 (i.e. third transistor), a first and gate electrode of the transistor D4); and a source of the fourth transistor is connected to the constant high-level voltage source (fig. 8; discloses second electrode of the transistor D4 is connected to VDD2);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen to replace the current mirror of Chen with Kim’s current mirror in order to achieve a display panel that reduces a control time of a current source from an external voltage source while reduces output deviations between data drive IC's;
Nishitoba as modified by Chen and Kim don’t expressly disclose a first end of the current source is connected to a digital-to-analog converter;
In the same field of endeavor, Sun disclose a display device and driving method (see abstract); Sun discloses a first end of the current source is connected to a digital-to-analog converter (fig. 2; discloses current mirror 212 connected to DAC 210);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen and Kim to incorporate the teachings of Sun to connect one end of the current mirror to a DAC such that current mirrors can accurately generate the current for the pixels based on the data received from the driving circuits.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitoba et al (US Pub 2005/0174307) in view of Chen et al (US Pub 2007/0205968) and Jeong et al (US Pub 2020/0365070).
With respect to claim 16, Nishitoba as modified by Chen discloses further comprising a row scanning circuit, (Nishitoba; fig. 3; data-line control line drive circuit 16) and a column scanning circuit; (Nishitoba; fig. 3; data signal generating circuit 15) the row scanning circuit is connected to scan lines in the display backplane, and the column scanning circuit is connected to data lines in the display backplane (Nishitoba; par 0064; discloses the data lines 6 are connected to a data signal generating circuit 15, and the data-line control lines 7 are connected to a data-line control line drive circuit 16. The data-line control line drive circuit 16 scans and sequentially activates the data-line control lines 7. The data signal generating circuit 15 provides the pixels 12 connected to the activated constant current control lines 5 with data signals in parallel through the data lines 6);
Nishitoba as modified by Chen don’t expressly disclose a timing controller, a data processor; the timing controller transmits scan signals to the row scanning circuit and controls the data processor to transmit data signals to the column scanning circuit;
In the same field of endeavor, JEONG discloses display device and driving method (see abstract); JEONG discloses a timing controller, (fig. 1; timing controller 200) a data processor; (fig. 1; data processor 300) the timing controller transmits scan signals to the row scanning circuit and controls the data processor to transmit data signals to the column scanning circuit (par 0053; discloses The timing controller 200 may provide red, green, and blue grayscale data DATA1 to the data processor 300. The timing controller 200 may generate a first control signal CONT1 for controlling the driving of the data processor 300 and may provide the first control signal CONT1 to the data processor 300. The timing controller 200 may generate a second control signal CONT2 for controlling the driving of the data driver 400 and may provide the second control signal CONT2 to the data driver 400. The timing controller 200 may generate a third control signal CONT3 for controlling the driving of the scan driver 500 and may provide the third control signal CONT3 to the scan driver 500);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen to incorporate the teachings of JEONG to include timing controller and data processor such that row driver and column driver are operated in sync to supply data signal to the pixels in the panels in order to display the images accurately.
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nishitoba et al (US Pub 2005/0174307) in view of Chen et al (US Pub 2007/0205968) and Kim et al (US Pub 2015/0008405) and Lee et al (US Pub 2013/0181967).
With respect to claim 18, Nishitoba as modified by Chen don’t expressly disclose wherein each sub-pixel unit comprises multiple frames of display data, each frame of display data comprises multiple subframes, each subframe comprises a data writing phase and an illumination phase, and an illumination duration during the illumination phase varies among different subframes; and for each sub-pixel unit, when the data signal received by the sub-pixel unit during the data writing phase from the data signal source is at a high level, the sub-pixel unit continuously emits light during the corresponding illumination phase, and when the data signal received by the sub-pixel unit during the data writing phase from the data signal source is at a low level, the sub-pixel unit does not emit light during the corresponding illumination phase;
In the same field of endeavor, Kim discloses a display device and driving method (see abstract); Kim discloses wherein each sub-pixel unit comprises multiple frames of display data, each frame of display data comprises multiple subframes, each subframe comprises a data writing phase and an illumination phase, (par 0034; discloses Referring to FIG. 2, the frame 1F is divided into sub-frames SF1 to SF8. Each of the sub-frames SF1 to SF8 is divided into a scan period and an emission period. In the scan period, a scan signal is supplied to the scan lines S1 to Sn. In the scan period, a first data signal is supplied to the first data lines D11 to D1m and a second data signal is supplied to the second data lines D21 to D2m, in synchronization with the scan signal. par 0035; discloses In the emission period, pixels 40 receiving the first data signal of the turn-on state (or the second data signal of the turn-on state) emit light) and an illumination duration during the illumination phase varies among different subframes (par 0036; discloses he emission periods are set to be identical and/or different for the sub-frames SF1 to SF8, so that a predetermined gray scale may be implemented); when the data signal received by the sub-pixel unit during the data writing phase from the data signal source is at a turn-on level, the sub-pixel unit continuously emits light during the corresponding illumination phase, and when the data signal received by the sub-pixel unit during the data writing phase from the data signal source is at a turn-off level, the sub-pixel unit does not emit light during the corresponding illumination phase (par 0031; discloses The data driver 20 supplies the first and second data signals, so as to be synchronized with the scan signal for each scan period in the sub-frame. The first data signal may be set to a voltage at which a transistor receiving the first data signal is turned on or turned off. Similarly, the second data signal may be set to a voltage at which a transistor receiving the second data signal is turned on or turned off. In a case where the first data signal and/or the second signal are/is set to a turn-on voltage, the pixel 40 is set in the emission state, during an emission period following the scan period);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen to incorporate the teaching of Kim to divide the frame into plurality of sub-frames having different emission duration in order to implement predetermined grayscale while improving display quality;
Nishitoba as modified by Chen and Kim don’t expressly disclose turn-on data signal is a high level signal and turn-off signal is a low level signal;
In the same field of endeavor, Lee discloses a display device and driving method where Lee discloses turn-on data signal is a high level signal and turn-off signal is a low level signal (par 0072; discloses each of the plurality of pixels 110 may turn on the organic light emitting diode to emit light during a corresponding sub-frame when receiving the data signal having a logic high level, and turn off the organic light emitting diode not to emit light during the corresponding sub-frame when receiving the data signal having a logic low level.);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen and Kim to incorporate the teachings of Lee to use high level signal as turn-on signal and low level signal as turn-off signal and still achieve the same predictable result of controlling the pixel to emit light only during emission period.
With respect to claim 19, Nishitoba as modified by Chen don’t expressly disclose wherein each sub-pixel unit comprises multiple frames of display data, each frame of display data comprises multiple subframes, each subframe comprises a data writing phase and an illumination phase, and an illumination duration during the illumination phase varies among different subframes; and for each sub-pixel unit, when the data signal received by the sub-pixel unit during the data writing phase from the data signal source is at a low level, the sub-pixel unit continuously emits light during the corresponding illumination phase, and when the data signal received by the sub-pixel unit during the data writing phase from the data signal source is at a high level, the sub-pixel unit does not emit light during the corresponding illumination phase;
In the same field of endeavor, Kim discloses a display device and driving method (see abstract); Kim discloses wherein each sub-pixel unit comprises multiple frames of display data, each frame of display data comprises multiple subframes, each subframe comprises a data writing phase and an illumination phase, (par 0034; discloses Referring to FIG. 2, the frame 1F is divided into sub-frames SF1 to SF8. Each of the sub-frames SF1 to SF8 is divided into a scan period and an emission period. In the scan period, a scan signal is supplied to the scan lines S1 to Sn. In the scan period, a first data signal is supplied to the first data lines D11 to D1m and a second data signal is supplied to the second data lines D21 to D2m, in synchronization with the scan signal. par 0035; discloses In the emission period, pixels 40 receiving the first data signal of the turn-on state (or the second data signal of the turn-on state) emit light) and an illumination duration during the illumination phase varies among different subframes (par 0036; discloses he emission periods are set to be identical and/or different for the sub-frames SF1 to SF8, so that a predetermined gray scale may be implemented); when the data signal received by the sub-pixel unit during the data writing phase from the data signal source is at a turn-on level, the sub-pixel unit continuously emits light during the corresponding illumination phase, and when the data signal received by the sub-pixel unit during the data writing phase from the data signal source is at a turn-off level, the sub-pixel unit does not emit light during the corresponding illumination phase (par 0031; discloses The data driver 20 supplies the first and second data signals, so as to be synchronized with the scan signal for each scan period in the sub-frame. The first data signal may be set to a voltage at which a transistor receiving the first data signal is turned on or turned off. Similarly, the second data signal may be set to a voltage at which a transistor receiving the second data signal is turned on or turned off. In a case where the first data signal and/or the second signal are/is set to a turn-on voltage, the pixel 40 is set in the emission state, during an emission period following the scan period);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen to incorporate the teaching of Kim to divide the frame into plurality of sub-frames having different emission duration in order to implement predetermined grayscale while improving display quality;
Nishitoba as modified by Chen and Kim don’t expressly disclose turn-on data signal is a low level signal and turn-off signal is a high level signal;
In the same field of endeavor, Lee discloses a display device and driving method where Lee discloses turn-on data signal is a high level signal and turn-off signal is a low level signal (par 0072; discloses Each of the plurality of pixels 110 may turn on the organic light emitting diode to emit light during a corresponding sub-frame when receiving the data signal having a logic low level, and turn off the organic light emitting diode not to emit light during the corresponding sub-frame when receiving the data signal having a logic high level);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba as modified by Chen and Kim to incorporate the teachings of Lee to use low level signal as turn-on signal and high level signal as turn-off signal and still achieve the same predictable result of controlling the pixel to emit light only during emission period.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 10, Nishitoba in view of Chen or other prior art of record fails to disclose wherein the signal receiving module comprises a first receiving module and a second receiving module; a first end of the first receiving module and a first end of the second receiving module are connected to a scan signal source; a second end of the first receiving module is connected to a first data signal source, and a second end of the second receiving module is connected to a second data signal source; a third end of the second receiving module, a first end of the signal storage module, and a first end of the switch module are connected to a second node; a third end of the first receiving module and a second end of the signal storage module are connected to a third node N; a second end of the switch module is connected to the adjustment module, a third end of the switch module is connected to the light-emitting device, and a third end of the signal storage module and the adjustment module are connected to a constant voltage high-level source and it would not have been obvious to one having ordinary skill in the art to modify the invention disclosed by Nishitoba and Chen to arrive at the claimed invention as the final result would have been unpredictable. Hence claim 10 comprises allowable subject matter.
Claims 11-15 are objected for being directly or indirectly dependent on claim 10.
Conclusion
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/SUJIT SHAH/ Examiner, Art Unit 2624