DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set
forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this
application is eligible for continued examination under 37 CFR 1.114, and the fee set
forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action
has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on
06/26/2025 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/14/2025 is being
considered by the examiner.
Response to Amendment
The office action is responding to the arguments filed on 11/13/2025. Claims 1-12 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2,6,8 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over HASHIMOTO et al. (US 20120284453 A1) in view of Takayuki et al. (US 20180076833 A1) and further in view of Mathews et al. (US 20200159463 A1) hereinafter HASHIMOTO and Takayuki and Mathews.
Regarding claim 1, HASHIMOTO teaches An information processing apparatus comprising: a host unit that performs information processing; (“according to one embodiment, an information processing device includes a host device and an external storage device”) (paragraph [0037] line 1-2) (i.e. Fig 1 illustrates a information processing device with a host 100 and SSD 100)
a memory that stores data for use in the information processing; and (“The NAND memory 20 stores therein user data specified by the host 100, stores the management table in which the user data is managed, and stores the management information”) (paragraph [0053] line 1-2) (i.e. Fig 1 illustrates NAND flash memory 20 stores data, stores management information for information processing)
a memory controller configured to access to the memory according to a request from the host unit, wherein (“an interface controller 30 for transmitting and receiving signals with the host 100”) (paragraph [0051] line 2-3) (i.e. Fig 1 illustrates controller receiving signals including requests from host 100)
the memory controller is further configured to: upon switching switch the memory to a read-only mode and (see Fig 1, paragraph [0077], illustrates controller 30 is configured to switch read-only mode)
load a read-only mode firmware configured to: (see Fig 1, paragraph [0075], illustrates memory controller 50 executes system program firmware for different modes on flash memory 20)
using storage area of the memory controller that is released from a write operation control, wherein the read request queue stores read access requests issued by the host unit to access the memory (see Fig 1, paragraph [0084], illustrates IPL 55 selects section switches to select Read only controller and unselect read write controller after host send the read requests excluding write requests)
HASHIMOTO teaches information processing apparatus. However, HASHIMOTO does not appear to explicitly teach increase a polling frequency, of the memory controller, for read access requests from the host unit,
On the other hand, Takayuki which also relates to information processing apparatus appears to specifically teach increase a polling frequency, of the memory controller, for read access requests from the host unit, (see Fig 2 and 4, paragraph [0044] and [0055], illustrates CPU 110 performs a polling process repeating step 204-206 to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency)
Both HASHIMOTO and Takayuki relate to information processing apparatus. HASHIMOTO teaches to information processing apparatus with read and write requests. On the other hand, Takayuki also teaches information processing apparatus with read and write requests and CPU performing a polling process to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO with Takayuki to specify information processing apparatus with read and write requests and CPU performing a polling process to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency providing increase in the use efficiency of calculation resources in the host as mentioned in paragraph [0098].
HASHIMOTO in view of Takayuki teaches information processing apparatus. However, HASHIMOTO - Takayuki combination does not appear to explicitly teach and increase a depth of a read request queue, of the memory controller,
On the other hand, Mathews which also relates to information processing apparatus appears to specifically teach and increase a depth of a read request queue, of the memory controller (see Fig 2, paragraph [0086] and [0087], illustrates different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine HASHIMOTO with Takayuki for the reasons set forth
above. In addition, HASHIMOTO, Takayuki and Mathews are considered
analogous arts, because they all relate to information processing apparatus. HASHIMOTO - Takayuki combination teaches information processing apparatus with read and write requests. On the other hand, Mathews also teaches information processing apparatus with read and write requests and also different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO - Takayuki combination with Mathews to specify teaches information processing apparatus with read and write requests and also different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance providing access to memory efficiently which may include decisions for when to switch between read and write turns and how to order accesses to different memory banks as mentioned in paragraph [0005].
Regarding claim 2, HASHIMOTO in view of Takayuki and further in view of Mathews teaches information processing apparatus of claim 1. However, HASHIMOTO - Takayuki - Mathews combination does not appear to specifically teach The information processing apparatus according to claim 1, wherein the memory controller is configured to: switch the memory to the read-only mode responsive to the data for use in the information processing being completely stored under a read/write mode, in which both a read request and a request for data writing into the memory are received, wherein the host unit is configured to: continue information processing using read data by issuing a read request to the memory that is in the read-only mode
On the other hand, HASHIMOTO which also relates to information processing apparatus appears to specifically teach The information processing apparatus according to claim 1, wherein the memory controller is configured to: switch the memory to the read-only mode responsive to the data for use in the information processing being completely stored under a read/write mode, in which both a read request and a request for data writing into the memory are received (see Fig 1, paragraph [0045], illustrates SSD accepts read and write requests from host for WB, WT and RO mode)
(see Fig 1, paragraph [0077], illustrates controller 30 is configured to switch read-only mode)
wherein the host unit is configured to: continue information processing using read data by issuing a read request to the memory that is in the read-only mode (see Fig 1, paragraph [0135], illustrates host 100 issues read requests and receives read data from SSD 10)
The same motivation that was utilized for combining HASHIMOTO - Takayuki combination with Mathews as set forth in claim 1 is equally applicable to claim 2.
Regarding claim 6, HASHIMOTO teaches An information processing system comprising: an information processing apparatus that performs information processing; and (“according to one embodiment, an information processing device includes a host device and an external storage device”) (paragraph [0037] line 1-2) (i.e. Fig 1 illustrates a information processing device with a host 100 and SSD 100)
a server configured to provide data for use in the information processing to the information processing apparatus over a network, (“In FIG. 7, a SSD control tool 110C is stored in a storage medium 400 in a WEB server”) (paragraph [0089] line 1-2) (i.e. Fig 7 illustrates a network server 400 which is used to provide data same as SSD 10 for information processing)
wherein: the information processing apparatus includes a plurality of device drives, each device drive of the plurality of device drives including a memory that configured to store the data for use in the information processing provided by the server, and a memory controller, wherein for a first device drive of the plurality of device drives the memory is a first memory and the memory controller is a first memory controller that configured to: makes an access the corresponding first memory according to a request from a host unit, and (see Fig 6-9, paragraph [0088]- [0091], illustrate plurality of servers and drives each having its own controller)
(“In FIG. 7, a SSD control tool 110C is stored in a storage medium 400 in a WEB server, and the SSD control tool 110C is downloaded to the SSD 10 or the external storage device 300 through the LAN controller 208 or the like via a network such as the Internet, local network, and wireless LAN”) (paragraph [0089] line 1-4)
(“The external storage device may be other readable and writable nonvolatile storage device other than the SSD 10 such as a hard disc drive, a hybrid hard disc drive, USB memory, or an SD card”) (paragraph [0050] line 3-4) (i.e. Fig 7 illustrates a network server 400 downloads data to SSD 10 thru LAN controller 208 and SSD 10 can be a plurality of device drives)
responsive to the data for use in the information processing being completely stored in the first memory, (see Fig 12, paragraph [0105], illustrates interface driver converts the response to relevant interface to the OS 150 command which is stored in the information processor)
switching the memory to a read-only mode and (see Fig 1, paragraph [0077], illustrates controller 30 is configured to switch read-only mode)
load a read-only mode firmware configured to: (see Fig 1, paragraph [0075], illustrates memory controller 50 executes system program firmware for different modes on flash memory 20)
using storage area of the memory controller that is released from a write operation control, wherein the read request queue stores read access requests issued by the host unit to access the memory (see Fig 1, paragraph [0084], illustrates IPL 55 selects section switches to select Read only controller and unselect read write controller after host send the read requests excluding write requests)
HASHIMOTO teaches information processing apparatus. However, HASHIMOTO does not appear to explicitly teach increase a polling frequency, of the memory controller, for read access requests from the host unit,
On the other hand, Takayuki which also relates to information processing apparatus appears to specifically teach increase a polling frequency, of the memory controller, for read access requests from the host unit, (see Fig 2 and 4, paragraph [0044] and [0055], illustrates CPU 110 performs a polling process repeating step 204-206 to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency)
Both HASHIMOTO and Takayuki relate to information processing apparatus. HASHIMOTO teaches to information processing apparatus with read and write requests. On the other hand, Takayuki also teaches information processing apparatus with read and write requests and CPU performing a polling process to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO with Takayuki to specify information processing apparatus with read and write requests and CPU performing a polling process to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency providing increase in the use efficiency of calculation resources in the host as mentioned in paragraph [0098].
HASHIMOTO in view of Takayuki teaches information processing apparatus. However, HASHIMOTO - Takayuki combination does not appear to explicitly teach and increase a depth of a read request queue, of the memory controller,
On the other hand, Mathews which also relates to information processing apparatus appears to specifically teach and increase a depth of a read request queue, of the memory controller (see Fig 2, paragraph [0086] and [0087], illustrates different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine HASHIMOTO with Takayuki for the reasons set forth
above. In addition, HASHIMOTO, Takayuki and Mathews are considered
analogous arts, because they all relate to information processing apparatus. HASHIMOTO - Takayuki combination teaches information processing apparatus with read and write requests. On the other hand, Mathews also teaches information processing apparatus with read and write requests and also different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO - Takayuki combination with Mathews to specify teaches information processing apparatus with read and write requests and also different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance providing access to memory efficiently which may include decisions for when to switch between read and write turns and how to order accesses to different memory banks as mentioned in paragraph [0005].
Regarding claim 8, HASHIMOTO in view of Takayuki and further in view of Mathews teaches information processing apparatus of claim 6. However, HASHIMOTO - Takayuki - Mathews combination does not appear to specifically teach The information processing system according to claim 6, wherein the information processing apparatus is configured to: write data generated while performing information processing using the data read from the first memory that is in the read-only mode, into a second memory of another a second device drive of the plurality of device drives, wherein the second memory that is in a read/write model in which both a read request and a request for data writing into the second memory are received.
On the other hand, HASHIMOTO which also relates to information processing apparatus appears to specifically teach The information processing system according to claim 6, wherein the information processing apparatus is configured to: write data generated while performing information processing using the data read from the first memory that is in the read-only mode, into a second memory of another a second device drive of the plurality of device drives, wherein the second memory that is in a read/write model in which both a read request and a request for data writing into the second memory are received.
(see Fig 1, paragraph [0053], illustrates NAND flash memory 20 may be configured by plurality memory chips or drives)
(“The ROIF controller 32 has a function of receiving the read request, other requests excluding the write request, and data from the host 100, transmitting the received requests and data to the memory controller 50, and transmitting the data to the RAM 40 by the control of the memory controller 50”) (paragraph [0083] line 1-3)
(“The RWIF controller 31 has a function of receiving the read request, the write request, and other requests and data from the host 100, transmitting the received requests and data to the memory controller 50, and transmitting the data to the RAM 40 by the control of the memory controller 50”) (paragraph [0082] line 1-3)
(i.e. Fig 1 illustrates ROIF controller 32 receives read only request from host from host 100, transmits to memory controller 50. Also, RWIF controller 31 receives read and write request from host 100 and transmits to memory controller 50 to various memory devices (Fig 6) like ROM (read only) or other memory cells for write)
The same motivation that was utilized for combining HASHIMOTO - Takayuki combination with Mathews as set forth in claim 6 is equally applicable to claim 8.
Regarding claim 12, HASHIMOTO teaches An information processing method which is performed by an information processing apparatus, the method comprising: (“according to one embodiment, an information processing device includes a host device and an external storage device”) (paragraph [0037] line 1-2) (i.e. Fig 1 illustrates a information processing device with a host 100 and SSD 100 for storing data)
storing data for use in information processing, into a memory; (“The NAND memory 20 stores therein user data specified by the host 100, stores the management table in which the user data is managed, and stores the management information”) (paragraph [0053] line 1-2) (i.e. Fig 1 illustrates NAND flash memory 20 stores data, stores management information for information processing)
after the data storing is completed, switching the memory into a read-only mode, in which the memory is configured to of receiving receive only a request for reading of data stored in the memory; upon switching to the read-only mode.
(see Fig 1, paragraph [0077], illustrates controller 30 is configured to switch read-only mode)
loading read-only mode firmware configured to: (see Fig 1, paragraph [0075], illustrates memory controller 50 executes system program firmware for different modes on flash memory 20)
using storage area of the memory controller that is released from a write operation control, wherein the read request queue stores read access requests issued by the host unit issuing a read request to the memory; and performing information processing using data read out according to the read request (see Fig 1, paragraph [0084], illustrates IPL 55 selects section switches to select Read only controller and unselect read write controller after host send the read requests excluding write requests)
(see Fig 1, paragraph [0082], illustrates read requests are issued by host and processed by memory controller)
HASHIMOTO teaches information processing apparatus. However, HASHIMOTO does not appear to explicitly teach increase a polling frequency, of the memory controller, for read access requests from the host unit,
On the other hand, Takayuki which also relates to information processing apparatus appears to specifically teach increase a polling frequency, of the memory controller, for read access requests from the host unit, (see Fig 2 and 4, paragraph [0044] and [0055], illustrates CPU 110 performs a polling process repeating step 204-206 to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency)
Both HASHIMOTO and Takayuki relate to information processing apparatus. HASHIMOTO teaches to information processing apparatus with read and write requests. On the other hand, Takayuki also teaches information processing apparatus with read and write requests and CPU performing a polling process to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO with Takayuki to specify information processing apparatus with read and write requests and CPU performing a polling process to acquire information of the requests from host and to determine whether or not to switch responding method and also memory controller is configured to control access frequency providing increase in the use efficiency of calculation resources in the host as mentioned in paragraph [0098].
HASHIMOTO in view of Takayuki teaches information processing apparatus. However, HASHIMOTO - Takayuki combination does not appear to explicitly teach and increase a depth of a read request queue, of the memory controller,
On the other hand, Mathews which also relates to information processing apparatus appears to specifically teach and increase a depth of a read request queue, of the memory controller (see Fig 2, paragraph [0086] and [0087], illustrates different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance)
It would have been obvious to one of ordinary skill in the art at the time of
Applicant’s filing to combine HASHIMOTO with Takayuki for the reasons set forth
above. In addition, HASHIMOTO, Takayuki and Mathews are considered
analogous arts, because they all relate to information processing apparatus. HASHIMOTO - Takayuki combination teaches information processing apparatus with read and write requests. On the other hand, Mathews also teaches information processing apparatus with read and write requests and also different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO - Takayuki combination with Mathews to specify teaches information processing apparatus with read and write requests and also different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance providing access to memory efficiently which may include decisions for when to switch between read and write turns and how to order accesses to different memory banks as mentioned in paragraph [0005].
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over HASHIMOTO in view of Takayuki and further in view of Mathews and further in view of Tokumoto et al. (US 20210019090 A1) hereinafter Tokumoto.
Regarding claim 3, HASHIMOTO in view of Takayuki and further in view of Mathews teaches information processing apparatus of claim 2. However, HASHIMOTO - Takayuki - Mathews combination does not appear to specifically teach The information processing apparatus according to claim 2, wherein the memory controller is configured to: switch from a read/write mode firmware to the read-only mode firmware.
On the other hand, Tokumoto which also relates to information processing apparatus appears to specifically teach The information processing apparatus according to claim 2, wherein the memory controller is configured to: switch from a read/write mode firmware to the read-only mode firmware. (see Fig 4, paragraph [0041], illustrates RO and RW modes having associated firmware stored in storage area 302 (Fig 3))
Both HASHIMOTO, Takayuki, Mathews and Tokumoto relate to information processing apparatus with read only and write modes. HASHIMOTO – Takayuki - Mathews combination teaches information processing apparatus with read only and write modes. On the other hand, YANO also teaches information processing apparatus with read only and write modes and RO and RW modes having associated firmware stored in storage area. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO - Takayuki - Mathews combination with Tokumoto to specify information processing apparatus with read only and write modes and RO and RW modes having associated firmware stored in storage area.
Regarding claim 4, HASHIMOTO in view of Takayuki and further in view of Mathews and further in view of Tokumoto teaches information processing apparatus of claim 3. However, HASHIMOTO- Takayuki - Mathews - Tokumoto combination does not appear to specifically teach The information processing apparatus according to claim 3, wherein the host unit is configured to, responsive to switching the memory to the read-only mode, remount a device drive that includes the memory controller
On the other hand, HASHIMOTO which also relates to information processing apparatus appears to specifically teach The information processing apparatus according to claim 3, wherein the host unit is configured to, responsive to switching the memory to the read-only mode, remount a device drive that includes the memory controller (“restarts the SSD 10 and switches the interface driver 120 from the RWIF driver 121 to the ROIF driver 122”) (paragraph [0107] line 7-8) (i.e. Restarting SSD 10 is performed by switching driver from RWIF 121 (Fig 1) to ROIF 122 (Fig 1))
The same motivation that was utilized for combining HASHIMOTO- Takayuki - Mathews combination with Tokumoto as set forth in claim 3 is equally applicable to claim 4.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over HASHIMOTO in view of Takayuki and further in view of Mathews and further in view of LEE et al. (US 20170109074 A1) hereinafter LEE.
Regarding claim 5, HASHIMOTO in view of Takayuki and further in view of Mathews teaches information processing apparatus of claim 2. However, HASHIMOTO - Takayuki - Mathews combination does not appear to specifically teach The information processing apparatus according to claim 2, wherein the memory is a first memory and the memory controller is a first memory controller and the first memory and the first memory controller are part of a first device drive, the apparatus further comprising: a second device drive coupled with the host, the second device drive including a second memory and a second memory controller configured to access the second memory according to a second memory based request from the host unit, wherein the second memory controller is configured to operate the second memory in the read/write mode when the first memory is in the read-only mode.
On the other hand, LEE which also relates to information processing apparatus appears to specifically teach The information processing apparatus
according to any one of claims 2, further comprising: a plurality of device drives each including the memory and the memory controller that makes an access to the memory, wherein in a certain time period, any one of the memory controllers realizes the read-only mode while another memory controller realizes the read/write mode. (see Fig 1, paragraph [0059], illustrates first memory 130 and second memory 150 may work as read-only or write bypass mode and write modes)
Both HASHIMOTO, Takayuki, Mathews and LEE relate to information processing apparatus with read only and write modes. HASHIMOTO - Takayuki - Mathews combination teaches information processing apparatus with read only and write modes. On the other hand, LEE also teaches information processing apparatus with read only and write modes and first memory and second memory may work as read-only and write modes. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO - Takayuki - Mathews combination with LEE to specify information processing apparatus with read only and write modes and first memory and second memory may work as read-only and write modes.
Claim(s) 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over HASHIMOTO in view of Takayuki and further in view of Mathews and further in view of SAITO et al. (US 20200073793 A1) hereinafter SAITO.
Regarding claim 7, HASHIMOTO in view of Takayuki and further in view of Mathews teaches information processing apparatus of claim 6. However, HASHIMOTO- Takayuki - Mathews combination does not appear to specifically teach The information processing system according to claim 6, wherein the information processing apparatus is configured to: while progressing performing the information processing using the data read out from the first memory that is in the read-only mode, acquire data for use in information processing to be performed next, from the server, and store the acquired data into a second memory of a second device drive of the plurality of device drives, wherein the second memory is in a read/write mode in which both a read request and a request for data writing into the second memory are received
On the other hand, SAITO which also relates to information processing apparatus appears to specifically teach The information processing system according to claim 6, wherein the information processing apparatus is configured to: while progressing performing the information processing using the data read out from the first memory that is in the read-only mode, acquire data for use in information processing to be performed next, from the server, and store the acquired data into a second memory of a second device drive of the plurality of device drives, wherein the second memory is in a read/write mode in which both a read request and a request for data writing into the second memory are received. (“the host unit 12 reads application programs and data from a recording medium driven in a recording medium driving block not illustrated or downloads application programs and data from a server network-connected by a communication block into the flash memory 20. At this moment, the host unit 12 issues an access request to the flash controller 18 for accessing the flash memory 20 and, in response thereto, the flash controller 18 executes read/write processing on the flash memory 20”) (paragraph [0022] line 2-6) (i.e. Fig 1 illustrates host 12 reads application data and programs server from server network-connected by communication block and then host issues access request to flash controller 18 for accessing flash memory 20 and executed read/write from flash memory 20)
Both HASHIMOTO, Takayuki, Mathews and SAITO relate to information processing apparatus with read only and write modes. HASHIMOTO- Takayuki - Mathews combination teaches information processing apparatus with read only and write modes from external storages. On the other hand, SAITO also teaches information processing apparatus with read only and write modes with storages that includes network server. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO- Takayuki - Mathews combination with SAITO to specify information processing apparatus with read only and write modes with storages that includes network server providing more options for storages.
Regarding claim 9, HASHIMOTO in view of Takayuki and further in view of Mathews teaches information processing apparatus of claim 8. However, HASHIMOTO- Takayuki - Mathews combination does not appear to specifically teach The information processing system according to claim 8, wherein the information processing apparatus is configured to: switch the first device drive that is in the read-only mode to the read/write mode at a predetermined time, and subsequent to the switch, copy the written in the second memory of the other second device driver drive, into the first memory of the first device drive
On the other hand, SAITO which also relates to information processing apparatus appears to specifically teach The information processing system according to claim 8, wherein the information processing apparatus is configured to: switch the first device drive that is in the read-only mode to the read/write mode at a predetermined time, and subsequent to the switch, copy the written in the second memory of the other second device driver drive, into the first memory of the first device drive. (“FIG. 4, there is illustrated a setting example of the types of queues to be processed in each phase, the processing upper limits of commands in each phase, and time limits. In this example, there are provided five phases, phase 1 through phase 5 that are cycled from phase 1, to phase 2, to phase 3, to phase 4, to phase 5, to phase 1, to phase 2, and so on, and are transitioned. First, in phase 1, the read-only queues”) (paragraph [0057] line 1-2) (i.e. Fig 4 table illustrates 5 modes starting from read only mode in phase 1 and read write mode in phase 2 transitions according to time limit in required time column (last column))
Both HASHIMOTO, Takayuki, Mathews and SAITO relate to information processing apparatus with read only and write modes. HASHIMOTO- Takayuki - Mathews combination teaches information processing apparatus with read only and write modes with no timing information. On the other hand, SAITO also teaches information processing apparatus with read only and write modes with fixed timing for each mode. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO- Takayuki - Mathews combination with SAITO to specify information processing apparatus with read only and write modes with fixed timing for each mode providing timing determination when to switch from read only to read write mode.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over HASHIMOTO in view of Takayuki and further in view of Mathews and further in view of UCHIGAITO et al. (US 20170003911 A1) hereinafter UCHIGAITO.
Regarding claim 10, HASHIMOTO in view of Takayuki and further in view of Mathews teaches information processing apparatus of claim 8. However, HASHIMOTO- Takayuki - Mathews combination does not appear to specifically teach The information processing system according to any one of claims 6, wherein the plurality of device drives are connected in parallel with the host unit via a switch.
On the other hand, UCHIGAITO which also relates to information processing apparatus appears to specifically teach The information processing system according to any one of claims 6, wherein the plurality of device drives are connected in parallel with the host unit via a switch. (“In the example of FIG. 7, storing destinations of data in one group are set across channels Ch. 1 to Ch. i having the same way number, where access is performed in a parallel manner”) (paragraph [0092] line 2-3)
(“the memory subsystem control module 60 dynamically changes a write area of the nonvolatile memory 80 according to a size of data of a write request”) (paragraph [0093] line 3-4) (i.e. Fig 7 illustrates storage destinations are working in parallel thru a module 60 similar to switch which dynamically determines the storage area for write request)
Both HASHIMOTO, Takayuki, Mathews and UCHIGAITO relate to information processing apparatus with read only and write modes. HASHIMOTO - Takayuki - Mathews combination teaches information processing apparatus with read only and write modes with no information of how the storage devices are oriented. On the other hand, UCHIGAITO also teaches information processing apparatus with read only and write modes and storage devices being connected in parallel. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO - Takayuki - Mathews combination with UCHIGAITO to specify information processing apparatus with read only and write modes and storage devices being connected in parallel providing simultaneous access.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over HASHIMOTO in view of Takayuki and further in view of Mathews and further in view of KE et al. (US 20210334209 A1) hereinafter KE.
Regarding claim 11, HASHIMOTO in view of Takayuki and further in view of Mathews teaches information processing apparatus of claim 8. However, HASHIMOTO- Takayuki - Mathews combination does not appear to specifically teach The information processing system according to any one of claims 6, wherein the plurality of device drives are cascade-connected with the host unit
On the other hand, KE which also relates to information processing apparatus appears to specifically teach The information processing system according to any one of claims 6, wherein the plurality of device drives are cascade-connected with the host unit. (“NAND flash devices, on the other hand, are not random access but serial access”) (paragraph [0003] line 2-3) (i.e. NAND flash devices in Fig 2 are in serial or cascaded access for operations)
Both HASHIMOTO, Takayuki, Mathews and KE relate to information processing apparatus with read only and write modes. HASHIMOTO- Takayuki - Mathews combination teaches information processing apparatus with read only and write modes with no information of how the storage devices are oriented. On the other hand, KE also teaches information processing apparatus with read only and write modes and storage devices being connected in serial or cascaded way. Therefore, it would have been obvious to one of ordinary skill at the time the invention was effectively filed to combine HASHIMOTO- Takayuki - Mathews combination with KE to specify information processing apparatus with read only and write modes and storage devices being connected in serial or cascaded way.
Response to Arguments
Applicant’s arguments filed on 11/13/2025 have been fully considered but they
are not persuasive.
Applicant’s first argument is claims 1, 6 and 12 mapping by reference
Takayuki in page 3 of the response: These portions of Takayuki cited in the office action do not teach or suggest the
abovementioned features of claim 1 because the cited portions are silent regarding a "read request queue," and therefore cannot possibly describe a memory controller configured to "increase a depth of a read request queue, of the memory controller," as recited in claim 1. While Figure 2 of Takayuki illustrates a memory controller 200 managing data transfer between a host 210 and one or more non-volatile memories (NVM 230), neither this figure nor its corresponding descriptive paragraphs shows or describes a "read request queue," associated with the memory controller 200, let alone increasing the depth of such a read request queue
In summary, applicant argued that primary and secondary references do not teach claim read request queue and increase in read request queue.
The new IDS necessitates adding secondary reference Mathews in this regard. For
further clarification examiner cites portion from Mathews. Also, for applicant’s
understanding examiner would like to explain the teachings of Mathews and examiner’s
interpretation in more detail here. see Fig 2, paragraph [0086] and [0087], Mathews teaches different thresholds maybe used to determine read and write queue depths and based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance. The cited portion along with Fig 2 clearly teaches read and write request queues and determining the depth of read and write queues based on threshold if depth of read or write queue gets larger burst of read or write are allowed to improve performance. Thus, the rejection of independent claims is maintained
Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 11/14/2025 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.K.C./Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132