DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US Patent/PGPub. No. 20230079023).
Regarding Claim 1, (Original)
Lee et al. teach
an array substrate ([0082], FIG. 2, i.e. substrate 100), comprising a voltage supply network ([0153], FIG. 5, i.e. display driver 31 may supply a driving power voltage ELVDD … may be applied to each pixel circuit PC through a driving voltage line PL);
wherein the voltage supply network (i.e. please see above citation(s)) comprises, in a corner region of a peripheral area (FIG. 5, i.e. lower and upper corners as shown by the figure(s)):
a first peripheral voltage supply line ([0153], FIG. 5, i.e. driver 31 may supply a driving power voltage ELVDD);
a plurality of second peripheral voltage supply lines ([0153], FIG. 5, i.e. a driving voltage line PL (please note that the figure shows ONLY one PL line for each pixel)); and
an electrical connecting structure ([0150], FIG. 5, i.e. driving voltage supply line 11) configured to connect ([0150], FIG. 5, i.e. ELVDD … through a driving voltage line PL connected to the driving voltage supply line 11) the plurality of second peripheral voltage supply lines with the first peripheral voltage supply line (i.e. please see above citation(s));
wherein the electrical connecting structure (i.e. please see above citation(s)) crosses over (FIG. 5, i.e. ELVDD are distributed through PLs by driving voltage supply line 11 from driver 31 as shown by the figure(s)) at least one of the plurality of second peripheral voltage supply lines (i.e. please see above citation(s)).
Regarding Claim 2, (Original)
Lee et al. teach
the array substrate of claim 1, wherein the plurality of second peripheral voltage supply lines (i.e. please see above citation(s)) are spaced apart from (FIG. 5, i.e. PL lines are spaced apart from ELVDD by 11 as shown by the figure(s)) the first peripheral voltage supply line (i.e. please see above citation(s)), respectively, by different distances (FIG. 7, i.e. PL lines which are continuation of CLV lines extending at the top of the display would have been longer (different distances) than those at the bottom as shown by the figure(s)).
Regarding Claim 3, (Original)
Lee et al. teach
the array substrate of claim 1, further comprising voltage supply lines ([0204], FIG. 14, i.e. plurality of vertical driving voltage lines PLV) extending along a first direction ([0204], FIG. 14, i.e. column direction) through a plurality of pixel driving circuit regions ([0153], FIG. 5, i.e. pixel circuit PC) in a display area ([0069], FIG. 5, i.e. display area DA), the plurality of pixel driving circuit regions being adjacent to the corner region (i.e. please see above citation(s));
wherein a respective second peripheral voltage supply line ([0204], FIG. 14, i.e. driving voltage line PL) of the plurality of second peripheral voltage supply lines is connected to multiple voltage supply lines ([0204], FIG. 14, i.e. plurality of vertical driving voltage lines PLV) extending through a respective region ([0150], FIG. 5, i.e. pixel circuits PC3/PC2/PC1) of the plurality of pixel driving circuit regions (i.e. please see above citation(s)); and
the plurality of pixel driving circuit regions (i.e. please see above citation(s)) are spaced apart from (FIG. 5, i.e. as shown by the figure(s)) the first peripheral voltage supply line, respectively, by different distances (FIG. 5, i.e. the pixel driving circuits for those on top of the display would have different distances from those at the bottom as shown by the figure(s)).
Regarding Claim 4, (Original)
Lee et al. teach
the array substrate of claim 3, wherein the electrical connecting structure is at least partially in a region (FIG. 5, i.e. driving voltage supply line 11 is partially in between driver 31 (ELVDD) and display area DA as shown by the figure(s)) between the first peripheral voltage supply line and the plurality of pixel driving circuit regions.
Regarding Claim 5, (Currently Amended)
Lee et al. teach
the array substrate of claim 1, wherein an orthographic projection (FIG. 5, i.e. an orthographic projection of 11 would have been the same as 11 itself on substrate 100 since FIG. 5 illustrate a top view as shown by the figure(s)) of the electrical connecting structure on a base substrate at least partially overlaps with (FIG. 5, i.e. ELVDD are distributed through PLs by driving voltage supply line 11 from driver 31 as shown by the figure(s)) an orthographic projection (FIG. 5, i.e. an orthographic projection of PL/ELVDD would have been the same as PL/ELVDD itself on substrate 100 since FIG. 5 illustrate a top view as shown by the figure(s)) of at least one of the plurality of second peripheral voltage supply lines on the base substrate (i.e. please see above citation(s)).
Regarding Claim 6, (Currently Amended)
Lee et al. teach
the array substrate of claim 1, wherein the electrical connecting structure comprises a plurality of first connecting lines ([0153], FIG. 5, i.e. ELVDD (please note that there are two ELVDD lines connected to driving voltage supply line 11 from the bottom left and right sides, shown by the figure)); and
a respective first connecting line ([0153], FIG. 5, i.e. each ELVDD (left/right)) of the plurality of first connecting lines electrically connects ([0153], FIG. 5, i.e. (ELVDD connects to driving voltage supply line 11 that branches out to PLs as shown by the figure)) at least one of the plurality of second peripheral voltage supply lines with the first peripheral voltage supply line (i.e. please see above citation(s)).
Regarding Claim 7, (Original)
Lee et al. teach
the array substrate of claim 6, wherein the electrical connecting structure (i.e. please see above citation(s)) electrically connects the plurality of second peripheral voltage supply lines with each other ([0153], FIG. 5, i.e. ELVDD may be applied to each pixel circuit PC through a driving voltage line PL), through one or more of the plurality of first connecting lines (i.e. please see above citation(s)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Patent/PGPub. No. 20230079023) in view of BANG et al. (US Patent/PGPub. No. 20220320248).
Regarding Claim 20, (Currently Amended)
Lee et al. teach
a display apparatus ([0069], FIG. 1, i.e. electronic apparatus 1 may include a display area DA), comprising the array substrate of claim 1 (i.e. please see above citation(s)).
However, Lee et al. do not explicitly teach
one or more integrated circuits connected to the array substrate.
In the same field of endeavor, BANG et al. teach
one or more integrated circuits ([0010], FIG. 2, i.e. scan driver) connected to the array substrate ([0010], FIG. 2, i.e. in the non-display area of the substrate).
It would have been obvious to a person having ordinary skill in the art at the time the invention’s effective date was filed to realize that Lee et al. teaching a display comprising display driver and power supply network would have been included scan driver and other electronics essential to drive pixels in the display similar to BANG et al. teaching a display including power supply network and scan driver to effectively distribute scan signal to plurality of scan lines of the display (BANG et al.’s [0010]).
Allowable Subject Matter
4. Claim(s) 8-19 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
5. The following is an examiner’s statement of reasons for allowance:
Lee et al. (US Patent/PGPub. No. 20230079023) teach a display device includes first light emitting elements and first pixel circuits in a first display area and connected to each other, second pixel circuits in a third display area and connected to second light emitting elements in a second display area, a first initialization voltage supply line to provide a first initialization voltage to the first pixel circuits, a second initialization voltage supply line to provide a second initialization voltage to the second pixel circuits, and a connection line-pattern unit including horizontal connection lines extending in a row direction and vertical connection lines extending in a column direction. A first vertical connection line of the connection line-pattern unit is connected to the pad unit. A second horizontal connection line of the connection line-pattern unit is to connect the second pixel circuits to the second initialization voltage supply line.
BANG et al. (US Patent/PGPub. No. 20220320248) teach a display device includes a display area having a pixel, a non-display area, and a non-display sub-region including a first area and a bending area, along a first direction, and a first power line which is in the non-display area and the first area and transmits a power voltage to the pixel, the first power line including a first and a second power connection portion spaced apart from each other in the first direction, and a first power path portion and a second power path portion which are spaced apart from each other along a second direction and connect the first and second power connection portions to each other. The length of the non-display sub-region is smaller than the length of the non-display area, and the first power path portion is closer to the outer edge of the non-display sub-region than the second power path portion.
The subject matter of the independent claims could either not be found or was not suggested in the prior art of record. The subject matter not found was a substrate of display device including
“…at least a first one of the plurality of first connecting lines electrically connects each of the plurality of second peripheral voltage supply lines with the first peripheral voltage supply line; and
at least a second one of the plurality of first connecting lines electrically connects only one of the plurality of second peripheral voltage supply lines with the first peripheral voltage supply line.” (Claim 8),
“…the electrical connecting structure further comprises a plurality of third peripheral voltage supply lines;
wherein the plurality of first connecting lines and the plurality of third peripheral voltage supply lines interconnect with each other; and
an orthographic projection of the plurality of third peripheral voltage supply lines on a base substrate at least partially overlaps with an orthographic projection of the plurality of second peripheral voltage supply lines on the base substrate.” (Claim 9),
“…the electrical connecting structure comprises a connecting plate; and
the connecting plate is in a layer different from the first peripheral voltage supply line and the plurality of second peripheral voltage supply lines.” (Claim 12),
“…the electrical connecting structure is in an additional display area where multiple light emitting elements are present, and transistors and capacitors of multiple pixel driving circuits are absent;
the array substrate further comprises a plurality of anode connecting pads extending from a display area into the additional display area; and
a respective anode connecting pad of the plurality of anode connecting pads electrically connects an anode of a respective light emitting element of the multiple light emitting elements in the additional display area to a respective pixel driving circuit of the multiple pixel driving circuits in the display area.” (Claim 16),
in combination with the other elements (or steps) of the device or apparatus and method recited in the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH TANG LAM whose telephone number is (571) 270-3704. The examiner can normally be reached Monday to Friday 8:00 AM to 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin K Patel can be reached at (571) 272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VINH T LAM/Primary Examiner, Art Unit 2628