DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/25/2023 and 04/11/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. In claim 14, the substrate needs to be established before the membrane region and outer region. Also the positional relationship with the substrate also has to be established.
Claims 15-22 is rejected by virtue of their dependency on claim 14.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites “no dicing marks” however claim 14 refer to the pre-dicing product while “no dicing mark” would refer to the post-dicing product. It is unclear if applicant is claiming both the intermediate product and the final product.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14, 18, 19, 22 are rejected under 35 U.S.C. 102(a)(1) being anticipated by Udayakumar et al. [US 2013/0062996 A1], “Udayakumar”.
Regarding claim 14, Udayakumar disclose a membrane semiconductor component (Fig. 1H, 2E), comprising:
an outer region (region outside region 110: 112 and 114) and a membrane region (110), wherein at least part of a substrate (102) is disposed in the outer region,
wherein the substrate (102) is structured such that a first backside cavity (160) is configured in the membrane region (110),
wherein the first backside cavity (160) is free of the substrate (the region within the cavity (160) is free from substrate material), and wherein at least one active region (136) is disposed in the membrane region (110), and
the active region (136) includes at least one control electrode (152) and a target separation point (154) which includes a second backside cavity (162) in the outer region (112 and 114), wherein the second backside cavity is free of the substrate (region 162 does not have substrate material).
Regarding claim 18, Udayakumar discloses claim 14, Udayakumar discloses the target separation point (Fig. 1H) is configured such that it is free of metal (as shown).
Regarding claim 19, Udayakumar discloses claim 14, Udayakumar discloses the target separation point further includes one (Fig. 1H, 156) or more layers on or above the second backside cavity (154), wherein the one or more layers includes a material that is optically transparent or translucent (¶[0038] teaches resin material).
Regarding claim 22, Udayakumar discloses claim 14, Udayakumar disclose the second backside cavity (Fig. 1H, 162) is free of dicing marks (there is no dicing mark).
Claims 14 and 16 are rejected under 35 U.S.C. 102(a)(1) being anticipated by Iwamuro et al. [US 2009/0283776 A1], “Iwamuro”.
Regarding claim 14, Iwamuro discloses a membrane semiconductor component (Fig. 35 annotated below), comprising:
an outer region (OC) and a membrane region (MR), wherein at least part of a substrate (21) is disposed in the outer region (OC), wherein the substrate is structured such that a first backside cavity (1BC) is configured in the membrane region (MR), wherein the first backside cavity is free of the substrate (the cavity portion does not contain substrate material), and
wherein at least one active region (as shown) is disposed in the membrane region (MR), and the active region includes at least one control electrode (anode) and a target separation point (TSP) which includes a second backside cavity (2BC) in the outer region, wherein the second backside cavity is free of the substrate (the cavity portion does not contain substrate material). (The term “target separation point” is a relative term without any structure description).
Regarding claim 16, Iwamuro discloses claim 14, Iwamuro discloses a drain electrode (33) disposed in the first backside cavity and in the second backside cavity (as shown in Fig. 35) .
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. [US 2013/0062996 A1], “Udayakumar” and further in view of Romano et al. [US 2003/0062526 A1], “Romano”.
Regarding claim 15, Udayakumar discloses claim 1, Udayakumar discloses the second backside cavity is free of the filling material. Udayakumar does not disclose a filling material which is disposed in the first backside cavity, wherein the filling material is electrically and thermally conductive, and wherein the second backside cavity is free of the filling material.
However, Romano discloses a substrate a device (Fig. 13, 400) with a cavity (416) filled with copper (416) (¶[0072]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to fill the first cavity as taught in Romano in the device of Udayakumar such that a filling material which is disposed in the first backside cavity, wherein the filling material is electrically and thermally conductive, and wherein the second backside cavity is free of the filling material because such a modification using a high thermal conductivity material can aid in maximum heat dissipation (¶[0072] of Romano).
Regarding claim 17, Udayakumar discloses claim 1, Udayakumar discloses the second backside cavity is free of the drain electrode. Udayakumar does not disclose a drain electrode disposed in the first backside cavity, wherein the second backside cavity is free of the drain electrode.
However, Romano discloses a substrate a device (Fig. 13, 400) with a cavity (416) filled with copper (416) (¶[0072]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to fill the first cavity as taught in Romano in the device of Udayakumar such that a drain electrode disposed in the first backside cavity, wherein the second backside cavity is free of the drain electrode because such a modification using a high thermal conductivity material can aid in maximum heat dissipation (¶[0072] of Romano). The Examiner notes, copper is a conductive material and can be used as an electrode material. The term, “drain electrode” is a relative term especially since no device structure other than membrane has been establish.
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. [US 2013/0062996 A1], “Udayakumar” and further in view of Frasca et al. [US 2021/0351075 A1], “Frasca”.
Regarding claim 20, Udayakumar discloses claim 14, Udayakumar discloses the second backside cavity (Fig. 1H, 162) is a trench (as shown) or a blind hole with a side wall in the substrate (as shown in Fig. 1H). Udayakumar does not explicitly disclose the side wall has a ripple structure.
However, in an alternative embodiment, Udayakumar teaches the etching process can result in ripple shape (Fig. 2E, 262). Further, Frasca disclose the etching process can result in ripple/scallop shape (see Fig. 2) when etching into a silicon substrate.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have ripple/scallop shape after the etching process as taught in Frasca in the device of Udayakumar such that the side wall has a ripple structure because the ripple/scallop structure is a result of the etching process (¶[0014] of Frasca and Fig. 2).
Regarding claim 21, Udayakumar discloses claim 20, Udayakumar as modified discloses the ripple structure is a periodic ripple pattern (as shown in Fig. 2).
Claims 23, 24 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. [US 2013/0062996 A1], “Udayakumar”
Regarding claim 23, Udayakumar discloses a membrane semiconductor component structure (Fig. 1H), 100), comprising:
a first membrane semiconductor component (110) and a second membrane semiconductor component (as show in Fig. 1H portions of the second membrane semiconductor component), the first and second membrane semiconductor components having a common substrate (104);
wherein each of the first and the second membrane semiconductor component includes a membrane region (110) and an outer region (112/114) )disposed between the first membrane semiconductor component and the second membrane semiconductor component,
wherein the substrate (104) is structured such that a respective first backside cavity (160) is configured in the membrane region (110 ) of the first membrane semiconductor component and in the membrane region of the second membrane semiconductor component, wherein the first backside cavity is free of the substrate (as shown), and wherein at least one respective active region (136) is disposed in the membrane region of the first membrane semiconductor component and in the membrane region of the second membrane semiconductor component, and the active region includes at least one control electrode (152); and
wherein a target separation point (154) which includes a second backside cavity (162)
in the outer region between the first membrane semiconductor component and the second membrane semiconductor component, and wherein the second backside cavity is free of the substrate (as shown.
Udayakumar does not explicitly disclose the second membrane wherein the first and second membrane semiconductor components having a common substrate (104); wherein each of the first and the second membrane semiconductor component includes a membrane region (110) and an outer region (112/114) disposed between the first membrane semiconductor component and the second membrane semiconductor component, wherein the substrate (110) is structured such that a respective first backside cavity (160) is configured in the membrane region (110 ) of the first membrane semiconductor component and in the membrane region of the second membrane semiconductor component.
However, Udayakumar disclose this is an SOI wafer substrate (102) which include one or more of the components of circuits in the MEMS device (100) formed on the substrate. Portions of the second device is show in Fig. 1H (¶[0023] – ¶[0024]). Therefore the second membrane semiconductor component would have the same components as the first membrane semiconductor component.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to second membrane semiconductor component would have the same components as the first membrane semiconductor component, such that the second membrane wherein the first and second membrane semiconductor components having a common substrate (104); wherein each of the first and the second membrane semiconductor component includes a membrane region (110) and an outer region (112/114) disposed between the first membrane semiconductor component and the second membrane semiconductor component, wherein the substrate (110) is structured such that a respective first backside cavity (160) is configured in the membrane region (110 ) of the first membrane semiconductor component and in the membrane region of the second membrane semiconductor component since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding claim 24, Udayakumar disclose method for producing a membrane semiconductor component (Fig. 1A- 1I) having an outer region (112/114) and a membrane region (110), the method comprising the following steps:
forming a first membrane semiconductor component (110) and a second membrane semiconductor component ((as show in Fig. 1H portions of the second membrane semiconductor component): 110 duplicate) on a common substrate (104), wherein the first membrane semiconductor component includes a membrane region (110) and an outer region (112/114) disposed between the first membrane semiconductor component and the second membrane semiconductor component, wherein the substrate is structured such that a respective first backside cavity is configured in the membrane region of the first membrane semiconductor component, wherein the first backside cavity is free of the substrate, and wherein at least one respective active region (136) is configured in the membrane region of the first membrane semiconductor component (110), and the active region includes at least one control electrode (152);
forming a target separation point (154)which includes a second backside cavity (162) in the outer region (112/114) between the first membrane semiconductor component and the second membrane semiconductor component (as shown), wherein the second backside cavity is free of the substrate (as shown); and
separating the target separation point such that the first membrane semiconductor component and the second membrane semiconductor component are separated from one another (as shown in Fig. 1H and ¶[0043]).
Udayakumar does not explicitly show a drawing with a second membrane semiconductor component wherein and the second membrane semiconductor component includes a membrane region and an outer region disposed between the first membrane semiconductor component and the second membrane semiconductor component; the substrate is structured such that a respective first backside cavity is configured in the membrane region of the second membrane semiconductor component; at least one respective active region (136) is configured in the membrane region of the second membrane semiconductor component and the active region includes at least one control electrode.
However, Udayakumar disclose this is an SOI wafer substrate (102) which include one or more of the components of circuits in the MEMS device (100) formed on the substrate. Portions of the second device is show in Fig. 1H (¶[0023] – ¶[0024]). Therefore the second membrane semiconductor component would have the same components as the first membrane semiconductor component.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to second membrane semiconductor component would have the same components as the first membrane semiconductor component, such that a second membrane semiconductor component wherein and the second membrane semiconductor component includes a membrane region and an outer region disposed between the first membrane semiconductor component and the second membrane semiconductor component; the substrate is structured such that a respective first backside cavity is configured in the membrane region of the second membrane semiconductor component; at least one respective active region (136) is configured in the membrane region of the second membrane semiconductor component and the active region includes at least one control electrode since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. In re Harza, 124 USPQ 378. See MPEP 2144.04.
Regarding claim 27, Udayakumar disclose claim 24, Udayakumar disclose the separation of the target separation point is carried out by an etching process, including a wet chemical etching process or a dry chemical etching process, such that one or more layers on or above the second backside cavity are removed by the etching process (Fig. 1I and ¶[0043] teaches plasma etcher).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. [US 2013/0062996 A1], “Udayakumar” as applied to claim 24 and further in view of Weeks et al. [US 7,233,028 B2], “Weeks”.
Regarding claim 25, Udayakumar as modified disclose claim 24, Udayakumar discloses the singulation of the completed MEMS device (100) (¶[0043]). Udayakumar does not disclose the separation of the target separation point is carried out using a saw.
However, Weeks discloses multiple device structures may be formed on the same wafer of substrate material. A dicing operation, which utilizes a saw, may be used to separate individual devices from one another (Col. 11, lines 54 -58).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a saw as taught in Weeks in the method of Udayakumar such that the separation of the target separation point is carried out using a saw since the selection of a suitable alternative process and the selection of a known process based on its suitability for its intended use supports a determination of obviousness (See MPEP §2144.07) and using a saw is suitable alternative singulation method for separating/dicing individual devices (Col. 11, lines 54 -58 of Weeks).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Udayakumar et al. [US 2013/0062996 A1], “Udayakumar” as applied to claim 24 and further in view of Yoshino et al. [US 2020/0357698 A1], “Yoshino”.
Regarding claim 26, Udayakumar disclose claim 24, Udayakumar discloses the separation of the target separation point is carried out by breaking one or more layers of the target separation point, using a lateral expansion of the target separation point or using a pressure difference at the target separation point.
However, Yoshino disclose an alternative way to separate devices. Yoshino discloses a cleaving method, a blade (Fig. 5 and 6, 32) is pressed against the cleavage introduction part (30) on the rear surface (14) to apply a load to the substrate (10), thereby splitting the substrate (10).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use a pressure method as taught in Yoshino in the method of Udayakumar such that the separation of the target separation point is carried out by breaking one or more layers of the target separation point, using a lateral expansion of the target separation point or using a pressure difference at the target separation point since the selection of a suitable alternative process and the selection of a known process based on its suitability for its intended use supports a determination of obviousness (See MPEP §2144.07) and using a saw is suitable alternative singulation method for separating individual devices while protecting the integrity of the device (¶[0030] of Yoshino).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Masuko et al. [US 2016/0079120 A1] teaches a semiconductor device includes a semiconductor substrate that has a first surface and a second surface opposite to the first surface, and has a groove or trench extending from the first surface toward the second surface, a bottom of the groove being situated between the first surface and the second surface, and a gallium nitride-containing layer on the first surface of the semiconductor substrate having a trench tapering inwardly along a direction toward the first surface of the semiconductor substrate and connected to the groove.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/ Examiner, Art Unit 2897
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