DETAILED ACTION
This office action is responsive to communication filed on December 19, 2025. Claims 1-17 are pending in the application and have been examined by the Examiner.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 19, 2025 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 have been considered but are moot in view of the new grounds of rejection.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 8, 10, 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 2020/0195863) in view of Nagai (US 2010/0066882).
Consider claim 1, Shim et al. teaches:
A solid-state imaging apparatus (figures 1, 2 and 5F) comprising:
a semiconductor substrate (see figure 5F) that includes a first substrate (“third substrate”, paragraph 0085) and a second substrate (“second substrate”, paragraph 0085), wherein the second substrate is different from the first substrate (see figure 5F); and
a pixel array unit (pixel array, 110) including a plurality of unit pixels (112, see figures 2 and 5F, paragraphs 0023 and 0024), wherein
the semiconductor substrate further includes the pixel array unit (see figure 5F),
each of the plurality of unit pixels (see figure 5F) includes:
a first floating diffusion portion and a second floating diffusion portion that is different from the first floating diffusion portion (Shim et al. teaches, in the embodiment shown in figure 5F, a floating diffusion region (FD) connected between a second terminal of the first transistor (11, paragraph 0047) and a gate terminal of the third transistor (13, paragraph 0052). This floating diffusion region includes a first FD portion connected to the first transistor (11) in the first substrate (“third substrate”, see figure 5F), a second FD portion in a boundary part between the first substrate (“third substrate”) and the second substrate (“second substrate”, see figure 5F), and a third FD portion connected to the third transistor (13) in the second substrate (“second substrate”, see figure 5F).);
a first photoelectric conversion portion (photodiode, PD, paragraph 0044) configured to transfer a first charge to the first FD portion (see paragraphs 0047 and 0048), wherein the first FD portion is configured to retain the first charge (see paragraphs 0047 and 0048), and
a plurality of pixel transistors configured to drive a respective unit pixel of the plurality of unit pixels (see the transistors on the second and third substrates in figure 5F, paragraph 0085),
the first substrate (“third substrate”) includes each of the first photoelectric conversion portion (PD), the first FD portion (FD, see figure 5F), and a specific pixel transistor of the plurality of pixel transistors (e.g. the second transistor, 12), the specific pixel transistor (12) is directly connected to the first FD portion (FD, see figure 5F, paragraph 0085),
the second substrate (“second substrate”) includes at least one of the plurality of pixel transistors that is not directly connected to the first FD portion (FD, see figure 5F, “As shown in FIG. 5F, the third transistor 13 (SF, first source follow transistor), the fourth transistor 14 (PC, pre-charge transistor), the fifth transistor 15 (SMPL, sampling transistor), the sixth transistor 16 (CAL, calibration transistor), the seventh transistor 17 (SF, second source follow transistor), the eighth transistor 18 (SEL1, first selection transistor), the ninth transistor 19 (SEL2, second selection transistor), the first capacitor C1, and the second capacitor C2 of the pixel driving circuit may be on a second substrate (for example, an intermediate substrate).” paragraph 0085),
the specific pixel transistor (12) is different from the at least one of the plurality of pixel transistors (see figure 5F, paragraph 0085), and
the second FD portion is in a boundary part between the first substrate and the second substrate (This floating diffusion region includes a first FD portion connected to the first transistor (11) in the first substrate (“third substrate”, see figure 5F), a second FD portion in a boundary part between the first substrate (“third substrate”) and the second substrate (“second substrate”, see figure 5F), and a third FD portion connected to the third transistor (13) in the second substrate (“second substrate”, see figure 5F).).
Shim et al. teaches that first photoelectric conversion portion (PD) is connected to a ground (see figure 5F).
However, Shim et al. does not explicitly teach that the connection of the first photoelectric conversion portion to the ground is via a well contact.
Nagai similarly teaches a unit pixel (see figure 5) having a first photoelectric conversion portion (photoelectric conversion region, 103, paragraph 0009).
However, Nagai additionally teaches a well contact (well contact region, 117, contact section, 119, figure 5, paragraph 0011) configured to connect a first well to a ground, wherein the first well includes the first photoelectric conversion portion (“That is, the photoelectric conversion region 103 and the well contact region 117 of the photoelectric conversion element 102 are formed in the same active region. The well contact region 117 is electrically connected at a contact section 119 with a metal wiring 118, which extends in a vertical direction (longitudinal direction in FIG. 5), for supplying a constant potential, such as a ground potential (0V), to configure a well potential fixing section.” paragraph 0011, see figure 5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first photoelectric conversion portion and ground taught by Shim et al. be connected to one another via a well contact as taught by Nagai for the benefit of suppressing an increase of the area per unit pixel while controlling the shading of output signals due to a change in well potential (Nagai, paragraph 0015).
Consider claim 2, and as applied to claim 1 above, Shim et al. further teaches that the plurality of pixel transistors includes an amplifier transistor (the third transistor 13 (SF, first source follow transistor)) that is configured to output a signal corresponding to the charge retained in the FD portion (“The third transistor 13 (SF, first source follow transistor) may be operated by the voltage of the floating diffusion node FD to output the charges in the floating diffusion node FD to the fourth transistor 14 (PC, pre-charge transistor), the fifth transistor 15 (SMPL, sampling transistor, and the ninth transistor 19 (SEL2, second selection transistor).” paragraph 0052. See figure 5F.).
Consider claim 8, and as applied to claim 1 above, Shim et al. further teaches an intra-pixel capacitance (e.g. first capacitor, C1), wherein the respective unit pixel is configured to acquire a second charge that is different from the first charge, and the intra-pixel capacitance is configured to retain the second charge (see figure 5E, paragraphs 0085 and 0055).
Consider claim 10, and as applied to claim 8 above, Shim et al. further teaches that the second substrate (“second substrate”) includes the intra-pixel capacitance (C1) (“As shown in FIG. 5F, the third transistor 13 (SF, first source follow transistor), the fourth transistor 14 (PC, pre-charge transistor), the fifth transistor 15 (SMPL, sampling transistor), the sixth transistor 16 (CAL, calibration transistor), the seventh transistor 17 (SF, second source follow transistor), the eighth transistor 18 (SEL1, first selection transistor), the ninth transistor 19 (SEL2, second selection transistor), the first capacitor C1, and the second capacitor C2 of the pixel driving circuit may be on a second substrate (for example, an intermediate substrate).” paragraph 0085. See figure 5F.).
Consider claim 13, and as applied to claim 8 above, Shim et al. further teaches that the first substrate includes a first layer (“second substrate”) and a second layer (“third substrate”, see figure 5F), wherein the second layer (“third substrate”) is different from the first layer (“second substrate”, see figure 5F), the first layer (“second substrate”) includes the intra-pixel capacitance (C1, figure 5F, see paragraph 0084) the first layer is stacked on the second layer, and the second layer includes the first photoelectric conversion portion (The substrates are vertically stacked, as detailed n paragraph 0081. The second layer (“third substrate”) includes the first photoelectric conversion portion (PD), figure 5F.).
Consider claim 17, Shim et al. teaches:
An electronic apparatus (“The image processing system may be implemented as a portable electronic device. The portable electronic device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a mobile internet device (MID), a wearable computer, an internet of things (IoT) device, or an internet of everything (IoE) device.” paragraph 0042) comprising:
a solid-state imaging apparatus (figures 1, 2 and 5F) including:
a semiconductor substrate (see figure 5F) that includes a first substrate (“third substrate”, paragraph 0085) and a second substrate (“second substrate”, paragraph 0085), wherein the second substrate is different from the first substrate (see figure 5F); and
a pixel array unit (pixel array, 110) including a plurality of unit pixels (112, see figures 2 and 5F, paragraphs 0023 and 0024), wherein
the semiconductor substrate further includes the pixel array unit (see figure 5F),
each of the plurality of unit pixels (see figure 5F) includes:
a first floating diffusion portion and a second floating diffusion portion that is different from the first floating diffusion portion (Shim et al. teaches, in the embodiment shown in figure 5F, a floating diffusion region (FD) connected between a second terminal of the first transistor (11, paragraph 0047) and a gate terminal of the third transistor (13, paragraph 0052). This floating diffusion region includes a first FD portion connected to the first transistor (11) in the first substrate (“third substrate”, see figure 5F), a second FD portion in a boundary part between the first substrate (“third substrate”) and the second substrate (“second substrate”, see figure 5F), and a third FD portion connected to the third transistor (13) in the second substrate (“second substrate”, see figure 5F).);
a first photoelectric conversion portion (photodiode, PD, paragraph 0044) configured to transfer a first charge to the first FD portion (see paragraphs 0047 and 0048), wherein the first FD portion is configured to retain the first charge (see paragraphs 0047 and 0048), and
a plurality of pixel transistors configured to drive a respective unit pixel of the plurality of unit pixels (see the transistors on the second and third substrates in figure 5F, paragraph 0085),
the first substrate (“third substrate”) includes each of the first photoelectric conversion portion (PD), the first FD portion (FD, see figure 5F), and a specific pixel transistor of the plurality of pixel transistors (e.g. the second transistor, 12), the specific pixel transistor (12) is directly connected to the first FD portion (FD, see figure 5F, paragraph 0085),
the second substrate (“second substrate”) includes at least one of the plurality of pixel transistors that is not directly connected to the first FD portion (FD, see figure 5F, “As shown in FIG. 5F, the third transistor 13 (SF, first source follow transistor), the fourth transistor 14 (PC, pre-charge transistor), the fifth transistor 15 (SMPL, sampling transistor), the sixth transistor 16 (CAL, calibration transistor), the seventh transistor 17 (SF, second source follow transistor), the eighth transistor 18 (SEL1, first selection transistor), the ninth transistor 19 (SEL2, second selection transistor), the first capacitor C1, and the second capacitor C2 of the pixel driving circuit may be on a second substrate (for example, an intermediate substrate).” paragraph 0085),
the specific pixel transistor (12) is different from the at least one of the plurality of pixel transistors (see figure 5F, paragraph 0085), and
the second FD portion is in a boundary part between the first substrate and the second substrate (This floating diffusion region includes a first FD portion connected to the first transistor (11) in the first substrate (“third substrate”, see figure 5F), a second FD portion in a boundary part between the first substrate (“third substrate”) and the second substrate (“second substrate”, see figure 5F), and a third FD portion connected to the third transistor (13) in the second substrate (“second substrate”, see figure 5F).).
Shim et al. teaches that first photoelectric conversion portion (PD) is connected to a ground (see figure 5F).
However, Shim et al. does not explicitly teach that the connection of the first photoelectric conversion portion to the ground is via a well contact.
Nagai similarly teaches a unit pixel (see figure 5) having a first photoelectric conversion portion (photoelectric conversion region, 103, paragraph 0009).
However, Nagai additionally teaches a well contact (well contact region, 117, contact section, 119, figure 5, paragraph 0011) configured to connect a first well to a ground, wherein the first well includes the first photoelectric conversion portion (“That is, the photoelectric conversion region 103 and the well contact region 117 of the photoelectric conversion element 102 are formed in the same active region. The well contact region 117 is electrically connected at a contact section 119 with a metal wiring 118, which extends in a vertical direction (longitudinal direction in FIG. 5), for supplying a constant potential, such as a ground potential (0V), to configure a well potential fixing section.” paragraph 0011, see figure 5).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the first photoelectric conversion portion and ground taught by Shim et al. be connected to one another via a well contact as taught by Nagai for the benefit of suppressing an increase of the area per unit pixel while controlling the shading of output signals due to a change in well potential (Nagai, paragraph 0015).
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 2020/0195863) in view of Nagai (US 2010/0066882), as applied to claim 2 above, and further in view of Kobayashi (US 2021/0082979).
Consider claim 3, and as applied to claim 2 above, the combination of Shim et al. and Nagai does not explicitly teach a separating portion configured to electrically separate a well in which the photoelectric conversion portion is formed and a well in which the amplifier transistor is formed in the substrate from each other.
Kobayashi similarly teaches an image sensor (figure 1) having a pixel structure (figure 2) including a photoelectric conversion portion (photodiode, 201, paragraph 0038) and an amplifier transistor (amplification transistor, 207, paragraph 0039) formed in a substrate (“semiconductor substrate”, paragraph 0078), wherein a floating diffusion (floating diffusion portion, 206, paragraph 0038) forms a gate of the amplifier transistor (207, see figure 2).
However, Kobayashi additionally teaches a separating portion (DTI, figure 10, paragraph 0078) configured to electrically separate a well in which the photoelectric conversion portion (e.g. PDA or PDB) is formed (see figure 10) and a well in which the amplifier transistor (see FD, 206) is formed in the substrate (see figure 10) from each other (see figure 10, paragraph 0078).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion portion and amplifier transistor taught by the combination of Shim et al. and Nagai be separated in the manner taught by Kobayashi for the benefit of improving sensitivity (Kobayashi, paragraph 0079).
Consider claim 4, and as applied to claim 3 above, the combination of Shim et al. and Nagai does not explicitly teach that the separating portion includes an insulator.
Kobayashi teaches that the separating portion (DTI) is formed by an insulator (e.g. hafnium oxide, see paragraph 0052).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion portion and amplifier transistor taught by the combination of Shim et al. and Nagai be separated in the manner taught by Kobayashi for the benefit of improving sensitivity and suppressing color mixture (Kobayashi, paragraphs 0078 and 0079).
Consider claim 5, and as applied to claim 3 above, the combination of Shim et al. and Nagai does not explicitly teach that at least a part of the separating portion is a through DTI that penetrates the substrate.
Kobayashi teaches that at least a part of the separating portion (DTI) is a through DTI that penetrates the substrate (“As shown in FIG. 10, in the DTI, except for a portion between the pixels 10, the FD portion 206, and a portion where the gates of the transfer transistor 703 and the transfer transistor 704 do not pass, the DTI is preferably configured to penetrate the semiconductor substrate to suppress color mixture.” paragraph 0078, see figure 10).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion portion and amplifier transistor taught by the combination of Shim et al. and Nagai be separated in the manner taught by Kobayashi for the benefit of improving sensitivity and suppressing color mixture (Kobayashi, paragraphs 0078 and 0079).
Consider claim 6, and as applied to claim 3 above, the combination of Shim et al. and Nagai does not explicitly teach that at least a part of the separating portion is a front DTI that does not penetrate the substrate.
Kobayashi teaches that at least a part of the separating portion (DTI) is a front DTI that does not penetrate the substrate (“Further, since the charge transfer channel is formed as described above, it is preferable that the obliquely provided intra-pixel DTI does not penetrate to the surface opposite to the light incident surface.” paragraph 0081, see figure 10).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion portion and amplifier transistor taught by the combination of Shim et al. and Nagai be separated in the manner taught by Kobayashi for the benefit of improving sensitivity and suppressing color mixture (Kobayashi, paragraphs 0078 and 0079).
Claims 7, 9, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 2020/0195863) in view of Nagai (US 2010/0066882), as applied to claims 1 and 8 above, and further in view of Kawazu et al. (WO 2019/163511). US 2020/0412950 is assumed to be a valid English translation of WO 2019/163511, and portions cited herein refer thereto.
Consider claim 7, and as applied to claim 1 above, the combination of Shim et al. and Nagai does not explicitly teach that a switching transistor is among the plurality of pixel transistors and that is used for connecting the FD portion and another FD portion to each other.
Kawazu et al. similarly teaches a solid-state imaging apparatus (figure 1) having a pixel array (9) including multiple pixels (P1, paragraphs 0059 and 0061), wherein each pixel (P1, see figure 2) includes multiple pixel transistors (i.e. the transistors shown in figure 2, paragraphs 0062 and 0063).
However, Kawazu et al. additionally teaches that a switching transistor (FDG) is among the multiple pixel transistors (see figure 2, paragraph 0063) and that is used for connecting the FD portion (FD) and another FD portion (i.e. the floating diffusion portion between RST, FCG and FDG) to each other (see figure 2) is provided in the substrate (The imaging device (1) of figure 1, including the pixel circuitry of figure 2, may be implemented in one semiconductor substrate, paragraph 0117.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the multiple pixel transistors provided in the substrate taught by the combination of Shim et al. and Nagai include a switching transistor as taught by Kawazu et al. as this only involves combining prior art elements according to known methods to yield predictable results such as enabling the conversion gain of the pixel to be changed.
Consider claim 9, and as applied to claim 8 above, the combination of Shim et al. and Nagai does not explicitly teach that the intra-pixel capacitance is provided in the first substrate.
Kawazu et al. similarly teaches a solid-state imaging apparatus (figure 1) having a pixel array (9) including multiple pixels (P1, paragraphs 0059 and 0061), wherein each pixel (P1, see figure 2) includes an intra-pixel capacitance (capacity element, FC, paragraph 0063).
However, Kawazu et al. additionally teaches that the intra-pixel capacitance (FC) is provided in the first substrate (The imaging device (1) of figure 1, including the pixel circuitry of figure 2, may be implemented in one semiconductor substrate, paragraph 0117.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the intra-pixel capacitance taught by the combination of Shim et al. and Nagai include a capacitance provided in the first substrate as taught by Kawazu et al. as this only involves combining prior art elements according to known methods to yield predictable results such as enabling the conversion gain of the pixel to be changed.
Consider claim 11, and as applied to claim 8 above, the combination of Shim et al. and Nagai does not explicitly teach that the unit pixel further includes another photoelectric conversion portion smaller than the photoelectric conversion portion, and the other photoelectric conversion portion is provided in the first substrate.
Kawazu et al. similarly teaches a solid-state imaging apparatus (figure 1) having a pixel array (9) including multiple pixels (P1, paragraphs 0059 and 0061), wherein each pixel (P1, see figure 2) includes a photoelectric conversion portion (photodiode, PD1, paragraph 0064).
However, Kawazu et al. additionally teaches that the unit pixel further includes another photoelectric conversion portion (photodiode, PD2, paragraph 0063) smaller than the photoelectric conversion portion (“A light reception region where the photodiode PD2 is able to receive light is narrower than a light reception region where the photodiode PD1 is able to receive light.” paragraph 0066, see figure 3), and the other photoelectric conversion portion (PD2) is provided in the first substrate (The imaging device (1) of figure 1, including the pixel circuitry of figure 2, may be implemented in one semiconductor substrate, paragraph 0117.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the unit pixel taught by the combination of Shim et al. and Nagai include another photoelectric conversion portion in the first substrate as taught by Kawazu et al. as this only involves combining prior art elements according to known methods to yield predictable results such as enabling the conversion gain of the pixel to be changed.
Consider claim 12, and as applied to claim 11 above, the combination of Shim et al. and Nagai does not explicitly teach that the intra-pixel capacitance retains the charge transferred from the other photoelectric conversion portion.
Kawazu et al. similarly teaches a solid-state imaging apparatus (figure 1) having a pixel array (9) including multiple pixels (P1, paragraphs 0059 and 0061), wherein each pixel (P1, see figure 2) includes an intra-pixel capacitance (capacity element, FC, paragraph 0063).
However, Kawazu et al. additionally teaches that the intra-pixel capacitance (FC) retains a third charge transferred from the other photoelectric conversion portion (PD2, see paragraph 0161).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the intra-pixel capacitance taught by the combination of Shim et al. and Nagai include a capacitance that retains a third charge transferred from the other photoelectric conversion portion as taught by Kawazu et al. as this only involves combining prior art elements according to known methods to yield predictable results such as enabling the conversion gain of the pixel to be changed.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 2020/0195863) in view of Nagai (US 2010/0066882), as applied to claim 8 above, and further in view of Dai et al. (US 2022/0239858).
Consider claim 14, and as applied to claim 8 above, the combination of Shim et al. and Nagai does not explicitly teach that the intra-pixel capacitance is a 3D MIM capacitance.
Dai et al. similarly teaches a pixel circuit (figure 2A) having an intra-pixel capacitance (storage capacitor, 250, paragraph 0032), and further teaches that the intra-pixel capacitance (250) is a 3D MIM capacitance (“In the depicted example, each bit of the digital memory is implemented with a 1T1C (one-transistor, one-capacitor) 3D MIM (three dimensional metal-insulator-metal) memory cell. As such, the example depicted in FIG. 2A illustrates the N bit digital memory including storage capacitor CS 250-0 and output transistor 252-0 coupled to event switch 248-0, storage capacitor CS 250-1 and output transistor 252-1 coupled to event switch 248-1, storage capacitor CS 250-2 and output transistor 252-2 coupled to event switch 248-2, and storage capacitor CS 250-3 and output transistor 252-3 coupled to event switch 248-3 as shown.” paragraph 0032).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the intra-pixel capacitance taught by the combination of Shim et al. and Nagai be a 3D MIM capacitance as taught by Dai et al. as this only involves combining prior art elements according to known methods to yield predictable results such as enabling charge storage.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 2020/0195863) in view of Nagai (US 2010/0066882), as applied to claim 8 above, and further in view of Tzeng et al. (US 2013/0043560).
Consider claims 15 and 16, and as applied to claim 8 above, the combination of Shim et al. and Nagai does not explicitly teach that the intra-pixel capacitance is a concave MIM capacitance or a cylinder MIM capacitance.
Tzeng et al. similarly teaches a CMOS image sensor (paragraph 0001) having a capacitor (paragraph 0002, 1 of figure 1(a), paragraph 0016).
However, Tzeng et al. additionally teaches that the capacitor is a concave MIM capacitance or a cylinder MIM capacitance (“The MIM capacitor 1 may be of different shapes such as cylindrical shape, or a concave shape.” paragraph 0017).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the intra-pixel capacitance taught by the combination of Shim et al. and Nagai be a concave MIM capacitance or a cylinder MIM capacitance as taught by Tzeng et al. for the benefit of providing reduced electrode resistance (Tzeng et al., paragraph 0002).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637