DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because the abstract contains more than 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7, 9-10, 12-14, 18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN et al (US Pub 2021/0208433) in view of WANG et al (US Pub 2015/0362809).
With respect to claim 1, AHN discloses an array substrate, (fig. 1; display device 1) comprising: a substrate (fig. 8; substrate 110); wherein the substrate comprises a display area, and the display area comprises a plurality of sub-pixel areas distributed in an array (par 0085; discloses Pixel areas PA and switching element areas TA may be defined on the first base substrate 110; par 0042; discloses Pixels PX may be disposed in the display area DA. The pixels PX may be arranged in a matrix in a first direction DR1 and in a second direction DR2, which intersects the first direction DR1); scan lines on the substrate (fig. 1; discloses plurality of scan line HSL formed in the display area DA; see annotated fig. 2 below); wherein each of the scan lines extends in a row direction (fig. 1; discloses scan lines HSL extends in the horizontal direction); scan signal lines, (fig. 1; vertical scan lines VSL; see annotated fig. 2 below) wherein the scan signal lines extend along a column direction (par 0049; discloses vertical scan lines VSL, which also extend in the second direction DR2); each of the scan signal lines is disposed between two adjacent columns of the sub-pixel areas (fig. 1; discloses VSL lines are disposed in the panel in column direction between the columns of pixels PX); and one of the scan signal lines is only electrically connected to two scan lines of one scan line group (par 0049; discloses the vertical scan lines VSL and the horizontal scan lines HSL may be placed in contact and may be connected. That is, the vertical scan lines VSL and the horizontal scan lines HSL may be electrically connected); data line pairs on the substrate (fig. 1; discloses plurality of data line DL are formed in the panel; see annotated fig. 2 below); wherein each of the data line pairs comprises two data lines spaced apart and arranged in parallel; the data lines extend along the column direction; (fig. 2; discloses each pixel column comprises two data lines DL spaced apart and extending in column direction and are parallel to each other) sub-pixel columns are in one-to-one correspondence with the data line pairs; and in a sub-pixel column and a data line pair which are mutually corresponding, two data lines in the data line pair pass through a corresponding sub-pixel area along the column direction (par 0054; discloses the data lines DL may be disposed to overlap with the pixel columns PXC, on first and second sides, e.g., the right and left sides, in the first direction DR1, of each of the pixel columns PXC. For example, a first data line DL1 may be disposed on a second side, in the first direction DR1, of the first pixel column PXC1, and a second data line DL2 may be disposed on a first side, in the first direction DR1, of the first pixel column PXC1 ); a thin film transistor, wherein the thin film transistor is electrically connected to the scan line and electrically connected to the data line (par 0056; discloses In the pixels PX, which form the pixel rows PXR and the pixel columns PXC, switching elements, TR1 through TR12), which are connected to the horizontal scan lines HSL and the data lines DL, may be disposed. The switching elements TR1 through TR12 may be formed as thin-film transistors (TFTs).); a pixel electrode; wherein the pixel electrode is in the sub-pixel area and electrically connected to the thin film transistor (par 0085; discloses the pixel areas PA may be defined as regions where pixel electrodes PE are disposed, and the switching element areas TA may be defined as regions where switching elements TR are disposed. Par 0102; discloses the first semiconductor pattern 151 may form the channel of a TFT that provides a first data signal D1 to the first pixel electrode PE1. The second semiconductor pattern 152 may form the channel of a TFT that provides a second data signal D2 to the second pixel electrode PE2. The third semiconductor pattern 153 may form the channel of a TFT that provides a third data signal D3 to the third pixel electrode PE3), and an orthographic projection of the pixel electrode on the base substrate overlaps with orthographic projections of two corresponding data lines on the base substrate (par 0112; discloses The first, second, third, fourth, fifth, and sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6 may generally extend in the second direction DR2. The first and fourth data lines DL1 and DL4 may partially overlap with the first pixel electrode PE1. The second and fifth data lines DL2 and DL5 may partially overlap with the second pixel electrode PE2. The third and sixth data lines DL3 and DL6 may partially overlap with the third pixel electrode PE3); and a light shielding strip, which is disposed between every two adjacent sub-pixel areas along the row direction (fig. 5; elements 1274, 1275, 1276, 1277; par 0093; discloses the extended portions 1274, 1275, 1276, and 1277 of the sustain line 127 may serve as light-shielding patterns for blocking the transmission of light at first and second sides, in the first direction DR1, of the pixel electrodes PE);
AHN doesn’t expressly disclose each of the scan lines is disposed between two adjacent rows of the sub-pixel areas and two adjacent scan lines form a scan line group; and in any two scan line groups, the scan lines in one of the any two scan line groups and the scan lines in other of the any two scan line groups are different from each other;
In the same field of endeavor, WANG discloses a display device comprising array substrate (see abstract); WANG discloses each of the scan lines is disposed between two adjacent rows of the sub-pixel areas and two adjacent scan lines form a scan line group (fig. 1; discloses each of the gate lines are disposed between the adjacent rows of subpixels and are formed in groups of two); and in any two scan line groups, the scan lines in one of the any two scan line groups and the scan lines in other of the any two scan line groups are different from each other (fig. 1; discloses each gate line in the group corresponds to a particular row of subpixels and are different from one another);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by AHN to incorporate the teachings of WANG to dispose the scan lines in groups between the adjacent rows of pixels in order to improve aperture ratio of the pixels in the display device.
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With respect to claim 2, AHN as modified by WANG discloses wherein an organic insulating layer is disposed between the data lines and the pixel electrode for isolation (AHN; fig. 9; discloses planarization layer 160 of formed between the data line DL and the pixel electrodes PE; par 0124; discloses the planarization layer 160 may have excellent planarization characteristics and may include an organic material with photosensitivity. The planarization layer 160 may fill any height differences generated by the underlying structure, for example, the color filters CF, and may planarize the surface on which the pixel electrodes PE are to be disposed; see annotated fig. 9 below).
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With respect to claim 3, AHN as modified by WANG discloses further comprising: a common electrode corresponding to the pixel electrode (fig. 9; common electrode CE); and a common electrode line electrically connected to the common electrode (par 0135; discloses the shield voltage may be substantially the same as the common voltage Vcom, which is applied to the common electrode CE, or may be a DC voltage).
With respect to claim 7, AHN as modified by WANG discloses wherein the thin film transistor comprises a gate, a gate insulating layer, an active layer, an insulating layer, and source and drain electrodes electrically connected to the active layer which are stacked in sequence (par 0100; discloses The gate insulating layer 130 may be disposed on the gate conductive layer 120; par 0102; discloses The semiconductor layer 150 may be disposed on the gate insulating layer 130; fig. 8; discloses source electrode SE and drain electrode DE connected to semiconductor layer 150); wherein the gate and the scan lines are prepared on a same layer; (AHN; par 0086; discloses the gate conductive layer 120 is disposed on the first base substrate 110. The gate conductive layer 120 may include the horizontal scan lines HSL and the gate electrodes GE) and the source and drain electrodes are disposed on a same layer as the data lines (AHN; par 0111; discloses the data conductive layer 170 may include the first, second, third, fourth, fifth, and sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6, the first, second, and third source electrodes SE1, SE2, and SE3, the first, second, and third drain electrodes DE1, DE2, and DE3, and the vertical scan lines VSL.).
With respect to claim 9, AHN as modified by WANG wherein the scan signal lines and the data lines are prepared on a same layer (AHN; fig. 6; discloses data line DL and vertical signal lines VSL are formed on the same layer; par 0111; discloses The data conductive layer 170 may include the first, second, third, fourth, fifth, and sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6, the first, second, and third source electrodes SE1, SE2, and SE3, the first, second, and third drain electrodes DE1, DE2, and DE3, and the vertical scan lines VSL).
With respect to claim 10, AHN as modified by WANG discloses wherein the pixel electrode comprises a plurality of electrode strips arranged at intervals and connected in sequence (AHN; fig. 7; structure of the pixel electrode PE; par 0129; discloses the first pixel electrode PE1 may include a stem portion 191a, branch portions 191b, which extend outwardly from the stem portion 191a and are spaced apart from one another by slits 191c,).
With respect to claim 12, AHN discloses a display panel, comprising an array substrate, (fig. 1; display device 1) wherein the array substrate comprising: a substrate (fig. 8; substrate 110); wherein the substrate comprises a display area, and the display area comprises a plurality of sub-pixel areas distributed in an array (par 0085; discloses Pixel areas PA and switching element areas TA may be defined on the first base substrate 110; par 0042; discloses Pixels PX may be disposed in the display area DA. The pixels PX may be arranged in a matrix in a first direction DR1 and in a second direction DR2, which intersects the first direction DR1); scan lines on the substrate (fig. 1; discloses plurality of scan line HSL formed in the display area DA; see annotated fig. 2 below); wherein each of the scan lines extends in a row direction (fig. 1; discloses scan lines HSL extends in the horizontal direction); scan signal lines, (fig. 1; vertical scan lines VSL; see annotated fig. 2 below) wherein the scan signal lines extend along a column direction (par 0049; discloses vertical scan lines VSL, which also extend in the second direction DR2); each of the scan signal lines is disposed between two adjacent columns of the sub-pixel areas (fig. 1; discloses VSL lines are disposed in the panel in column direction between the columns of pixels PX); and one of the scan signal lines is only electrically connected to two scan lines of one scan line group (par 0049; discloses the vertical scan lines VSL and the horizontal scan lines HSL may be placed in contact and may be connected. That is, the vertical scan lines VSL and the horizontal scan lines HSL may be electrically connected); data line pairs on the substrate (fig. 1; discloses plurality of data line DL are formed in the panel; see annotated fig. 2 below); wherein each of the data line pairs comprises two data lines spaced apart and arranged in parallel; the data lines extend along the column direction; (fig. 2; discloses each pixel column comprises two data lines DL spaced apart and extending in column direction and are parallel to each other) sub-pixel columns are in one-to-one correspondence with the data line pairs; and in a sub-pixel column and a data line pair which are mutually corresponding, two data lines in the data line pair pass through a corresponding sub-pixel area along the column direction (par 0054; discloses the data lines DL may be disposed to overlap with the pixel columns PXC, on first and second sides, e.g., the right and left sides, in the first direction DR1, of each of the pixel columns PXC. For example, a first data line DL1 may be disposed on a second side, in the first direction DR1, of the first pixel column PXC1, and a second data line DL2 may be disposed on a first side, in the first direction DR1, of the first pixel column PXC1 ); a thin film transistor, wherein the thin film transistor is electrically connected to the scan line and electrically connected to the data line (par 0056; discloses In the pixels PX, which form the pixel rows PXR and the pixel columns PXC, switching elements, TR1 through TR12), which are connected to the horizontal scan lines HSL and the data lines DL, may be disposed. The switching elements TR1 through TR12 may be formed as thin-film transistors (TFTs).); a pixel electrode; wherein the pixel electrode is in the sub-pixel area and electrically connected to the thin film transistor (par 0085; discloses the pixel areas PA may be defined as regions where pixel electrodes PE are disposed, and the switching element areas TA may be defined as regions where switching elements TR are disposed. Par 0102; discloses the first semiconductor pattern 151 may form the channel of a TFT that provides a first data signal D1 to the first pixel electrode PE1. The second semiconductor pattern 152 may form the channel of a TFT that provides a second data signal D2 to the second pixel electrode PE2. The third semiconductor pattern 153 may form the channel of a TFT that provides a third data signal D3 to the third pixel electrode PE3), and an orthographic projection of the pixel electrode on the base substrate overlaps with orthographic projections of two corresponding data lines on the base substrate (par 0112; discloses The first, second, third, fourth, fifth, and sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6 may generally extend in the second direction DR2. The first and fourth data lines DL1 and DL4 may partially overlap with the first pixel electrode PE1. The second and fifth data lines DL2 and DL5 may partially overlap with the second pixel electrode PE2. The third and sixth data lines DL3 and DL6 may partially overlap with the third pixel electrode PE3); and a light shielding strip, which is disposed between every two adjacent sub-pixel areas along the row direction (fig. 5; elements 1274, 1275, 1276, 1277; par 0093; discloses the extended portions 1274, 1275, 1276, and 1277 of the sustain line 127 may serve as light-shielding patterns for blocking the transmission of light at first and second sides, in the first direction DR1, of the pixel electrodes PE);
AHN doesn’t expressly disclose each of the scan lines is disposed between two adjacent rows of the sub-pixel areas and two adjacent scan lines form a scan line group; and in any two scan line groups, the scan lines in one of the any two scan line groups and the scan lines in other of the any two scan line groups are different from each other;
In the same field of endeavor, WANG discloses a display device comprising array substrate (see abstract); WANG discloses each of the scan lines is disposed between two adjacent rows of the sub-pixel areas and two adjacent scan lines form a scan line group (fig. 1; discloses each of the gate lines are disposed between the adjacent rows of subpixels and are formed in groups of two); and in any two scan line groups, the scan lines in one of the any two scan line groups and the scan lines in other of the any two scan line groups are different from each other (fig. 1; discloses each gate line in the group corresponds to a particular row of subpixels and are different from one another);
Therefore, it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by AHN to incorporate the teachings of WANG to dispose the scan lines in groups between the adjacent rows of pixels in order to improve aperture ratio of the pixels in the display device.
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With respect to claim 13, AHN as modified by WANG discloses wherein an organic insulating layer is disposed between the data lines and the pixel electrode for isolation (AHN; fig. 9; discloses planarization layer 160 of formed between the data line DL and the pixel electrodes PE; par 0124; discloses the planarization layer 160 may have excellent planarization characteristics and may include an organic material with photosensitivity. The planarization layer 160 may fill any height differences generated by the underlying structure, for example, the color filters CF, and may planarize the surface on which the pixel electrodes PE are to be disposed; see annotated fig. below).
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With respect to claim 14, AHN as modified by WANG discloses further comprising: a common electrode corresponding to the pixel electrode (fig. 9; common electrode CE); and a common electrode line electrically connected to the common electrode (par 0135; discloses the shield voltage may be substantially the same as the common voltage Vcom, which is applied to the common electrode CE, or may be a DC voltage).
With respect to claim 18, AHN as modified by WANG discloses wherein the thin film transistor comprises a gate, a gate insulating layer, an active layer, an insulating layer, and source and drain electrodes electrically connected to the active layer which are stacked in sequence (par 0100; discloses The gate insulating layer 130 may be disposed on the gate conductive layer 120; par 0102; discloses The semiconductor layer 150 may be disposed on the gate insulating layer 130; fig. 8; discloses source electrode SE and drain electrode DE connected to semiconductor layer 150); wherein the gate and the scan lines are prepared on a same layer; (AHN; par 0086; discloses the gate conductive layer 120 is disposed on the first base substrate 110. The gate conductive layer 120 may include the horizontal scan lines HSL and the gate electrodes GE) and the source and drain electrodes are disposed on a same layer as the data lines (AHN; par 0111; discloses the data conductive layer 170 may include the first, second, third, fourth, fifth, and sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6, the first, second, and third source electrodes SE1, SE2, and SE3, the first, second, and third drain electrodes DE1, DE2, and DE3, and the vertical scan lines VSL.).
With respect to claim 20, AHN as modified by WANG wherein the scan signal lines and the data lines are prepared on a same layer (AHN; fig. 6; discloses data line DL and vertical signal lines VSL are formed on the same layer; par 0111; discloses The data conductive layer 170 may include the first, second, third, fourth, fifth, and sixth data lines DL1, DL2, DL3, DL4, DL5, and DL6, the first, second, and third source electrodes SE1, SE2, and SE3, the first, second, and third drain electrodes DE1, DE2, and DE3, and the vertical scan lines VSL).
Claim(s) 4-6, 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN et al (US Pub 2021/0208433) in view of WANG et al (US Pub 2015/0362809) and CHUNG et al (US Pub 2021/0149511).
With respect to claim 4, AHN as modified by WANG discloses wherein the common electrode is on a side away from the base substrate, of the data lines; (AHN; fig. 9; discloses common electrode CE is formed away from substrate 110) the pixel electrode is on a side away from the data lines, of the common electrode (AHN; fig. 9; discloses pixel electrode PE are disposed away from the data line DL); the organic insulating layer is between the data lines and the common electrode (AHN; fig. 9; discloses planarization layer 160 is disposed between the data lines DL and the common electrode CE);
AHN as modified by WANG don’t expressly disclose a passivation layer is disposed between the common electrode and the pixel electrode for isolation;
In the same field of endeavor, CHUNG discloses a display device where a passivation layer is disposed between the common electrode and the pixel electrode for isolation (par 0019; discloses a third passivation layer is provided between the pixel electrode and the common electrode);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by AHN as modified by WANG to incorporate the teachings of CHUNG to dispose a passivation layer between the pixel electrode and the common electrode in order to separate the pixel electrode from common electrode such that capacitance between pixel electrode and common electrode is created.
With respect to claim 5, AHN as modified by WANG and CHUNG discloses wherein the light shielding strip is a metal light shielding strip, and the metal light shielding strip is electrically connected to the common electrode line (AHN; par 0089; discloses The gate conductive layer 120 may further include a sustain lines 127. A sustain voltage may be applied to the sustain line 127. The sustain voltage may be substantially the same as the common voltage Vcom, which is applied to a common electrode CE, and may be a direct current (DC) voltage; par 0093; discloses the extended portions 1274, 1275, 1276, and 1277 of the sustain line 127 may serve as light-shielding patterns for blocking the transmission of light at first and second sides, in the first direction DR1, of the pixel electrodes PE.).
With respect to claim 6, AHN as modified by WANG and CHUNG discloses wherein the light shielding strip and the scan lines are prepared on a same layer (AHN; fig. 5; discloses gate lines HSL and sustain lines 127 comprising the extended portions 1274, 1275, 1276, 1277 are formed in the same layer; par 0086; discloses the gate conductive layer 120 is disposed on the first base substrate 110. The gate conductive layer 120 may include the horizontal scan lines HSL and the gate electrodes GE; par 0089; discloses the gate conductive layer 120 may further include a sustain lines 127; i.e. gate lines HSL and sustain lines 127 are formed on the same layer).
With respect to claim 15, AHN as modified by WANG discloses wherein the common electrode is on a side away from the base substrate, of the data lines; (AHN; fig. 9; discloses common electrode CE is formed away from substrate 110) the pixel electrode is on a side away from the data lines, of the common electrode (AHN; fig. 9; discloses pixel electrode PE are disposed away from the data line DL); the organic insulating layer is between the data lines and the common electrode (AHN; fig. 9; discloses planarization layer 160 is disposed between the data lines DL and the common electrode CE);
AHN as modified by WANG don’t expressly disclose a passivation layer is disposed between the common electrode and the pixel electrode for isolation;
In the same field of endeavor, CHUNG discloses a display device where a passivation layer is disposed between the common electrode and the pixel electrode for isolation (par 0019; discloses a third passivation layer is provided between the pixel electrode and the common electrode);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by AHN as modified by WANG to incorporate the teachings of CHUNG to dispose a passivation layer between the pixel electrode and the common electrode in order to separate the pixel electrode from common electrode such that capacitance between pixel electrode and common electrode is created.
With respect to claim 16, AHN as modified by WANG and CHUNG discloses wherein the light shielding strip is a metal light shielding strip, and the metal light shielding strip is electrically connected to the common electrode line (AHN; par 0089; discloses The gate conductive layer 120 may further include a sustain lines 127. A sustain voltage may be applied to the sustain line 127. The sustain voltage may be substantially the same as the common voltage Vcom, which is applied to a common electrode CE, and may be a direct current (DC) voltage; par 0093; discloses the extended portions 1274, 1275, 1276, and 1277 of the sustain line 127 may serve as light-shielding patterns for blocking the transmission of light at first and second sides, in the first direction DR1, of the pixel electrodes PE.).
With respect to claim 17, AHN as modified by WANG and CHUNG discloses wherein the light shielding strip and the scan lines are prepared on a same layer (AHN; fig. 5; discloses gate lines HSL and sustain lines 127 comprising the extended portions 1274, 1275, 1276, 1277 are formed in the same layer; par 0086; discloses the gate conductive layer 120 is disposed on the first base substrate 110. The gate conductive layer 120 may include the horizontal scan lines HSL and the gate electrodes GE; par 0089; discloses the gate conductive layer 120 may further include a sustain lines 127; i.e. gate lines HSL and sustain lines 127 are formed on the same layer).
Claim(s) 8, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN et al (US Pub 2021/0208433) in view of WANG et al (US Pub 2015/0362809) and NAKAYASU (US Pub 2012/0119979).
With respect to claim 8, AHN as modified by WANG discloses wherein, in the scan signal lines, a part of the scan signal lines are non-electrically connected to the scan lines (fig. 2; discloses scan signal line VSL1 formed on the same array as gate lines HSl3 and HSL4 but is not electrically connected to them)
AHN as modified by WANG don’t expressly disclose a part of the scan signal lines are electrically connected to the common electrode lines;
In the same field of endeavor, NAKAYASU discloses display device where a part of the scan signal lines are electrically connected to the common electrode lines (par 0029; discloses each of the gate lines GL intersects the ground lines VGL on the left side and the right side of the display region in plan view. Further, bidirectional diodes BD are respectively provided correspondingly to the intersecting portions. The bidirectional diode BD is provided so as to connect the gate line GL and the ground line VGL forming the corresponding intersecting portion.);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by AHN as modified by WANG to incorporate the teachings of NAKAYASU to electrically connect part of the scan signal lines to the common electrode lines in order to prevent any electrostatic discharge damage in the display device.
With respect to claim 19, AHN as modified by WANG discloses wherein, in the scan signal lines, a part of the scan signal lines are non-electrically connected to the scan lines (fig. 2; discloses scan signal line VSL1 formed on the same array as gate lines HSl3 and HSL4 but is not electrically connected to them)
AHN as modified by WANG don’t expressly disclose a part of the scan signal lines are electrically connected to the common electrode lines;
In the same field of endeavor, NAKAYASU discloses display device where a part of the scan signal lines are electrically connected to the common electrode lines (par 0029; discloses each of the gate lines GL intersects the ground lines VGL on the left side and the right side of the display region in plan view. Further, bidirectional diodes BD are respectively provided correspondingly to the intersecting portions. The bidirectional diode BD is provided so as to connect the gate line GL and the ground line VGL forming the corresponding intersecting portion.);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by AHN as modified by WANG to incorporate the teachings of NAKAYASU to electrically connect part of the scan signal lines to the common electrode lines in order to prevent any electrostatic discharge damage in the display device.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over AHN et al (US Pub 2021/0208433) in view of WANG et al (US Pub 2015/0362809) and KIM et al (US Pub 2021/0026210).
With respect to claim 11, AHN as modified by WANG don’t expressly disclose further comprising a light shielding layer disposed along the row direction and corresponding to the scan lines for shielding light;
In the same field of endeavor, Kim discloses a display device (see abstract); Kim discloses a light shielding layer disposed along the row direction and corresponding to the scan lines for shielding light (par 0095; discloses A light blocking member 220, for example, a black matrix, may be disposed on the second substrate 210 to prevent light leakage. The light blocking member 220 may include a portion that extends in the first direction x between the first subpixel electrode 191a and the second subpixel electrode 191b and overlaps the first and second transistors Qa and Qb. The light blocking member 220 may be disposed on the first display panel 100; fig. 2; discloses light blocking member 220 overlaps the gate lines 121);
Therefore it would have been obvious to one having ordinary skill in the art to modify the invention disclosed by AHN as modified by WANG to incorporate the teachings of KIM to include a light blocking member that overlaps the gate lines in order to prevent any light leakage from occurring around the pixel areas.
Conclusion
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/SUJIT SHAH/ Examiner, Art Unit 2624