CTNF 18/557,573 CTNF 89258 DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. There are a total of 20 claims and claims 1-20 are pending. Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/26/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) which papers have been placed of record in the file. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claims 1-13 and 19-20 are r ejected under 35 U.S.C. 103 as being unpatentable over H asegawa et al. ( US 2019/0353760) in view of Hostetler et al.( US 2022/0107400 A1). R egarding claim 1, Hasegawa discloses a photodetector comprising([abstract and para 006-007]- a single-photon avalanche diode (SPAD) disposed on a first semiconductor substrate, and each generating a first logic signal (S35) depending on detection timing in the single-photon avalanche diode (SPAD)): a first substrate having a first surface serving as a light receiving surface and a second surface opposed to the first surface, the first substrate having a plurality of pixels disposed in an arrayed manner, the first substrate including a light receiving section provided for each of the pixels, the light receiving section generating, through photoelectric conversion, electric charge corresponding to an amount of received ligh t([para 009;0011]- a light-emitting section, a mirror, a plurality of pixels, and a time measurement section. The light-emitting section emits light. The mirror reflects reflective light corresponding to the light. The plurality of pixels is provided side by side in a first direction, and each includes a single-photon avalanche diode that is disposed on a first semiconductor substrate and detects the reflective light reflected by the mirror, and each generates a first logic signal depending on detection timing in the single-photon avalanche diode. The time measurement section is disposed on a second semiconductor substrate attached to the first semiconductor substrate and measures the detection timing in each of the plurality of pixels); )); a first electrode provided at the first surface of the first substrate and electrically coupled to the light receiving section ([see in Fig. 5]- The semiconductor substrate 110 is provided with the light receiving elements 31 in the pixel array 21, and a surface on which the light receiving elements 31 are disposed serves as a light receiving surface S of the time measurement device 20. On the semiconductor substrate 120, in a region 121 corresponding to a region in which the light receiving elements 31 are disposed on the semiconductor substrate 110, the resistor elements 32 and circuits in the pixel array 21 are disposed. Further, in a region 122, the selection signal generator 22, the waveform shaping section 23, and the time measurement section 24 are disposed. The semiconductor substrate 110 and the semiconductor substrate 120 are electrically coupled to each other using, for example, Cu—Cu bonding). However, Hasegawa does not explicitly disclose a second substrate disposed on a side of the second surface of the first substrate, the second substrate having a third surface directly opposed to the second surface and also having a fourth surface opposed to the third surface, the second substrate having a band gap wider than a band gap of the first substrate, the second substrate including a multiplication section provided for each of the pixels, the multiplication section applying avalanche multiplication to the electric charge generated at the light receiving section; a first electrode provided at the first surface of the first substrate and electrically coupled to the light receiving section; and a second electrode provided at the fourth surf ace of the second substrate and electrically coupled to the multiplication section. In an analogous art, Hostetler discloses a second substrate disposed on a side of the second surface of the first substrate, the second substrate having a third surface directly opposed to the second surface and also having a fourth surface opposed to the third surface, the second substrate having a band gap wider than a band gap of the first substrate ([see in Fig. 3-5 and para 0047]- a photodetector having a surface region of p-type semiconductor material 512 is positioned at the bottom of the photodetector to serve as an anode, and a region of n-type semiconductor material 513 is positioned between the p-type semiconductor 512 and the N+ substrate 511 to provide a p-n junction that is held under reverse bias. The current is sourced by the surface region of p-type semiconductor material 452 of the photodetector via a conductive contact trace 517 that leads from the region of p-type semiconductor material 512 to the ROIC 533. The entire photodetector and device side of the substrate 511 surface are coated with an anti-reflective dielectric coating 519 that covers all areas except where trace 517 meets makes contact to p-region 512 as described above for FIG. 3 for passivation purposes. Mask material 520 may be coated on the substrate 511 to block the light-receiving region of masked pixel 501b. Mask 520 can be the backside metal and also be the cathode. Because no light reaches the active region, the only signal that will be emitted via the conductive trace of the masked pixel 501b will be that resulting from intrinsic noise such as DCR and crosstalk as described above. As described in FIG. 3, the avalanche event induces luminescence 515 at the higher band gap energy of the drift layer material (for example, Eg=1.33 eV for indium phosphide (InP) for the near IR regime)) , the second substrate including a multiplication section provided for each of the pixels, the multiplication section applying avalanche multiplication to the electric charge generated at the light receiving section ([para 0041-0042]- the photon generates an exciton, 316a (i.e. electron-hole pair). The generated carriers are accelerated in opposite directions by the applied electric field, where one carrier 316a (in this case a hole) drifts to the multiplication region 313a. Once the carrier reaches the multiplication region, the carrier induces an electron avalanche through impact ionization and amplification occurs to create a measurable current as measured through metal trace 317a that leads from the surface region of p-type semiconductor material 312a to a readout integrated circuit (ROIC) (not shown; and a second electrode provided at the fourth surf ace of the second substrate and electrically coupled to the multiplication section). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the technique of Hostetler to the modified system of Hasegawa a method to detect, and optionally to compensate, for the intrinsic noise in an isolated pixel in real time. In this way, the sensitivity of the system can be improved without further increasing the bias, or by increasing the signal-to-noise ratio at higher bias, thereby improving performance [Hostetler ;paragraph 0037]. Regarding claim 2, Hasegawa discloses wherein the first electrode is provided between the plurality of pixels, and is provided at the first surface of the first substrate in a lattice form([para 0205]-lattice pattern). Regarding claim 3, Hasegawa discloses The photodetector according to claim 1, wherein a negative voltage is applied to the first electrode([see in Fig. 7]- in FIG. 7, when light enters the light receiving element 31 in timing t19, electron-hole pairs are generated in the light receiving element 31. Subsequently, the generated electrons and holes are accelerated by an electric field, and the electron-hole pairs are formed one after another through impact ionization. In such a manner that the light receiving element 31 performs so-called avalanche amplification, a voltage of the signal S31 drops once from the bias voltage Vbias. Subsequently, the voltage of the signal S31 rises gradually to return to the bias voltage Vbias finally). Regarding claim 4, Hasegawa discloses further comprising an impurity diffusion layer that is provided at the first surface of the first substrate and contains a first conduction-type impurity, wherein the first electrode is provided at the first surface of the first substrate with the impurity diffusion layer being interposed between the first electrode and the first surface([para 0201-0202]- N-type semiconductor layer 201 is a semiconductor layer that includes, for example, silicon (Si), having a high impurity concentration and a conductivity type of an N type. The P-type semiconductor layer 202 is a semiconductor layer having a high impurity concentration and a conductivity type of a P type). Regarding claim 5, Hasegawa discloses The photodetector according to claim 4, wherein the impurity diffusion layer is provided over all of the first surface([para 0201- 0202]- N-type semiconductor layer 201 is a semiconductor layer that includes, for example, silicon (Si), having a high impurity concentration and a conductivity type of an N type. The P-type semiconductor layer 202 is a semiconductor layer having a high impurity concentration and a conductivity type of a P type. The N-type semiconductor layer 201 and the P-type semiconductor layer 202 configure a PN junction in an interfacial surface). Regarding claim 6, Hostetler discloses wherein a semiconductor layer having a band gap that falls between the band gap of the first substrate and the band gap of the second substrate is further provided between the first substrate and the second substrate([see in Fig. 3-5 and para 0047]- a photodetector having a surface region of p-type semiconductor material 512 is positioned at the bottom of the photodetector to serve as an anode, and a region of n-type semiconductor material 513 is positioned between the p-type semiconductor 512 and the N+ substrate 511 to provide a p-n junction that is held under reverse bias. The current is sourced by the surface region of p-type semiconductor material 452 of the photodetector via a conductive contact trace 517 that leads from the region of p-type semiconductor material 512 to the ROIC 533. The entire photodetector and device side of the substrate 511 surface are coated with an anti-reflective dielectric coating 519 that covers all areas except where trace 517 meets makes contact to p-region 512 as described above for FIG. 3 for passivation purposes. Mask material 520 may be coated on the substrate 511 to block the light-receiving region of masked pixel 501b. Mask 520 can be the backside metal and also be the cathode. Because no light reaches the active region, the only signal that will be emitted via the conductive trace of the masked pixel 501b will be that resulting from intrinsic noise such as DCR and crosstalk as described above. As described in FIG. 3, the avalanche event induces luminescence 515 at the higher band gap energy of the drift layer material (for example, Eg=1.33 eV for indium phosphide (InP) for the near IR regime)). Regarding claim 7, Hasegawa discloses wherein the multiplication section includes a first conduction-type region provided on a side of the third surface, and a second conduction-type region provided on a side of the fourth surface([para 0041-0042]- the photon generates an exciton, 316a (i.e. electron-hole pair). The generated carriers are accelerated in opposite directions by the applied electric field, where one carrier 316a (in this case a hole) drifts to the multiplication region 313a. Once the carrier reaches the multiplication region, the carrier induces an electron avalanche through impact ionization and amplification occurs to create a measurable current as measured through metal trace 317a that leads from the surface region of p-type semiconductor material 312a to a readout integrated circuit (ROIC) (not shown; and a second electrode provided at the fourth surf ace of the second substrate and electrically coupled to the multiplication section). Regarding claim 8, Hasegawa discloses wherein the multiplication section further includes a first first-conduction type layer provided at or around an interface of the third surface and having an impurity concentration relatively lower than that of the first conduction-type region([para 0201]- The P-type semiconductor layer 202 is disposed under the N-type semiconductor layer 201. The N-type semiconductor layer 201 and the P-type semiconductor layer 202 are provided inside the well 203. The P-type semiconductor layer 202 has a multiplier region that performs avalanche multiplication of carriers generated by entrance of light. Preferably, the P-type semiconductor layer 202 is depleted, which ensures that the PDE (Photon Detection Efficiency) is improved). Regarding claim 9, Hasegawa discloses wherein the second substrate further includes a separation section that electrically separates adjacent ones of the pixels from each other, and the separation section is formed by the first first-conduction type layer extending, between the adjacent ones of the pixels, from the third surface toward the fourth surface([para 0204-0205]- hole storage layer 207 is disposed under the anode 205 between the separating layer 208 and the well 203 to be electrically coupled to the anode 205. The hole storage layer 207 is disposed at a portion in which different quality of materials comes in contact with each other. In other words, in an illustrated example, the separating layer 208 includes, for example, a silicon oxide film that is different from a constituent material of the well 203. Therefore, the hole storage layer 207 is provided to suppress a dark current that is generated on an interfacial surface between the separating layer 208 and the well 203). Regarding claim 10, Hasegawa discloses wherein the second substrate further includes a separation section that electrically separates adjacent ones of the pixels from each other, and the separation section includes a material having a light-blocking property([para 0204-0205]- hole storage layer 207 is disposed under the anode 205 between the separating layer 208 and the well 203 to be electrically coupled to the anode 205. The hole storage layer 207 is disposed at a portion in which different quality of materials comes in contact with each other. In other words, in an illustrated example, the separating layer 208 includes, for example, a silicon oxide film that is different from a constituent material of the well 203. Therefore, the hole storage layer 207 is provided to suppress a dark current that is generated on an interfacial surface between the separating layer 208 and the well 203). Regarding claim 11, Hasegawa discloses wherein the first first-conduction type layer further includes an extended section extending within the second substrate toward a middle of the pixel, the extended section having a first opening in the middle of the pixel, and the first conduction-type region is in contact with the extended section on the side of the fourth surface([see in Fig. 25 and para 0199-0201]- FIG. 25 illustrates an example of the backside illumination pixel (a pixel 230). With reference to a lower side of the drawing, in the pixel 230, an SPAD 221 is disposed on an on-chip lens 223; a sensor substrate 241 is disposed on the SPAD 221; and further a circuit substrate 242 is disposed on the sensor substrate 241. The SPAD 221 has an N-type semiconductor layer 201, a P-type semiconductor layer 202, a well 203, an anode 205, and a hole storage layer 207). Regarding claim 12, Hasegawa discloses wherein the first conduction-type region is formed within the second substrate over an entire surface of the pixel so as to be in contact with the first first-conduction type layer extending from the third surface toward the fourth surface([para 0204-0205]- hole storage layer 207 is disposed under the anode 205 between the separating layer 208 and the well 203 to be electrically coupled to the anode 205. The hole storage layer 207 is disposed at a portion in which different quality of materials comes in contact with each other. In other words, in an illustrated example, the separating layer 208 includes, for example, a silicon oxide film that is different from a constituent material of the well 203. Therefore, the hole storage layer 207 is provided to suppress a dark current that is generated on an interfacial surface between the separating layer 208 and the well 203). Regarding claim 13, Hasegawa discloses wherein the first conduction-type region has a second opening in a middle of the pixel([para 0193]- he plurality of light receiving elements 31 in the pixel array are disposed on the semiconductor substrate 110, and the elements and circuits other than the light receiving elements 31 in the pixel array are disposed on the semiconductor substrate 120; however, a configuration is not limited thereto. As an alternative, for example, the plurality of light receiving elements 31 and the plurality of resistor elements 32 in the pixel array may be disposed on the semiconductor substrate 110). Regarding claim 19, Hasegawa discloses wherein a condenser lens that condenses entering light onto the light receiving section is further provided at the first surface for each of the pixels([see in Fig. 1-2]- FIGS. 1 and 2, the description is provided on an overview of overall operation of the time measurement unit 1. The light-emitting section 11 performs light-emitting operation to emit light in timing depending on the light-emitting control signal C1. The diffusing lens 12 diffuses the light emitted from the light-emitting section 11 within a range of predetermined angles). Regarding claim 20, the claim is interpreted and rejected for the same reason as set forth in claim 1. Hence; all limitations for claim 20 have been met in claim 1. Hostetler discloses a distance measurement apparatus comprising ([para 0002]- method of determining the location of such objects is by time-of-flight (TOF) where light pulses are emitted from the sensor and the distance to the target is determined by the round trip time of the reflected pulse): an optical system ([para 0032]- One or more optical element structures 109), a photodetector ([see in Fig. 5]- a photodetector). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the technique of Hostetler to the modified system of Hasegawa a method to detect, and optionally to compensate, for the intrinsic noise in an isolated pixel in real time. In this way, the sensitivity of the system can be improved without further increasing the bias, or by increasing the signal-to-noise ratio at higher bias, thereby improving performance [Hostetler ;paragraph 0037] . 07-21-aia AIA Claim s 17, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa in view of Hostetler as applied to claim 1 above further in view of Lee et al.( US 2017/0179028 A1) . Regarding claim 17, the combination of Hasegawa and Hostetler do not exclusively disclose wherein the first substrate comprises a substrate including germanium, silicon germanium, and indium-gallium-arsenic. In an analogous art, Lee discloses wherein the first substrate comprises a substrate including germanium, silicon germanium, and indium-gallium-arsenic([see Fig. 30-31 and para 0148]- the substrate 10 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium-arsenic (GaAs), indium-gallium-arsenic (InGaAs), or aluminum-gallium-arsenic (AlGaAs)). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the technique of Lee to the modified system of Hasegawa and Hostetler a highly integrated 3D semiconductor memory device capable of improving an integration density[Lee ;paragraph 0004]. Claim 18, Lee discloses wherein the second substrate comprises a silicon substrate([see Fig. 30-31 and para 0148]- the substrate 10 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium-arsenic (GaAs), indium-gallium-arsenic (InGaAs), or aluminum-gallium-arsenic (AlGaAs)) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 14, The photodetector according to claim 8, further comprising: an impurity diffusion region formed at the first surface of the first substrate in an embedded manner and containing a first conduction-type impurity; and a second first-conduction type region provided around the impurity diffusion region, the second first-conduction type region penetrating through between the first surface and the second surface of the first substrate, the second first-conduction type region being electrically coupled to the first first-conduction type layer and having an impurity concentration lower than that of the impurity diffusion region. Citation of Pertinent Prior Art The prior art are made of record and not relied upon but considered pertinent to applicant’s disclosure: 1. Marshall et al., US 2005/0253132 A1, discloses photodetector circuits incorporating photodiode detectors and associated readout circuitry, and to methods of making such circuits and arrays incorporating such circuits. 2. Matsuda et al., US 2002/0158268 A1, discloses a photodetector and a unit mounted with a photodetector, and in particular relates to a photodetector that selectively receives signal light of a long wavelength (on the long wavelength side) when there is a plurality of incident signal lights of different wavelengths. 3. VON KAENEL, US 2019/0288026 A1, discloses pixel detectors made from monolithic, Complementary Metal Oxide Semiconductor (CMOS) integrated structures for the detection and imaging of electromagnetic radiation, and to methods for forming such structures. 4. YAGI et al., US 2016/0254310 A1, discloses a method of manufacturing the photodetector, a radiation detector, and a radiation detection apparatus. 5. HOSONO, US 2016/0380020 A1, discloses a photodetector and a method for manufacturing the photodetector. 6. WECKBECKER et al., US 2021/0351228 A1, a light-emitting device includes a multiplicity of light-emitting modules arranged on a first substrate . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MD NAZMUL HAQUE whose telephone number is (571)272-5328. The examiner can normally be reached IFW. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Czekaj can be reached at 5712727327. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MD N HAQUE/Primary Examiner, Art Unit 2487 Application/Control Number: 18/557,573 Page 2 Art Unit: 2487 Application/Control Number: 18/557,573 Page 3 Art Unit: 2487 Application/Control Number: 18/557,573 Page 4 Art Unit: 2487 Application/Control Number: 18/557,573 Page 5 Art Unit: 2487 Application/Control Number: 18/557,573 Page 6 Art Unit: 2487 Application/Control Number: 18/557,573 Page 7 Art Unit: 2487 Application/Control Number: 18/557,573 Page 8 Art Unit: 2487 Application/Control Number: 18/557,573 Page 9 Art Unit: 2487 Application/Control Number: 18/557,573 Page 10 Art Unit: 2487 Application/Control Number: 18/557,573 Page 11 Art Unit: 2487 Application/Control Number: 18/557,573 Page 12 Art Unit: 2487 Application/Control Number: 18/557,573 Page 13 Art Unit: 2487 Application/Control Number: 18/557,573 Page 14 Art Unit: 2487 Application/Control Number: 18/557,573 Page 15 Art Unit: 2487 Application/Control Number: 18/557,573 Page 16 Art Unit: 2487
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