DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is made in response to applicant’s amendment filed 02/19/2026. Claims 1-11, 13-16, 18 and 20-23 are currently pending in the application. Claims 9-11, 13-16, 18 and 20-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected groups II and III. Applicant timely traversed the Restriction requirement in the reply filed on 09/29/2025. Claims 1-8 are currently considered in the application. An action follows below:
Response to Arguments
The claim objection of claim 2 in the previous Office action dated 11/19/2025 has been withdrawn in light of the amendment to claim 2.
In response to the rejections under 35 U.S.C. 102(a)(1) and 35 U.S.C. 103 in the previous Office action, Applicant has amended independent claim 1 and provided on pages 12-14 of the amendment an argument, which has been considered but is not persuasive because, as necessitated by the amendment, Jang discloses the period/phase “SP” corresponding to the compensation phase of the currently amended claim 1 (see at least Fig. 3; ¶ 69.) See the detailed rejection of claim 1 made below.
Notice to Applicant(s)
Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968).
Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (US 2019/0180675 A1; hereinafter Jang.)
As per claim 1, Jang discloses a pixel circuit [P] comprising: a light-emitting element [ELD] and a pixel driving circuit [PC] (see at least Fig. 2,) wherein the pixel driving circuit comprises a driving circuit [a circuit including element Tdr; Fig. 2], a data writing circuit [a circuit including element Tsw1; Fig. 2], and a compensation control circuit [a circuit including element Tsw2; Fig. 2];
the data writing circuit is electrically connected to a write control line [SS], a data line [DL], and a control end of the driving circuit (see at least Fig. 2,) and the data writing circuit is configured to write a data voltage [Vdata] provided by the data line [DL] into the control end of the driving circuit under control of a write control signal provided by the write control line [SS] in a data writing phase [DWP] (see at least Figs. 2, 3; ¶ 72;)
the compensation control circuit is electrically connected to a compensation control line [SCS], a reference voltage line [RL], and the control end of the driving circuit (see at least Fig. 2,) and the compensation control circuit is configured to write a reference voltage [Vref] provided by the reference voltage line [RL] into the control end of the driving circuit under control of a compensation control signal [SCS] provided by the compensation control line [SCS] in a compensation phase [SP] (see at least Figs. 2, 3; ¶ 69;)
the driving circuit is electrically connected to the light-emitting element [ELD] (see at least Fig. 2,) and the driving circuit is configured to drive the light-emitting element (see at least Figs. 2, 3; ¶¶ 73-74;)
the data writing phase [DWP] does not overlap with the compensation phase [SP] (see at least Fig. 3;) and
in a timing sequence, a threshold voltage compensation process during the compensation phase [SP] does not occupy time for data writing during the data writing phase [DWP] (see at least Fig. 3; ¶ 69,) and the time for data writing phase [DWP] is longer than that for the compensation phase [SP] (see at least Fig. 3.)
As per claim 2, Jang discloses: wherein the pixel driving circuit further comprises a light-emitting control circuit [a circuit including element Tem; Fig. 2] (see at least Fig. 2;)
the light-emitting control circuit is electrically connected to a light-emitting control line [ECS], a first end of the driving circuit and a first voltage line [PL] (see at least Fig. 2,) and the light-emitting control circuit is configured to control a connection between the first end of the driving circuit and the first voltage line [PL] under control of a light-emitting control signal [ECS] provided by the light-emitting control line [ECS] (see at least Fig. 2;) and
a second end of the driving circuit is electrically connected to a first/anode electrode of the light-emitting element, and a second/cathode electrode of the light-emitting element is electrically connected to a second voltage line [VSS] (see at least Fig. 2.)
As per claim 3, Jang discloses: wherein the pixel driving circuit further comprises a reset circuit [a circuit including element Tini; Fig. 2] (see at least Fig. 2;)
the reset circuit is electrically connected to a reset control line [ICS], an initial voltage line [IL], and the second end of the driving circuit (see at least Fig. 2,) and the reset circuit is configured to write an initial voltage [Vini] provided by the initial voltage line [IL] into the second end of the driving circuit under control of a reset control signal [ICS] provided by the reset control line [ICS] in a reset phase [IP] (see at least Figs. 2, 3; ¶ 68.)
As per claim 4, Jang discloses: wherein at least a portion of a time period during which the light-emitting control circuit controls the first end of the driving circuit to be connected to the first voltage line does not overlap with the reset phase (see at least Figs. 2-3, disclosing that the time period [OVFP/SP/EP], during which the transistor Tem of the light-emitting control circuit activates and controls the first end of the driving circuit to be connected to the first voltage line [VDD], does not overlap with the reset phase [IP].)
As per claim 5, Jang discloses: wherein the pixel driving circuit further comprises an energy storage circuit [a circuit including element Cst; Fig. 2] (see at least Fig. 2;)
a first end of the energy storage circuit is electrically connected to the control end of the driving circuit, a second end of the energy storage circuit is electrically connected to the second end of the driving circuit, and the energy storage circuit is configured to store electric energy (see at least Fig. 2; ¶ 72.)
As per claim 6, Jang discloses: wherein the data writing circuit comprises a first transistor [Tsw1], the compensation control circuit comprises a second transistor [Tsw2], the reset circuit comprises a third transistor [Tini], the light-emitting control circuit comprises a fourth transistor [Tem], the driving circuit comprises a driving transistor [Tdr], and the energy storage circuit comprises a storage capacitor [Cst]; the light-emitting element [ELD] comprises an organic light-emitting diode (see at least ¶ 52;)
a gate electrode of the first transistor is electrically connected to the write control line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to a gate electrode of the driving transistor (see at least Fig. 2;)
a gate electrode of the second transistor is electrically connected to the compensation control line, a first electrode of the second transistor is electrically connected to the reference voltage line, and a second electrode of the second transistor is electrically connected to the gate electrode of the driving transistor (see at least Fig. 2;)
a gate electrode of the third transistor is electrically connected to the reset control line, a first electrode of the third transistor is electrically connected to the initial voltage line, and a second electrode of the third transistor is electrically connected to a second electrode of the driving transistor (see at least Fig. 2;)
a gate electrode of the fourth transistor is electrically connected to the light-emitting control line, a first electrode of the fourth transistor is electrically connected to the first voltage line, and a second electrode of the fourth transistor is electrically connected to a first electrode of the driving transistor (see at least Fig. 2;)
the second electrode of the driving transistor is electrically connected to an anode of the organic light-emitting diode, and a cathode of the organic light-emitting diode is electrically connected to the second voltage line (see at least Fig. 2;) and
a first plate of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second plate of the storage capacitor is electrically connected to the second electrode of the driving transistor (see at least Fig. 2.)
As per claim 7, Jang discloses a driving method applied to the pixel circuit according to claim 1 (see at least Fig. 3; ¶ 8,) wherein a displaying period [IP, SP, OVFP, DWP, EP] comprises the data writing phase [DWP] and the compensation phase [SP] (see at least Fig. 3;) the driving method comprises:
writing, in the data writing phase by the data writing circuit, the data voltage provided by the data line into the control end of the driving circuit under control of the write control signal (see at least Figs. 2, 3; ¶ 72;) and
writing, in the compensation phase by the compensation control circuit, the reference voltage provided by the reference voltage line into the control end of the driving circuit under control of the compensation control signal (see at least Figs. 2, 3; ¶ 69;); and
driving, by the driving circuit, the light-emitting element (see at least Figs. 2, 3; ¶¶ 73, 74;)
wherein the data writing phase [DWP] does not overlap with the compensation phase [SP] (see at least Fig. 3.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Kim et al. (US 2021/0065619 A1; hereinafter Kim.)
As per claim 8, Jang discloses: wherein the displaying period further comprises a light-emitting phase [EP] arranged after the data writing phase [DWP] and the compensation phase [SP] (see at least Fig. 3;) the pixel driving circuit further comprises a light-emitting control circuit [a circuit including element Tem; Fig. 2] (see at least Fig. 2;) the driving method comprises: controlling, in the light-emitting phase [EP] by the light-emitting control circuit, a first end of the driving circuit to be connected to a first voltage line [PL] under control of a light-emitting control signal [ECS] (see at least Figs. 2, 3; ¶¶ 73-74.)
Jang’s Fig. 3 shows, wherein in the light-emitting phase [EP], the light-emitting control signal ECS including a pulse having a width, but is silent to the light-emitting control signal [ECS] being a pulse width modulation (PWM) signal, as claimed.
However, in the same field of endeavor, Kim discloses, wherein in the light-emitting phase, the light-emitting control signal EM being a pulse width modulation (PWM) signal (see at least ¶ 64,) thereby controlling the luminance of light emitted from the light emitting element (see at least ¶ 69.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to utilize the light-emitting control signal being a pulse width modulation (PWM) signal, in view of the teaching in the Kim reference, to improve the above modified pixel circuit of the Jang reference for the predictable result of improving a control of the luminance of light emitted from the light emitting element.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jimmy H Nguyen whose telephone number is (571) 272-7675. The examiner can normally be reached on Monday-Friday 8:30AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Temesghen Ghebretinsae, can be reached at (571) 272-3017. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jimmy H Nguyen/
Primary Examiner, Art Unit 2626