DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This Office Action is in response to Applicant’s amendment filed on 5/26/2026.
Claims 1-20 are canceled. Claims 21-40 are pending.
Response to Amendment
Applicant’s amendments have fixed the deficiencies set forth in the previous Office Action hence the respective rejections/objections have been withdrawn, except for those rejections/objections if still maintained or newly added in this Office Action.
Independent claims 21, 31 and 37 have been amended to include new matter not fully disclosed in original disclosure. Therefore, the claims are rejected under 112(a) for lack of description. Please see details in the 112(a) rejection section.
Response to Arguments
Regarding Applicant’s arguments about the rejections for claims under 35 U.S.C § 102/103, the arguments have been fully considered.
Regarding Applicant’s arguments about the rejections for claim 21 under 35 U.S.C § 102, the arguments have been fully considered but are deemed moot, in view of new matter added which lacks sufficient description in the original disclosure.
Regarding rejections under 35 U.S.C § 103 for claims 22 and 23, Applicant argued in substance that (1) Wang does not teach “obtaining a processor temperature”; (2) temperature of the processor is different and significantly higher than that of the IO interface; (3) Wang and Anderson are not analogous art; (4) Anderson can not be combined into Wang since Wang “does not updated calibration parameters in real-time”.
As per point (1), Wang teaches in [0015] to obtain temperature of link component 102. Component 102 can not work without a processor with stored software to control its operations. As further evidenced by Wang’s teaching in [0010] that “Here, components 102 and 106 can be understood to include elements within an information handling system, such as components that are attached to one or more printed circuit board of the information handling system where link 100 represents a PCIe link”. So obtaining temperature of link component 102 teaches to obtain temperature of the processor controlling the operation of 102.
As per point (2), first, the IO interface is included in the processor (as recited in claim 21) so the temperatures of the IO interface and the processor are substantially the same; second, Applicant’s disclosure does not teach the temperature of the processor is different and significantly higher than that of the IO interface.
As per point (3), Wang and Anderson are analogous art since they both teach to recalibrate an electrical device when temperature changes to maintain the performance of the electrical device.
As per point (4), Wang teaches to recalibrate the IO interface in real-time when temperature changes, which involves updating the calibration parameters of the IO interface to compensate for the electrical changes resulted from the temperature change.
Regarding rejections under 35 U.S.C § 103 for claims 28 and 30, Applicant argued in substance that (1) Wang and Puthillathe can not combine since Puthillathe does no teach to use BMC to cause IO interface to retrain/recalibrate; (2) Puthillathe does no teach the reason to combine in [0004].
As per point (1), "A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton." (KSR, 550 U.S. at 421, 82 USPQ2d at 1397). Wang teaches to measure the temperature and generate a signal to trigger a recalibration of the IO interface. Although Wang is silent on the details of which function block is used to realize this function, this function/feature has been be implemented somewhere by an electrical module/block. Puthillathe teaches in FIG. 1 to use a BMC working together with a controller 116 and PCI device 120. BMC is famous for handling out-of-band signal, i.e., signals of low speed, to offload the high-speed processor. Since the temperature monitoring in Wang’s teaching does not require high speed processing, and since Puthillathe teaches a BMC working together with a controller 116 and PCI device 120, it is obvious to incorporate the BMC in Puthillathe’s teaching to handle the low-speed temperature monitoring function.
As per point (2), Puthillathe teaches in [0004] to provide out-of-band real-time management which involves using a BMC, which suggests to use a BMC to handle out-of-band real-time management, which fits the temperature monitoring in Wang.
Regarding Applicant’s arguments about the rejections for claims 31, 32, 33, 36, 37, 38 and 39 under 35 U.S.C § 103, the arguments have been fully considered but are deemed moot, in view of new matter added in claims 31 and 37 which lacks sufficient description in the original description.
Claim Objections
In claim 24, the limitation “in response to receiving a trigger for at least one of retraining and recalibrating the IO link; monitoring a link utilization level” should be amended to “in response to receiving a trigger for at least one of retraining and recalibrating the IO link[[;]], monitoring a link utilization level”, to correct the grammatical error.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 21-40 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
The amended independent claim 21 includes new limitations “A method for extending a dynamic temperature range of a processor including a first input-output (IO) interface coupled to a second IO interface of a device via an IO link, comprising: …., wherein the monitoring of the one or more of temperature, environmental, and workload conditions is not monitored at the first or second IO interfaces”. Although in independent claims 31 and 37, the recited “first IO interface” is between a host processor and a device (e.g. PCIe device), and the recited “second IO interface” is between the host processor and a BMC, here in claim 21 the recited “first” and “second” IO interface have to be interpreted differently to be meaningful. According to the recited limitations in claim 21, the “first IO interface” is included in the “processor”, the “second IO interface” is of a device, and the first and second IO interface is coupled via an IO link. Therefore, the amended claim 21 requires the first IO interface connects to the second IO interface of a device (e.g. PCIe device). Under this situation, the added limitation “wherein the monitoring of the one or more of temperature, environmental, and workload conditions is not monitored at the first or second IO interfaces” requires the monitoring does not happen at the first IO interface included in the host processor (nor at the second interface of the device), which introduces new matter not sufficiently disclosed before.
PNG
media_image1.png
688
928
media_image1.png
Greyscale
According to Applicant’s original disclosure in FIG. 1 and specification paragraph [0019]: “Host 104 includes a PCie PHY 114, an on-die digital thermal sensor (DTS) 116, …. BMC 106 receives measurements from DTS 116 over a Platform Environment Control Interface (PECI) 120”) and [0022]: “When a difference between Tc (Temperature at current time) and TT exceeds a dynamic temperature range threshold (TT- Tc> DTRTH), then BMC 106 can trigger Link retraining through 25 ASL”. Original disclosure teaches to measure weather/(ambient temperature) to decide an acceptable DTR temperature range (FIG. 1 and [0020]: “BMC 106 1s configured to monitor thermal related inputs 110 to determine and 10 characterize the temperature range at which Link Retrain has happened, and continuously measure current temperature for DTR to determine the acceptable DTR range, before which Link Retrain is to be initiated”), and then monitor current time temperature from the thermal sensor 116 and trigger a retraining if the temperature is beyond the determined acceptable DTR range. Since the temperature is monitored by DTS 116 on the host processor CPU comprising the first IO interface, therefore the monitoring is done at the first IO interface. The newly added limitation “wherein the monitoring of the one or more of temperature, environmental, and workload conditions is not monitored at the first or second IO interfaces” is not fully disclosed in the original disclosure, and actually contradicts the original disclosure.
In independent claims 31 and 37, the recited “first IO interface” is between a host processor and a device (e.g. PCIe device), and the recited “second IO interface” is between the host processor and a BMC. The newly added limitation “wherein the processor temperature is not monitored at the first IO interface” is not fully disclosed in the original disclosure, and actually contradicts the original disclosure, for the same reasons recited above.
All other claims are also rejected for the same reason since they depend on claims 21, 31 or 37 and have inhered the same deficiencies.
Claim Rejections - 35 USC § 102/103
Prior arts rejections can not be made due to the new matter added in claims 21, 31 and 37 which lack sufficient description in and actually contradict the original disclosure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES CAI whose telephone number is (571)272-7192. The examiner can normally be reached on M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamini Shah can be reached on 571-272-2279. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHARLES CAI/
Primary Patent Examiner, Art Unit 2115