DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20110012153 A1), and further in view of Fukumitsu et al. (US 20150108533 A1; hereinafter “Fukumitsu”) and Takada (US 2015/0147855 A1).
Kim teaches a semiconductor device comprising:
a substrate (a package body 10) having a first conductivity type and made of a single-crystal silicon (the package body 10 is a SOI (Silicon-On-Insulator) formed with p-type impurities) (Fig. 2 and paragraphs 44 and 47),
the substrate (a package body 10) having an upper surface and a lower surface on which thermally-oxidized films are formed (first dielectric layers 30a and 30b and second dielectric layer 40 can be formed on the surface of the first body 10a and the second body 10b by using a thermal oxidation method) (Fig. 2 and paragraph 53)
However, Kim doesn’t explicitly teach a first opening portion and a second opening portion being formed to be mutually spaced in the thermally-oxidized film formed on the lower surface, the substrate including a diode structure unit that includes a first well region and a second well region, the first well region being formed in a first region along the lower surface and being exposed at the first opening portion, the first ·well region having a second conductivity type different from the first conductivity type, the second well region being formed in a second region along the lower surface in the first region and being exposed at the second opening portion, the second well region having the first conductivity type; a semiconductor element disposed on the substrate and including a semiconductor layer; a first external electrode formed on a lower surface of the thermally-oxidized film and in contact with the first well region at the first opening portion; and a second external electrode formed on the lower surface of the thermally oxidized film, spaced from the first external electrode, and in contact with the second well region at the second opening portion, wherein the second well region extends to the first opening portion side exceeding a middle line between the first opening portion ,and the second opening portion along the lower surface of the substrate.
Fukumitsu teaches a semiconductor device comprising:
a first opening portion (an opening in insulating film 13B exposing a first diffusion regions 15A) and a second opening portion (an opening in insulating film 13B exposing a second diffusion regions 15B) being formed to be mutually spaced in a thermally-oxidized film formed on the lower surface (Fig. 2 and paragraphs 47), the substrate including a diode structure unit (a semiconductor element portion 15 including the first diffusion region 15A and the second diffusion region 15B configures the Zener diode 3) that includes a first well region (the semiconductor element portion 15 includes an n-type semiconductor region) having a low impurity concentration) (Fig. 2, Fig. 3 and paragraph 57), the first well region being formed in a first region along the lower surface and being exposed at the first opening portion (the semiconductor element portion 15 that includes n-type semiconductor region is shown exposed by the opening in insulating film 13B over the first diffusion region 15A in Fig. 2), the first-well region having a second conductivity type different from the first conductivity type (the first diffusion region 15A is an n-type semiconductor region (n+)) (Fig. 3 and paragraph 57), the second well region being formed in a second region along the lower surface in the first region and being exposed at the second opening portion (the second diffusion region 15B is shown in a region within the semiconductor element portion 15 that includes n-type semiconductor region and exposed by the opening in insulating film 13B in Fig. 2), the second well region having the first conductivity type (the second diffusion region 15B is a p-type semiconductor region (p+)) (Fig. 3 and paragraph 57); a semiconductor element (an LED element 2) disposed on the substrate and including a semiconductor layer (the LED element 2 includes a semiconductor compound layer 22) (Fig. 2 and paragraph 41); a first external electrode (a first wiring electrode 18A) formed on a lower surface of the thermally-oxidized film and in contact with the first well region at the first opening portion (the first wiring electrode 18A is shown in contact with the semiconductor element portion 15 at the opening in the insulating film 13B containing the first diffusion region 15A) (Fig. 2A and paragraph 44); and a second external electrode (a second wiring electrode 18B) formed on the lower surface of the thermally oxidized film (the second wiring electrode 18B is shown on the bottom surface of the insulating film 13B in Fig. 2), spaced from the first external electrode, and in contact with the second well region at the second opening portion (the second wiring electrode 18B is shown in contact with the second diffusion region 15B at the opening in the insulating film 13B in Fig. 2).
It would have been obvious to one skilled in the art to combine the teachings of Fukumitsu with the teachings of Kim to have a first opening portion and a second opening portion being formed to be mutually spaced in the thermally-oxidized film formed on the lower surface, the substrate including a diode structure unit that includes a first well region and a second well region, the first well region being formed in a first region along the lower surface and being exposed at the first opening portion, the first ·well region having a second conductivity type different from the first conductivity type, the second well region being formed in a second region along the lower surface in the first region and being exposed at the second opening portion, the second well region having the first conductivity type; a semiconductor element disposed on the substrate and including a semiconductor layer; a first external electrode formed on a lower surface of the thermally-oxidized film and in contact with the first well region at the first opening portion; and a second external electrode formed on the lower surface of the thermally oxidized film, spaced from the first external electrode, and in contact with the second well region at the second opening portion since this allows for a light-emitting device according with a semiconductor-based electrostatic discharge protection element as taught by Fukimitsu (paragraph 25).
Takada teaches a semiconductor device (a semiconductor device containing a normal Zener diode (ZD) formation region) (Fig. 2S and paragraph 41), comprising:
a second well region (an n-type wells 4) extends to a first opening portion (annotated as 1st OP in annotated Fig. 2S below) side exceeding a middle line (annotated as ML in Fig. 2s below) between the first opening portion and a second opening portion (annotated as 2nd OP in annotated Fig. 2S below) along the lower surface of the substrate (the n-type wells 4 is shown extending towards the first opening 1st OP passing the middle line ML across a surface of the substrate in annotated Fig. 2S below. The Examiner takes official notice that due the surface of the device being a preferred orientation and not a required orientation, the top surface of the substrate can function as the bottom of surface of the substrate.) (Fig. 2J, annotated Fig. 2S and paragraphs 49 and 51).
It would have been an obvious to one having ordinary skill in the art at the time the invention was made to combine the teachings of Kim with the teachings of Takada to have the second well region extend to the first opening portion side exceeding a middle line between the first opening portion, and the second opening portion along the lower surface of the substrate, since the examiner takes Office Notice of the equivalence of the top surface of the substrate and the bottom surface of the substrate can function as presented in the claims for their use in the art and the selection of any of these known equivalents to a normal Zener diode for protection of transistors as taught by Takada (paragraph 68), would be within the level of ordinary skill in the art.
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In regard to claim 3, Kim in view of Fukumitsu teaches wherein the second well region has a high concentration well region in one region facing the second opening portion, and a carrier density is higher in the one region than in another region (the second diffusion region 15B having a high impurity concentration and would have a higher carrier density than semiconductor element portion 15 having a low impurity concentration) (paragraph 57).
In regard to claim 4, Kim teaches wherein a diode structure unit is a Zener diode (Zener diodes 20a) or an avalanche diode (Fig. 2 and paragraph 42).
In regard to claim 6, Kim teaches wherein the substrate is formed by bonding a plate-shaped first substrate (a second body 10b) and a second substrate (a first body 10a) (Fig. 2 and paragraph 43), the first substrate has the first conductivity type and is made of a single-crystal silicon (the second body 10b is SOI (Silicon-On-Insulator) formed with p-type impurities) (paragraphs 44 and 47), the second substrate is disposed on the first substrate and provided with an opening having an inner side surface that forms a recessed portion with an upper surface of the first substrate (the first body 10a is shown with a recess between a side surface and upper surface of the second body 10b in Fig. 2), and an oxidized film is formed on a surface in the second substrate side of the first substrate (first dielectric layers 30a and 30b and second dielectric layer 40 can be formed on the surface of the first body 10a and the second body 10b by using a thermal oxidation method) (Fig. 2 and paragraph 53).
In regard to claim 7, Kim in view of Fukumitsu teaches wherein a semiconductor element (a light emitting element 100) includes a pair of electrodes on a lower surface thereof (a first electrode 51 and a second electrode 52 are shown on the bottom of the light emitting element 100 in Fig. 2) (Fig. 2 and paragraph 42),
the substrate is provided with a plurality of through holes penetrating from a bottom surface of the recessed portion to a back surface of the substrate in columnar shapes (a groove 81 serves as a channel to connect the first top electrode 51a to the first bottom electrode 51b and a groove 82 that serves as a channel to connect the second top electrode 52a to the second bottom electrode 52b are formed) (Fig. 2 and paragraph 59), and inner side surfaces of the plurality of through holes are covered with the thermally-oxidized film (first dielectric layers 30a are shown on the side surfaces of the grooves 81 and 82) (Fig. 2),
a plurality of columnar through electrodes (portions of the first electrode 51 and second electrode 52 in the grooves 81 and 82 as shown in Fig. 2) are formed in the plurality of through holes (Fig. 2), and the plurality of through electrodes fill the plurality of through holes of the substrate and project from the bottom surface (portions of the first electrode 51 and second electrode 52 in the grooves 81 and 82 and project through the bottom surface as shown in Fig. 2), and
the plurality of through electrodes electrically connect the pair of respective electrodes of the semiconductor element to the first external electrode and the second external electrode (the groove 81 serves as a channel to connect the first top electrode 51a to the first bottom electrode 51b and the groove 82 that serves as a channel to connect the second top electrode 52a to the second bottom electrode 52b are formed) (Fig. 2 and paragraph 59).
In regard to claim 10, Kim teaches wherein the semiconductor element is a light-emitting element that emits an ultraviolet light from the semiconductor layer (the light emitting element 100 emits light with UV wavelength) (paragraph 69).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Fukumitsu and Takada, and further in view of Takizawa et al. (JP 2014110332 A; hereinafter “Takizawa”).
In regard to claim 5, Kim in view of Fukumitsu and Takada don’t explicitly teach wherein the first well region is doped with boron, and the second well region is doped with phosphorus.
Takizawa teaches a semiconductor device (a semiconductor light emitting device 10), wherein the first well region is doped with boron, and the second well region is doped with phosphorus (the P-type diffusion layer 11 is a layer in which boron (B) is doped in one half (the right half in FIG. 1) a N-type diffusion layer 12 is doped with phosphorus (P)) (Fig. 1 and paragraphs 19-20).
It would have been obvious to one skilled in the art to combine the teachings of Kim in view of Fukumitsu and Takada with the teachings of Takizawa to have the first well region is doped with boron, and the second well region is doped with phosphorus since Boron and phosphorus are well known N-type and P-type dopants and it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim Objections
Claims 2 and 8-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regard to claim 2, Kim is considered a close prior art of record. However, Kim fails to teach the first external electrode and the second external electrode each include a titanium seed layer, a copper seed layer, and a nickel plated layer laminated in an order. While Kim teaches that the electrodes can be formed of said materials there is no teaching to suggest the order of materials used in the electrode.
In regard to claim 8, Kim is considered a close prior art of record. However, Kim fails to teach wherein the plurality of through electrodes are disposed at respective lattice points of an equilateral triangular grid on the bottom surface of the recessed portion. Kim is silent to the regard of the layout of the elements mapped as the through electrodes.
In regard to claim 9, Kim is considered a close prior art of record. However, Kim fails to teach lid member made of a glass and being bonded to the upper surface of the substrate via a fritted glass layer, wherein at a bonding portion of the substrate and the fritted glass layer, the thermally-oxidized film and a reaction layer of the thermally-oxidized film and the fritted glass layer are formed in an order thereof from a surface of the substrate between the substrate and the fritted glass layer. Kim is silent to the regard of a lid or fritted glass used as an adhesive to secure said lid.
Allowable Subject Matter
Claims 11-17 are allowed.
The following is the Office's statement of reasons for allowance:
Regarding claim 11 , the prior art of record, taken alone or in combination, fails to teach or suggest:
A method for manufacturing a semiconductor device, comprising: a step of preparing a substrate having a first conductivity type and made of a single- crystal silicon; a first diffusion step of forming a first well region having a second conductivity type different from the first conductivity type in a first region along a lower surface of the substrate; a second diffusion step of forming a second well region having the first conductivity type in a second region along the lower surface of the substrate in the first region; a thermally-oxidized film formation step of forming a thermally-oxidized film on the lower surface of the substrate, the thermally-oxidized film being provided with a first opening portion at which the first well region is exposed and a second opening portion at which the second well region is exposed; and an external electrode formation step of forming a first external electrode and a second external electrode on a lower surface of the thermally-oxidized film, the first external electrode being in contact with the first well region at the first opening portion, and the second external electrode being spaced from the first external electrode and in contact with the second well region at the second opening portion, wherein in the second diffusion step, the second well region is formed to extend to the first opening portion side exceeding a middle line between the first opening portion and the second opening portion along the lower surface of the substrate.
Kim is considered a close prior art of record. However, Kim fails to teach the method of manufacturing the device as taught in the claims. Kim teaches the thermally oxidized films are formed prior to the well regions.
As such, modification of the prior art of record can only be motivated by hindsight reasoning, or by changing the intended use and function of the prior art themselves. Therefore, it is not clear that one of ordinary skill in the art at the time of the invention would have made the necessary modifications to the prior art of record to encompass the limitations set forth in the present application. Moreover, none of the prior arts of record, taken either alone or in combination, anticipate nor render obvious the claimed inventions. Hence, claims 11-17 are allowable over the prior arts of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893